M36DR432AD10ZA6T ,32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory ProductBlock Diagram 10Table 2. Main Operation Modes . . . 11FLASH MEMORY COMPONENT . . ..
M36L0R7050B0ZAQ ,128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip PackageAbsolute Maximum Ratings . . . . . . . 11DC AND AC PARAMETERS . 12Table 5. Operating and ..
M36L0R7060T1ZAQF , 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package
M36L0R8060T1ZAQE , 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
M36L0T7050B2ZAQF , 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
M36L0T7050T2ZAQF , 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
M54585KP , 8-UNIT 500mA DARLINGTON TRANSISTOR-ARRAY WITH CLAMP DIODE
M54587FP , 8-UNIT 500mA DARLINGTON TRANSISTOR ARRAY WITH CLAMP DIODE
M54587FP , 8-UNIT 500mA DARLINGTON TRANSISTOR ARRAY WITH CLAMP DIODE
M54641L , Bi-DIRECTIONAL MOTOR DRIVER WITH BRAKE FUNCTION
M54641L , Bi-DIRECTIONAL MOTOR DRIVER WITH BRAKE FUNCTION
M54678FP , 2-PHASE STEPPER MOTOR DRIVER
M36DR432AD10ZA6T
32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product
1/52February 2003
M36DR432AD
M36DR432BD32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory
and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARYMultiple Memory Product1 bank of 32 Mbit (2Mb x16) Flash Memory1 bank of 4 Mbit (256Kb x16) SRAMSUPPLY VOLTAGE
–VDDF = VDDS =1.65V to 2.2V
–VPPF = 12V for Fast Program (optional)ACCESS TIMES: 85ns, 100ns, 120nsLOW POWER CONSUMPTIONELECTRONIC SIGNATUREManufacturer Code: 0020hTop Device Code, M36DR432AD: 00A0hBottom Device Code, M36DR432BD: 00A1h
FLASH MEMORYMEMORY BLOCKSDual Bank Memory Array: 4 Mbit, 28 MbitParameter Blocks (Top or Bottom location) PROGRAMMING TIME10μs by Word typicalDouble Word Program OptionASYNCHRONOUS PAGE MODE READPage Width: 4 WordsPage Access: 35nsRandom Access: 85ns, 100ns, 120nsDUAL BANK OPERATIONSRead within one Bank while Program or
Erase within the otherNo delay between Read and Write operationsBLOCK LOCKINGAll blocks locked at Power upAny combination of blocks can be locked
–WPF for Block Lock-DownCOMMON FLASH INTERFACE (CFI)64 bit Unique Device Identifier 64 bit User Programmable OTP Cells
Figure 1. PackageERASE SUSPEND and RESUME MODES100,000 PROGRAM/ERASE CYCLES per
BLOCK20 YEARS DATA RETENTIONDefectivity below 1ppm/year
SRAM4 Mbit (256Kb x16)LOW VDDS DATA RETENTION: 1.0VPOWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
M36DR432AD, M36DR432BD
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Flash Reset/Power-Down (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VDDF Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VPPF Programming Voltage (11.4V to 12.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VSSF Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
SRAM Chip Enable (ES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SRAM Upper Byte Enable (UBS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VDDS Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
FLASH MEMORY COMPONENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 5. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . .13
Flash Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Flash Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Flash Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Flash Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Flash Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Automatic Flash Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Flash Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Dual Bank Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Flash Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Flash Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3/52
M36DR432AD, M36DR432BDAuto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Quadruple Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Enter Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Exit Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Double Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Quadruple Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Lock-Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Bank Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Erase Suspend Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 5. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 6. Flash Read Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 7. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 9. Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . .19
Flash Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 10. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 12. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
M36DR432AD, M36DR432BDStandby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 13. Absolute Maximum Ratings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 14. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 15. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 16. Flash DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 17. SRAM DC Characteristics (TA = –40 to 85°C; VDDF = VDDS = 1.65V to 2.2V) . . . . . . . .28
Figure 8. Flash Random Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 9. Flash Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 18. Flash Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 10. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 20. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 12. Flash Reset/Power-Down AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 21. Flash Reset/Power-Down AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 13. Flash Data Polling DQ7 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 22. Flash Data Polling and Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 15. Flash Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 16. Flash Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL . . . . . .38
Figure 18. SRAM Read AC Waveforms, ES or GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 23. SRAM Read AC Characteristics). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . .40
Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High. . . . . . . . . . . . . . . . . . . . . .40
Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . .41
Figure 23. SRAM Write AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 24. SRAM Low VDDS Data Retention AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . .42
Table 25. SRAM Low VDDS Data Retention Characteristics (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . .43
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline44
Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . . .44
5/52
M36DR432AD, M36DR432BD
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Table 27. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
APPENDIX A. BLOCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Table 28. Bank A, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 29. Bank B, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD. . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD. . . . . . . . . . . . . . . . . . . . . . . . . .47
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48Table 32. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 33. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 34. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 35. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51Table 36. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
M36DR432AD, M36DR432BD
SUMMARY DESCRIPTIONThe M36DR432AD/BD is a low-voltage Multiple
Memory Product which combines two memory de-
vices: a 32 Mbit (2Mbit x16) non-volatile Flash
memory and a 4 Mbit SRAM.
The memory is available in a Stacked LFBGA66
12x8mm - 8x8 active ball array, 0.8mm pitch pack-
age and supplied with all the bits erased (set to
‘1’).
Figure 2. Logic Diagram
Table 1. Signal Names
7/52
M36DR432AD, M36DR432BD
M36DR432AD, M36DR432BD
SIGNAL DESCRIPTIONSSee Figure 2 Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17).Addresses A0-A17
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. During a write oper-
ation, the address inputs for the Flash memory are
latched on the falling edge of the Flash Chip En-
able (EF) or Write Enable (WF), whichever occurs
last, whereas for the SRAM array they are latched
on the falling edge of the SRAM Chip Enable lines
(E1S or E2S) or Write Enable (WS). In the rest of
the datasheet, only the Active Low SRAM Chip
Enable line will be discussed. It will be referred to
as ES.
Address Inputs (A18-A20).Addresses A18-A20
are inputs for the Flash component only. They are
latched during a write operation on the falling edge
of Flash Chip Enable (EF) or Write Enable (WF),
whichever occurs last.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Write Bus op-
eration.
The input is data to be programmed in the Flash or
SRAM memory array or a command to be written
to the C.I. of the Flash memory. Both are latched
on the rising edge of Flash Write Enable (WF) and,
SRAM Chip Enable lines (ES) or Write Enable
(WS). The output is data from the Flash memory
array or SRAM array, the Electronic Signature
Manufacturer or Device codes, the Block Protec-
tion status, the Configuration Register status or
the Status Register Data (Polling bit DQ7, Toggle
bits DQ6 and DQ2, Error bit DQ5 or Erase Timer
bit DQ3) depending on the address. Outputs are
valid when Flash Chip Enable (EF) and Output En-
able (GF) or SRAM Chip Enable lines (ES) and
Output Enable (GS) are active.
The output is high impedance when both the Flash
chip and the SRAM chip are deselected or the out-
puts are disabled and when Reset (RPF) is at VIL.
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at VIH the memory is deselected
and the power consumption is reduced to the
standby level.
Flash Output Enable (GF). gates the outputs
through the data buffers during a read operation.
When Output Enable, GF, is at VIH the outputs are
High impedance.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memory’s Command Interface.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each Flash block. When Write Protect is at VIL,
the locked-down blocks cannot be locked or un-
locked. When Write Protect is at VIH, the Lock-
Down is disabled and the Locked-Down blocks
can be locked or unlocked. Refer to Table 8, Read
Protection Register.
Flash Reset/Power-Down (RPF). The Reset/
Power-Down input provides hardware reset of the
Flash memory, and/or Power-Down functions, de-
pending on the Flash Configuration Register sta-
tus. Reset or Power-Down of the memory is
achieved by pulling RPF to VIL for at least tPLPH.
The Reset/Power-Down function is set in the Con-
figuration Register (see Set Configuration Regis-
ter Command). If it is set to ‘0’ the Reset function
is enabled, if it is set to ‘1’ the Power-Down func-
tion is enabled. After a Reset or Power-Up the
power save function is disabled and all blocks are
locked.
The memory Command Interface is reset on Pow-
er Up to Read Array. Either Chip Enable or Write
Enable must be tied to VIH during Power Up to al-
low maximum security and the possibility to write a
command on the first rising edge of Write Enable.
After a Reset, when the device is in Read, Erase
Suspend Read or Standby, valid data will be out-
put tPHQ7V1 after the rising edge of RPF. If the de-
vice is in Erase or Program, the operation will be
aborted and the reset recovery will take a maxi-
mum of tPLQ7V. The memory will recover from Re-
set/Power-Down tPHQ7V2 after the rising edge of
RPF. See Tables 18 and 19, and Figure 12.
VDDF Supply Voltage (1.65V to 2.2V).VDDF pro-
vides the power supply to the internal core and I/O
pins of the memory device. It is the main power
supply for all operations (read, program and
erase).
VPPF Programming Voltage (11.4V to 12.6V).VPPF provides a high voltage power supply for fast
factory programming. VPPF is required to use the
Double Word and Quadruple Word Program com-
mands.
VSSF Ground.VSSF ground is the reference for
the core supply. It must be connected to the sys-
tem ground.
SRAM Chip Enable (ES).The Chip Enable in-
puts for SRAM activate the memory control logic,
input buffers and decoders. ES at VIH deselects
9/52
M36DR432AD, M36DR432BDthe memory and reduces the power consumption
to the standby level. ES can also be used to con-
trol writing to the SRAM memory array, while WS
remains at VIL. It is not allowed to set EF at VIL and
ES at VIL at the same time.
SRAM Write Enable (WS).The Write Enable in-
put controls writing to the SRAM memory array.
WS is active Low.
SRAM Output Enable (GS).The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM chip. GS is active
Low.
SRAM Upper Byte Enable (UBS).Enables the
upper bytes for SRAM (DQ8-DQ15). UBS is active
Low.
SRAM Lower Byte Enable (LBS). Enables the
lower bytes for SRAM (DQ0-DQ7). LBS is active
Low.
VDDS Supply Voltage (1.65V to 2.2V).VDDS is the
SRAM power supply for all operations.
Note: Each device in a system should have
VDDF and VPPF decoupled with a 0.1μF capaci-
tor close to the pin. See Figure 7, AC Measure-
ment Load Circuit. The PCB trace widths
should be sufficient to carry the required VPPF
program and erase currents.
M36DR432AD, M36DR432BD
FUNCTIONAL DESCRIPTIONThe Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF for the Flash mem-
ory and ES (E1S and E2S, respectively) for the
SRAM.
Figure 4. Functional Block Diagram
11/52
M36DR432AD, M36DR432BD
Table 2. Main Operation ModesNote:1.X = Don’t care (VIL or VIH).If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
M36DR432AD, M36DR432BD
FLASH MEMORY COMPONENTThe Flash Memory is a 32 Mbit (2Mbit x16) non-
volatile Flash memory that may be erased electri-
cally at block level and programmed in-system on
a Word-by-Word basis using a 1.65V to 2.2V VDDF
supply for the circuitry and a 1.65V to 2.2V VDDQF
supply for the Input/Output pins (in the stacked de-
vice, VDDF and VDDQF are tied internally). An op-
tional 12V VPPF power supply is provided to speed
up customer programming.
The Flash device features an asymmetrical block
architecture with an array of 71 blocks divided into
two banks, Banks A and B, providing Dual Bank
operations. While programming or erasing in Bank
A, read operations are possible in Bank B or vice
versa. Only one bank at a time is allowed to be in
program or erase mode. The bank architecture is
summarized in Table 3, and the Block Addresses
are shown in Appendix A. The Parameter Blocks
are located at the top of the memory address
space for the M36DR432AD and, at the bottom for
the M36DR432BD.
Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Each block can be programmed and erased over
100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The Flash memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have two
levels of protection. They can be individually
locked and locked-down preventing any acciden-
tal programming or erasure. All blocks are locked
at Power Up and Reset.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system’s design. The Protection Register is di-
vided into two 64 bit segments. The first segment
contains a unique device number written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user. Figure 5, shows the Flash Security Block
and Protection Register Memory Map.
Table 3. Flash Bank Architecture
13/52
M36DR432AD, M36DR432BD
Figure 5. Flash Security Block and Protection Register Memory Map
Flash Bus OperationsThe following operations can be performed using
the appropriate bus cycles: Flash Read Array
(Random and Page Modes), Flash Write, Flash
Output Disable, Flash Standby and Flash Reset/
Power-Down, see Table 2, Main Operation
Modes.
Flash Read.Flash Read operations are used to
output the contents of the Memory Array, the Elec-
tronic Signature, the Status Register, the CFI, the
Block Protection Status or the Configuration Reg-
ister status. Read operation of the Flash memory
array is performed in asynchronous page mode,
that provides fast access time. Data is internally
read and stored in a page buffer. The page has a
size of 4 words and is addressed by A0-A1 ad-
dress inputs. Read operations of the Electronic
Signature, the Status Register, the CFI, the Block
Protection Status, the Configuration Register sta-
tus and the Security Code are performed as single
asynchronous read cycles (Random Read). Both
Flash Chip Enable EF and Flash Output Enable
GF must be at VIL in order to read the output of the
memory.
Flash Write.Write operations are used to give
commands to the memory or to latch Input Data to
be programmed. A write operation is initiated
when Chip Enable EF and Write Enable WF are at
VIL with Output Enable GF at VIH. Addresses are
latched on the falling edge of WF or EF whichever
occurs last. Commands and Input Data are
latched on the rising edge of WF or EF whichever
occurs first. Noise pulses of less than 5ns typical
on EF, WF and GF signals do not start a write cy-
cle.
Flash Output Disable.The data outputs are high
impedance when the Output Enable GF is at VIH
with Write Enable WF at VIH.
Flash Standby.The memory is in standby when
Chip Enable EF is at VIH and the P/E.C. is idle.
The power consumption is reduced to the standby
level and the outputs are high impedance, inde-
pendent of the Output Enable GF or Write Enable
WF inputs.
Automatic Flash Standby.In Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus.
Flash Power-Down.The memory is in Power-
Down when the Configuration Register is set for/
Power-Down and RPF is at VIL. The power con-
sumption is reduced to the Power-Down level, and
Outputs are high impedance, independent of the
Chip Enable EF, Output Enable GF or Write En-
able WF inputs.
Dual Bank Operations.The Dual Bank allows
data to be read from one bank of memory while a
program or erase operation is in progress in the
other bank of the memory. Read and Write cycles
can be initiated for simultaneous operations in dif-
ferent banks without any delay. Status Register
during Program or Erase must be monitored using
an address within the bank being modified.
Flash Command InterfaceAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
M36DR432AD, M36DR432BDdles all timings and verifies the correct execution
of the Program and Erase commands. Two bus
write cycles are required to unlock the Command
Interface. They are followed by a setup or confirm
cycle. The increased number of write cycles is to
ensure maximum data security.
The Program/Erase Controller provides a Status
Register whose output may be read at any time to
monitor the progress or the result of the operation.
The Command Interface is reset to Read mode
when power is first applied or exiting from Reset.
Command sequences must be followed exactly.
Any invalid combination of commands will reset
the device to Read mode
Flash Read/Reset Command.The Read/Reset
command returns the device to Read mode. One
Bus Write cycle is required to issue the Read/Re-
set command and return the device to Read mode.
Subsequent Read operations will read the ad-
dressed location and output the data. The write cy-
cle can be preceded by the unlock cycles but it is
not mandatory.
Flash Read CFI Query Command.The Read
CFI Query command is used to read data from the
Common Flash Interface (CFI) and the Electronic
Signature (Manufacturer or the Device Code, see
Table 5). The Read CFI Query Command consists
of one Bus Write cycle. Once the command is is-
sued the device enters Read CFI mode. Subse-
quent Bus Read operations read the Common
Flash Interface or Electronic Signature. Once the
device has entered Read CFI mode, only the
Read/Reset command should be used and no oth-
er. Issuing the Read/Reset command returns the
device to Read mode.
See Appendix B, Common Flash Interface, Tables
33, 34, and 35 for details on the information con-
tained in the Common Flash Interface memory ar-
ea.
Auto Select Command.The Auto Select com-
mand uses the two unlock cycles followed by one
write cycle to any bank address to setup the com-
mand. Subsequent reads at any address will out-
put the Block Protection status, Protection
Register and Protection Register Lock or the Con-
figuration Register status depending on the levels
of A0 and A1 (see Tables 6, 7 and 8). Once the
Auto Select command has been issued only the
Read/Reset command should be used and no oth-
er. Issuing the Read/Reset command returns the
device to Read mode.
Set Configuration Register Command.The
Flash component contains a Configuration Regis-
ter, see Table 7, Configuration Register.
It is used to define the status of the Reset/Power-
Down functions. The value for the Configuration
Register is always presented on A0-A15, the other
address bits are ignored. Address input A10 de-
fines the status of the Reset/Power-Down func-
tions. If it is set to ‘0’ the Reset function is enabled,
if it is set to ‘1’ the Power-Down function is en-
abled. At Power Up the Configuration Register bit
is set to ‘0’.
The Set Configuration Register command is used
to write a new value to the Configuration Register.
The command uses the two unlock cycles followed
by one write cycle to setup the command and a
further write cycle to write the data and confirm the
command.
Program Command.The Program command
uses the two unlock cycles followed by a write cy-
cle to setup the command and a further write cycle
to latch the Address and Data and start the Pro-
gram Erase Controller. Read operations within the
same bank output the Status Register after pro-
gramming has started.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole bank from ’0’ to ’1’. If the Program
command is used to try to set a bit from ‘0’ to ‘1’
Status Register Error bit DQ5 will be set to ‘1’, only
if VPPF is in the range of 11.4V to 12.6V.
Double Word Program Command.This feature
is offered to improve the programming throughput
by writing a page of two adjacent words in parallel.
The VPPF supply voltage is required to be from
11.4V to 12.6V for the Double Word Program com-
mand.
The command uses the two unlock cycles followed
by a write cycle to setup the command. A further
two cycles are required to latch the address and
data of the two Words and start the Program Erase
Controller.
The addresses must be the same except for the
A0. The Double Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Double Word Program command
cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Double Word Program command is used to try to
set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5
will be set to ‘1’.
Quadruple Word Program Command.The
Quadruple Word Program command improves the
programming throughput by writing a page of four
adjacent words in parallel. The four words must
differ only for the addresses A0 and A1. The VPPF
supply voltage is required to be from 11.4V to
12.6V for the Quadruple Word Program com-
mand.
15/52
M36DR432AD, M36DR432BDThe command uses the two unlock cycles followed
by a write cycle to setup the command. A further
four cycles are required to latch the address and
data of the four Words and start the Program
Erase Controller.
The Quadruple Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Quadruple Word Program command
cannot change a bit set to ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Quadruple Word Program command is used to try
to set a bit from ‘0’ to ‘1’ Status Register Error bit
DQ5 will be set to ‘1’.
Enter Bypass Mode Command.The Bypass
mode is used to reduce the overall programming
time when large memory arrays need to be pro-
grammed.
The Enter Bypass Mode command uses the two
unlock cycles followed by one write cycle to set up
the command. Once in Bypass mode, it is impera-
tive that only the following commands be issued:
Exit Bypass, Program, Double Word Program or
Quadruple Word Program.
Exit Bypass Mode Command.The Exit Bypass
Mode command uses two write cycles to setup
and confirm the command. The unlock cycles are
not required. After the Exit Bypass Mode com-
mand, the device resets to Read mode.
Program in Bypass Mode Command.The
Program in Bypass Mode command can be is-
sued when the device is in Bypass mode (issue a
Enter Bypass Mode command). It uses the same
sequence of cycles as the Program command with
the exception of the unlock cycles.
Double Word Program in Bypass Mode Com-
mand.The Double Word Program in Bypass
Mode command can be issued when the device is
in Bypass mode (issue a Enter Bypass Mode com-
mand). It uses the same sequence of cycles as the
Double Word Program command with the excep-
tion of the unlock cycles.
Quadruple Word Program in Bypass Mode
Command.The Quadruple Word Program in By-
pass Mode command can be issued when the de-
vice is in Bypass mode (issue a Enter Bypass
Mode command). It uses the same sequence of
cycles as the Quadruple Word Program command
with the exception of the unlock cycles.
Block Lock Command.The Block Lock com-
mand is used to lock a block and prevent Program
or Erase operations from changing the data in it.
All blocks are locked at power-up or reset.
Three Bus Write cycles are required to issue the
Block Lock command. The first two bus cycles unlock the Command
Interface. The third bus cycle sets up the Block Lock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the Lock Status after issuing a Block Lock com-
mand.
The Block Lock bits are volatile, once set they re-
main set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.
Block Unlock Command.The Blocks Unlock
command is used to unlock a block, allowing the
block to be programmed or erased.
Three Bus Write cycles are required to issue the
Blocks Unlock command. The first two bus cycles unlock the Command
Interface. The third bus cycle sets up the Block UnLock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the lock status after issuing a Block Unlock com-
mand. Refer to the section, Block Locking, for a
detailed explanation.
Block Lock-Down Command.A locked or un-
locked block can be locked-down by issuing the
Block Lock-Down command. A locked-down block
cannot be programmed or erased, or have its pro-
tection status changed when WPF is Low, VIL.
When WPF is High, VIH, the Lock-Down function is
disabled and the locked blocks can be individually
unlocked by the Block Unlock command.
Three Bus Write cycles are required to issue the
Block Lock-Down command. The first two bus cycles unlock the Command
Interface. The third bus cycle sets up the Block Lock-
Down command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Locked-Down
blocks revert to the locked (and not locked-down)
state when the device is reset on power-down. Ta-
ble 10 shows the Lock Status after issuing a Block
Lock-Down command. Refer to the section, Block
Locking, for a detailed explanation.
Block Erase Command.The Block Erase com-
mand can be used to erase a block. It sets all the
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the device will return
to Read Array mode. It is not necessary to pre-pro-
M36DR432AD, M36DR432BDgram the block as the Program/Erase Controller
does it automatically before erasing.
Six Bus Write cycles are required to issue the
command. The first two write cycles unlock the Command
Interface. The third write cycles sets up the commandthe fourth and fifth write cycles repeat the unlock
sequencethe sixth write cycle latches the block address
and confirms the command.
Additional Block Erase confirm cycles can be is-
sued to erase other blocks without further unlock
cycles. All blocks must belong to the same bank; if
a new block belonging to the other bank is given,
the operation is aborted.
The additional Block Erase confirm cycles must be
given within the DQ3 erase timeout period. Each
time a new confirm cycle is issued the timeout pe-
riod restarts. The status of the internal timer can
be monitored through the level of DQ3, see Status
Register section for more details.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
After the command has been issued the Flash
Read/Reset command will be accepted during the
DQ3 timeout period, after that only the Erase Sus-
pend command will be accepted.
On successful completion of the Block Erase com-
mand, the device returns to Read Array mode.
Bank Erase Command.The Bank Erase com-
mand can be used to erase a bank. It sets all the
bits within the selected bank to ’1’. All previous
data in the bank is lost. The Bank Erase command
will ignore any protected blocks within the bank. If
all blocks in the bank are protected then the Bank
Erase operation will abort and the data in the bank
will not be changed. It is not necessary to pre-pro-
gram the bank as the Program/Erase Controller
does it automatically before erasing.
As for the Block Erase command six Bus Write cy-
cles are required to issue the command. The first two write cycles unlock the Command
Interface. The third write cycles sets up the commandthe fourth and fifth write cycles repeat the unlock
sequencethe sixth write cycle latches the block address
and confirms the command.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
On successful completion of the Bank Erase com-
mand, the device returns to Read Array mode.
Erase Suspend Command.The Erase Suspend
command is used to pause a Block Erase opera-
tion. In a Dual Bank memory it can be used to read
data within the bank where an Erase operation is
in progress. It is also possible to program data in
blocks not being erased.
One bus write cycle is required to issue the Erase
Suspend command. The Program/Erase Control-
ler suspends the Erase operation within 20μs of
the Erase Suspend command being issued and
bits 7, 6 and/ or 2 of the Status Register are set to
‘1’. The device is then automatically set to Read
mode. The command can be addressed to any
bank.
During Erase Suspend the memory will accept the
Erase Resume, Program, Read CFI Query, Auto
Select, Block Lock, Block Unlock and Block Lock-
Down commands.
Erase Resume Command.The Erase Resume
command can be used to restart the Program/
Erase Controller after an Erase Suspend com-
mand has paused it. One Bus Write cycle is re-
quired to issue the command. The command must
be issued to an address within the bank being
erased. The unlock cycles are not required.
Protection Register Program Command.The
Protection Register Program command is used to
Program the Protection Register (One-Time-Pro-
grammable (OTP) segment and Protection Regis-
ter Lock). The OTP segment is programmed 16
bits at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits
to ‘0’.
Four write cycles are required to issue the Protec-
tion Register Program command. The first two bus cycles unlock the Command
Interface.The third bus cycle sets up the Protection
Register Program command.The fourth latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The OTP segment can be protected by program-
ming bit 1 of the Protection Register Lock. The
segment can be protected by programming bit 1 of
the Protection Register Lock. Bit 1 of the Protec-
tion Register Lock also protects bit 2 of the Protec-
tion Register Lock. Programming bit 2 of the
Protection Register Lock will result in a permanent
protection of Parameter Block #0 (see Figure 5,
Flash Security Block and Protection Register
Memory Map). Attempting to program a previously
17/52
M36DR432AD, M36DR432BDprotected Protection Register will result in a Status
Register error. The protection of the Protection
Register and/or the Security Block is not revers-
ible.
Table 4. Flash CommandsNote:X = Don’t Care, BA = Block Address, PA = Program address, PD = Program Data, CRD = Configuration Register Data. For Coded
cycles address inputs A12-A20 are don’t care.
M36DR432AD, M36DR432BD
Table 5. Read Electronic Signature Note:X = Don’t care.
Table 6. Flash Read Block ProtectionNote:X = Don’t care.
Table 7. Configuration RegisterNote:X = Don’t care.
19/52
M36DR432AD, M36DR432BD
Table 8. Read Protection RegisterNote:X= Don’t care.
Table 9. Program, Erase Times and Program, Erase Endurance CyclesNote:1.Excludes the time needed to execute the sequence for program command.Same timing value if VPPF = 12V
Flash Block Locking The Flash memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has two levels of protection.Lock/Unlock - this first level allows software-
only control of block locking.Lock-Down - this second level requires
hardware interaction before locking can be
changed.
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 10, de-
fines all of the possible protection states (WPF,
DQ1, DQ0).
Reading a Block’s Lock StatusThe lock status of every block can be read in the
Auto Select mode of the device. Subsequent
reads at the address specified in Table 6, will out-
put the protection status of that block. The lock
status is represented by DQ0 and DQ1. DQ0 indi-
cates the Block Lock/Unlock status and is set by
the Lock command and cleared by the Unlock
command. It is also automatically set when enter-
M36DR432AD, M36DR432BDing Lock-Down. DQ1 indicates the Lock-Down sta-
tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked StateThe default status of all blocks on power-up or af-
ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper-
ations attempted on a locked block will reset the
device to Read Array mode. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com-
mands. An Unlocked block can be Locked by issu-
ing the Lock command.
Unlocked StateUnlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be un-
locked by issuing the Unlock command.
Lock-Down StateBlocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can-
not be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked-
Down blocks revert to the Locked state when the
device is reset or powered-down.
The Lock-Down function is dependent on the WPF
input pin. When WPF=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
WPF=1 (VIH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be individu-
ally unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WPF
remains High. When WPF is Low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WPF was High. Device reset or power-down
resets all blocks, including those in Lock-Down, to
the Locked state.
Locking Operations During Erase SuspendChanges to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
21/52
M36DR432AD, M36DR432BD
Table 10. Flash Lock Status Note:1.The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Auto Select command with A1 = VIH and A0 = VIL.All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Flash Status RegisterThe Status Register provides information on the
current or previous Program or Erase operations.
Bus Read operations from any address within the
bank, always read the Status Register during Pro-
gram and Erase operations.
The various bits convey information about the sta-
tus and any errors of the operation.
The bits in the Status Register are summarized in
Table 12, Status Register Bits. Refer to Tables 11
and 12 in conjunction with the following text de-
scriptions.
Data Polling Bit (DQ7).When Program opera-
tions are in progress, the Data Polling bit outputs
the complement of the bit being programmed on
DQ7. For a Double Word Program operation, it is
the complement of DQ7 for the last Word written to
the Command Interface.
During an Erase operation, it outputs a ’0’. After
completion of the operation, DQ7 will output the bit
last programmed or a ’1’ after erasing.
Data Polling is valid and only effective during P/
E.C. operation, that is after the fourth WF pulse for
programming or after the sixth WF pulse for erase.
It must be performed at the address being pro-
grammed or at an address within the block being
erased. See Figure 22 for the Data Polling flow-
chart and Figure 13 for the Data Polling wave-
forms.
DQ7 will also flag an Erase Suspend by switching
from ’0’ to ’1’ at the start of the Erase Suspend. In
order to monitor DQ7 in the Erase Suspend mode
an address within a block being erased must be
provided. DQ7 will output ’1’ if the read is attempt-
ed on a block being erased and the data value on
other blocks. During a program operation in Erase
Suspend, DQ7 will have the same behavior as in
the normal program.
Toggle Bit (DQ6).When Program or Erase oper-
ations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6
will toggle following the toggling of either GF or EF.
The operation is completed when two successive
reads give the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing.
The Toggle Bit DQ6 is valid only during P/E.C. op-
erations, that is after the fourth WF pulse for pro-
gramming or after the sixth WF pulse for Erase.
DQ6 will be set to ’1’ if a read operation is attempt-
ed on an Erase Suspend block. When erase is
suspended DQ6 will toggle during programming
operations in a block different from the block in
Erase Suspend.
See Figure 16 for Toggle Bit flowchart and Figure
14 for Toggle Bit waveforms.
Toggle Bit (DQ2).Toggle Bit DQ2, together with
DQ6, can be used to determine the device status
during erase operations.
During Erase Suspend a read from a block being
erased will cause DQ2 to toggle. A read from a
block not being erased will output data. DQ2 will
be set to '1' during program operation and to ‘0’ in
erase operation. If a read operation is addressed
to a block where an erase error has occurred, DQ2
will toggle.
M36DR432AD, M36DR432BD
Error Bit (DQ5).The Error Bit can be used to
identify if an error occurs during a program or
erase operation.
The Error Bit is set to ‘1’ when a program or erase
operation has failed. When it is set to ‘0’ the pro-
gram or erase operation was successful.
If any Program command is used to try to set a bit
from ‘0’ to ‘1’ Status Register Error bit DQ5 will be
set to ‘1’, only if VPP is in the range of 11.4V to
12.6V.
The Error Bit is reset by a Read/Reset command.
Erase Timer Bit (DQ3).The Erase Timer bit is
used to indicate the timeout period for an erase
operation.
When the last block Erase command has been en-
tered to the Command Interface and it is waiting
for the erase operation to start, the Erase Timer Bit
is set to ‘0’. When the erase timeout period is fin-
ished, DQ3 returns to ‘1’, (80μs to 120μs).
DQ0, DQ1 and DQ4 are reserved for future useand should be masked.
Table 11. Polling and Toggle Bits
23/52
M36DR432AD, M36DR432BD
Table 12. Status Register BitsNote:1.Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations.In case of double word program DQ7 refers to the last word input.
M36DR432AD, M36DR432BD
SRAM COMPONENTThe SRAM is a 4 Mbit (256Kb x16) low-power con-
sumption memory array with low VDDS data reten-
tion.
SRAM Operations The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 2).
Read.Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS) is at VIH with
Output Enable (GS) at VIL, Chip Enable ES and
UBS, LBS combinations are asserted.
Valid data will be available at the output pins within
tAVQV after the last stable address, provided that
GS is Low and ES is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (tELQV or
tGLQV) rather than the address. Data out may be
indeterminate at tELQX and tGLQX, but data lines
will always be valid at tAVQV (see Table 23, Figures
17 and 18).
Write.Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the WS and ES pins are at VIL. Either the Chip En-
able input (ES) or the Write Enable input (WS)
must be de-asserted during address transitions for
subsequent write cycles. Write begins with the
concurrence of Chip Enable being active and WS
at VIL. A Write begins at the latest transition
among ES going to VIL and WS going to VIL.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as tAVWL and tAVEL
respectively, and is determined by the latter occur-
ring edge. The Write cycle can be terminated by
the rising edge of ES or the rising edge of WS,
whichever occurs first.
If the Output is enabled (ES=VIL and GS=VIL),
then WS will return the outputs to high impedance
within tWLQZ of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for tDVWH before the ris-
ing edge of Write Enable, or for tDVEH before the
rising edge of ES, whichever occurs first, and re-
main valid for tWHDX and tEHAX (see Table 24, Fig-
ure 20, 22, 24).
Standby/Power-Down.The SRAM chip has a
Chip Enable power-down feature which invokes
an automatic standby mode (see Table 23, Figure
19) whenever either Chip Enable is de-asserted
(ES=VIH).
Data Retention.The SRAM data retention per-
formances as VDDS go down to VDR are described
in Table 25 and Figure 24. In ES controlled data
retention mode, minimum standby current mode is
entered when ES≥VDDS–0.2V.
Output Disable.The data outputs are high im-
pedance when the Output Enable (GS) is at VIH
with Write Enable (WS) at VIH.
25/52
M36DR432AD, M36DR432BD
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 13. Absolute Maximum Ratings(1) Note:1.Minimum voltage may undershoot to –2V during transition and for less than 20ns.Depends on range.VDD = VDDS = VDDF.
M36DR432AD, M36DR432BD
DC AND AC PARAMETERSThis section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 14, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 14. Operating and AC Measurement ConditionsNote:1.VDD = VDDS = VDDF
Figure 6. AC Measurement I/O WaveformNote:VDD means VDDF = VDDS
Figure 7. AC Measurement Load CircuitNote:VDD means VDDF = VDDS
Table 15. Device CapacitanceNote:Sampled only, not 100% tested.
