M34E02-FMB1TG ,2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMsLogic Diagram . . 4Figure 3. TSSOP and MLP Connections (Top View) . . . . 4Table 1. Sign ..
M35045-054SP , SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35045-092SP , SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35045-096SP , SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35045-151SP , SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35052-001 , SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M54125P , EARTH LEAKAGE CURRENT DETECTOR
M54128L , EARTH LEAKAGE CURRENT DETECTOR
M-542CT , DC Line Fileters
M-542CT , DC Line Fileters
M54410P , KEY CONTROLLER FOR TAPE DECK
M54410P , KEY CONTROLLER FOR TAPE DECK
M34E02-FDW1TP-M34E02-FMB1TG
2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs
1/23November 2004
M34E022 Kbit Serial I²C Bus EEPROM
Serial Presence Detect for DDR2 DIMMs
FEATURES SUMMARYSoftware Data Protection for lower 128 bytesTwo Wire I2C Serial Interface100kHz Transfer Rates1.7 to 3.6V Single Supply Voltage:BYTE and PAGE WRITE (up to 16 bytes)RANDOM and SEQUENTIAL READ ModesSelf-Timed Programming CycleAutomatic Address IncrementingEnhanced ESD/Latch-Up ProtectionMore than 1 Million Erase/Write CyclesMore than 40 Year Data Retention
M34E02
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3.TSSOP and MLP Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Serial Data (SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chip Enable (E0, E1, E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 4.Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . . .5
Figure 5.I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 2.Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DEVICE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 3.Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 6.Result of Setting the Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Setting the Write-Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 7.Setting the Write Protection (WC = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 8.Write Mode Sequences in a Non Write-Protected Area . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 9.Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 10.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3/23
M34E02
USE WITHIN A DDR2 DIMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 4.DRAM DIMM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Programming the M34E02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12DDR2 DIMM Isolated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DDR2 DIMM Inserted in the Application Mother Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 5.Acknowledge when Writing Data or Defining the Write-protection
(Instructions with R/W bit=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6.Acknowledge when Reading the Write Protection (Instructions with R/W bit=1). . . . . . .13
Figure 11.Serial Presence Detect Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 7.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 8.Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 9.AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 12.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 10.Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 11.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 12.AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 13.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 13.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .20
Table 14.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data. . . . . . . . . . . .20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 15.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 16.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
M34E02
SUMMARY DESCRIPTION
5/23
M34E02
SIGNAL DESCRIPTION
Serial Clock (SCL)This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to VCC. (Figure 4
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to VCC. (Fig-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. In the
end application, E0, E1 and E2 must be directly
(not through a pull-up or pull-down resistor) con-
nected to VCC or VSS to establish the Device Se-
lect Code. When these inputs are not connected,
an internal pull-down circuitry makes (E0,E1,E2) =
(0,0,0).
The E0 input is used to detect the VHV voltage,
when decoding an SWP or CWP instruction.
Write Control (WC)This input signal is provided for protecting the con-
tents of the whole memory from inadvertent write
operations. Write Control (WC) is used to enable
(when driven Low) or disable (when driven High)
write instructions to the entire memory area or to
the Protection Register.
When Write Control (WC) is tied Low or left
unconnected, the write protection of the first half of
the memory is determined by the status of the
Protection Register.
M34E02
7/23
M34E02
DEVICE OPERATION The device supports the I2C protocol. This is sum-
marized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The memory device is always a
slave in all communication.
Start ConditionStart is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop ConditionStop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During theth clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data InputDuring data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory AddressingTo start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b; to access the
write-protection settings, it is 0110b.
Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the
device only responds if the Chip Enable Address
is the same as the value on the Chip Enable (E0,
E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Table 3. Operating ModesNote:1.X = VIH or VIL.
M34E02
Setting the Write-ProtectionThe M34E02 has a hardware write-protection
feature, using the Write Control (WC) signal. This
signal can be driven High or Low, and must be
held constant for the whole instruction sequence.
When Write Control (WC) is held High, the whole
memory array (addresses 00h to FFh) is write
protected. When Write Control (WC) is held Low,
the write protection of the memory array is
dependent on whether software write-protection
has been set.
Software write-protection allows the bottom half of
the memory area (addresses 00h to 7Fh) to be
write protected irrespective of subsequent states
of the Write Control (WC) signal.
Software write-protection is handled by three in-
structions:SWP: Set Write ProtectionCWP: Clear Write ProtectionPSWP: Permanently Set Write Protection
The level of write-protection (set or cleared) that
has been defined using these instructions, re-
mains defined even after a power cycle.
SWP and CWP.If the software write-protection
has been set with the SWP instruction, it can be
cleared again with a CWP instruction.
The two instructions (SWP and CWP) have the
same format as a Byte Write instruction, but with a
different Device Type Identifier (as shown in Table
2). Like the Byte Write instruction, it is followed by
an address byte and a data byte, but in this case
the contents are all “Don’t Care” (Figure 7). Anoth-
er difference is that the voltage, VHV, must be ap-
plied on the E0 pin, and specific logical levels must
be applied on the other two (E1 and E2, as shown
in Table 2).
PSWP.If the software write-protection has been
set with the PSWP instruction, the first 128 bytes
of the memory are permanently write-protected.
This write-protection cannot be cleared by any in-
struction, or by power-cycling the device, and re-
gardless the state of Write Control (WC). Also,
once the PSWP instruction has been successfully
executed, the M34E02 no longer acknowledges
any instruction (with a Device Type Identifier of
0110) to access the write-protection settings.
9/23
M34E02
Write Operations Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
8, and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte WriteAfter the Device Select Code and the address
byte, the bus master sends one data byte. If the
addressed location is hardware write-protected,
the device replies to the data byte with NoAck, and
the location is not modified. If, instead, the ad-
dressed location is not Write-protected, the device
replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown
in Figure 8.
Page WriteThe Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is hardware write-protected, the device replies
to the data byte with NoAck, and the locations are
not modified. After each byte is transferred, the in-
ternal byte address counter (the 4 least significant
address bits only) is incremented. The transfer is
terminated by the bus master generating a Stop
condition.
M34E02
Minimizing System Delays by Polling On ACKDuring the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Table
12, but the typical time is shorter. To make use of
this, a polling sequence can be used by the bus
master.
The sequence, as shown in Figure 9, is:Initial condition: a Write cycle is in progress.Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
11/23
M34E02
Read OperationsRead operations are performed independently of
whether hardware or software protection has been
set.
The device has an internal address counter which
is incremented each time a byte is read.
Random Address ReadA dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 10) but without sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
RW bit set to 1. The device acknowledges this,
and outputs the contents of the addressed byte.
The bus master must not acknowledge the byte,
and terminates the transfer with a Stop condition.
Current Address ReadFor the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 10, without acknowledging the
byte.
M34E02
Sequential ReadThis operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 10.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read ModeFor all Read commands, the device waits, after
each byte read, for an acknowledgment during theth bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
INITIAL DELIVERY STATEThe device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh).
USE WITHIN A DDR2 DIMMIn the application, the M34E02 is soldered directly
in the printed circuit module. The three Chip
Enable inputs (E0, E1, E2) must be connected to
VSS or VCC directly (that is without using a pull-up
or pull-down resistor) through the DIMM socket
(see Table 4.). The pull-up resistors needed for
normal behavior of the I2C bus are connected on
the I2C bus of the mother-board (as shown in
Figure 11).
The Write Control (WC) of the M34E02 can be left
unconnected. However, connecting it to VSS is
recommended, to maintain full read and write
access.
Table 4. DRAM DIMM Connections
Programming the M34E02The situations in which the M34E02 is pro-
grammed can be considered under two headings:when the DDR2 DIMM is isolated (not inserted
on the PCB motherboard)when the DDR2 DIMM is inserted on the PCB
motherboard
DDR2 DIMM Isolated.With specific program-
ming equipment, it is possible to define the
M34E02 content, using Byte and Page Write in-
structions, and its write-protection using the SWP
and CWP instructions. To issue the SWP and
CWP instructions, the DDR2 DIMM must be insert-
ed in the DDR2-specific slot where the E0 signal
can be driven to VHV during the whole instruction.
This programming step is mainly intended for use
by DDR2 DIMM makers, whose end application
manufacturers will want to clear this write-protec-
tion with the CWP on their own specific program-
ming equipment, to modify the lower 128 Bytes,
and finally to set permanently the write-protection
with the PSWP instruction.
DDR2 DIMM Inserted in the Application Mother
Board.As the final application cannot drive the
E0 pin to VHV, the only possible action is to freeze
the write-protection with the PSWP instruction.
Table 5 and Table 6 show how the Ack bits can be
used to identify the write-protection status.
