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M34C02-WMN6T
2 Kbit Serial IC Bus EEPROM For DIMM Serial Presence Detect
1/19December 1999
M34C02
2 Kbit Serial I²C Bus EEPROM
For DIMM Serial Presence DetectTwo Wire I2C Serial Interface
Supports 400kHz ProtocolSingle Supply Voltage:2.5V to 5.5V for M34C02-W2.2V to 5.5V for M34C02-LSoftware Data Protection for lower 128 bytesBYTE and PAGE WRITE (up to 16 bytes)RANDOM and SEQUENTIAL READ ModesSelf-Timed Programming CycleAutomatic Address IncrementingEnhanced ESD/Latch-Up Protection1 Million Erase/Write Cycles (minimum)40 Year Data Retention (minimum)
DESCRIPTION
The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of
Table 1. Signal Names
M34C02
the memory become permanently write protected.
Care must be taken when using this sequence as
its effect cannot be reversed. In addition, the
device allows the entire memory area to be write
protected, using the WC input (for example by
tieing this input to VCC).
The M34C02 is a 2 Kbit electrically erasable pro-
grammable memory (EEPROM), organized as
256x8 bits, fabricated with STMicroelectronics’
High Endurance, Advanced, CMOS technology.
This guarantees an endurance typically well
above one million Erase/Write cycles, with a data
retention of 40years. These memory devices
operate with a power supply down to 2.2V for the
M34C02-L.
The M34C02 is available in Plastic Dual In-line,
Plastic Small Outline and Thin Shrink Small
Outline packages.
These memory devices are compatible with the2C memory standard. This is a two wire serial
interface that uses a bi-directional data bus and
serial clock. The memory carries a built-in 4-bit
Device Type Identifier code (1010) in accordance
with the I2C bus definition to access the memory
area and a second Device Type Identifier Code
(0110) to access the Protection Register. These
codes are used together with three chip enable
inputs (E2, E1, E0) so that up to eight 2 Kbit
devices may be attached to the I²C bus and
selected individually.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
Table 2. Absolute Maximum Ratings 1
Note:1.Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.MIL-STD-883C, 3015.7 (100pF, 1500 Ω)
3/19
M34C02
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated bySTOP condition after an Ack for WRITE, and
after a NoAck for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the VCC voltage has reached
the POR threshold value, and all operations are
disabled – the device will not respond to any
command. In the same way, when VCC drops from
the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable and
valid VCC must be applied before applying any
logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be connected
from the SCL line to VCC. (Figure 3 indicates how
the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected from the SDA
bus to VCC. (Figure 3 indicates how the value of
the pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
VCC or VSS to establish the device select code.
Write Control (WC)
A hardware Write Control (WC, pin 7) is provided
for protecting the contents of the whole memory
from erroneous erase/write cycles. The Write
Control signal is used to enable (WC=VIL) or
disable (WC=VIH) write instructions to the entire
memory area or to the Protection Register.
When WC is tied to VSS or left unconnected, the
write protection of the first half of the memory is
determined by the status of the Protection
Register.
DEVICE OPERATION
The memory device supports the I2C protocol.
This is summarized in Figure 4. Any device that
sends data on to the bus is defined to be a
transmitter, and any device that reads the data to
be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can only be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.
M34C02
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, provided that it is followed by a
NoAck, forces the memory device into its standby
state. A STOP condition at the end of a Write
Table 3. Device Select Code 1
Note:1.The most significant bit (b7) is sent first.
5/19
M34C02
command triggers the internal EEPROM write
cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9th
clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
transition, and the data must change only when
the SCL line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b. To address the Protection
Register, it is 0110b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the
memory only responds if the Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.
The 8th bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the
corresponding memory gives an acknowledgment
on the SDA bus during the 9th bit time. If the
memory does not match the Device Select code, it
will deselect itself from the bus, and go into stand-
by mode.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address byte, the master sends one
data byte. If the addressed location is in a write
protected area, the memory replies with a NoAck,
and the location is not modified. If, instead, the
addressed location is not in a write protected area,
the memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b7-b4) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 16 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified. After each byte is transferred, the
internal byte address counter (the 4 least
Table 4. Operating Modes
Note:1.X = VIH or VIL.
M34C02
significant bits only) is incremented. The transfer is
terminated by the master generating a STOP
condition.
When the master generates a STOP condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not
trigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (tw) is shown in Table 9,
but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the
master.
7/19
M34C02
M34C02
Setting the Protection, Using the Protection
Register
The M34C02 has a software write-protection
function, using the Protecton Register, that allows
the bottom half of the memory area (addresses
00h to 7Fh) to be permanently write protected. The
write protection feature is activated by writing once
to the Protection Register (with the WC input held
at VSS).
The Protection Register is accessed with the
device select code set to 0110b (as shown in
Table 3), and the E2-E1-E0 bits set according to
the states being applied to the E2-E1-E0 pins. As
The sequence, as shown in Figure 7, is:Initial condition: a Write is in progress.Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
9/19
M34C02
for any other write command, the WC input needs
to be held at VSS. Address and data bytes must be
sent with this command, but their values are all
ignored, and are treated as Don’t Care. Once the
Protection Register has been written, the write
protection of the first 128 bytes of the memory is
enabled, and it is not possible to unprotect these
128 bytes, even if the device is powered off and
on, and regardless the state of the WC input.
When the Protection Register has been written,
the M34C02 no longer responds to the device type
identifier 0110b in either read or write mode.
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 9.
Then, without sending a STOP condition, the
master sends another START condition, and
repeats the Device Select Code, with the RW bit
set to ‘1’. The memory acknowledges this, and
outputs the contents of the addressed byte. The
master must not acknowledge the byte output, and
terminates the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as
shown in Figure 9, without acknowledging the byte
output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
counter ‘rolls-over’ and the memory continues to
output data from address 00h (at the start of the
memory block).
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its standby state.
USE WITHIN A DRAM DIMM
In the application, the M34C02 is soldered directly
in the printed circuit module. The 3 Chip Enable
inputs (pins 1, 2 and 3) are connected to pins 165,
166 and 167, respectively, of the 168-pin DRAM
DIMM module. They are wired at VCC or VSS
through the DIMM socket (see Table 5). The SCL
and SDA lines (pins 6 and 5) are connected
respectively to pins 83 and 82 of the memory
module. The pull-up resistors needed for normal
behavior of the I2C bus are connected on the I2C
bus of the mother-board (as shown in Figure 10).
The Write Control input of the M34C02 (WC on pin
7) can be left unconnected. However, connecting
it to VSS is recommended, to maintain full read and
write access to the top half of the memory.
Programming the M34C02
When the M34C02 is delivered, full read and write
access is given to the whole memory array. It is
recommended that the first step is to use the test
equipment to write the module information (such
as its access speed, its size, its organization) to
the first half of the memory, starting from the first
memory location. When the data has been
validated, the test equipment can send a Write
command to the Protection Register, using the
device select code ’01100000b’ followed by an
address and data byte (made up of Don’t Care
values) as shown in Figure 8. The first 128 bytes
of the memory area are then write-protected, and
the M34C02 will no longer respond to the specific
device select code ’0110000xb’. It is not possible
to reverse this sequence.
Table 5. 168 Pin DRAM DIMM Connections
M34C02

Partno	Mfg	Dc	Qty	Available	Descript
M34C02-WMN6T \|M34C02WMN6T	ST	N/a	27500	avai	2 Kbit Serial IC Bus EEPROM For DIMM Serial Presence Detect