M28W320CB90GB6T ,32 Mbit 2Mb x16/ Boot Block Low Voltage Flash MemoryAbsolute Maximum Ratings” maycause permanent damage to the device. These are stress ratings only an ..
M28W320CB90N6 ,32 MBIT (2MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYM28W320CTM28W320CB32 Mbit (2Mb x16, Boot Block)3V Supply Flash Memory
M28W320CB-90N6 ,32 MBIT (2MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V Core Power SupplyDD–V = 1.65V ..
M28W320CB-90N6 ,32 MBIT (2MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYLogic Diagramvided to speed up customer programming.The device
M28W320CB90N6T ,32 MBIT (2MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYTABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
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M28W320CB90GB6T-M28W320CT100GB6T
32 Mbit 2Mb x16/ Boot Block Low Voltage Flash Memory
1/42
PRELIMINARY DATAMay 2000
M28W320CT
M28W320CB Mbit (2Mb x16, Boot Block) Low Voltage Flash Memory SUPPLY VOLTAGE
–VDD= 2.7Vto 3.6V:for Program, Erase and
Read
–VDDQ= 1.65Vor 2.7V: Input/Output option
–VPP= 12V: optional Supply Voltagefor fast
Program ACCESS TIME 2.7Vto 3.6V: 90ns 2.7Vto 3.6V: 100ns PROGRAMMING TIME:
–10μs typical Double Word Programming Option PROGRAM/ERASE CONTROLLER (P/E.C.) COMMON FLASH INTERFACE MEMORY BLOCKS Parameter Blocks (Topor Bottom location) Main Blocks BLOCK PROTECTION UNPROTECTIONAll Blocks protectedat PowerUp Any combinationof blocks canbe protected WPfor block locking SECURITY 64-bit user Programmable OTP cells 64-bit unique device identifier One Parameter Block Permanently Lockable AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLESper
BLOCK 20 YEARSof DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M28W320CT: 88BAh Bottom Device Code, M28W320CB: 88BBh
Figure1. Logic DiagramAI03521
A0-A20
DQ0-DQ15
VDD
M28W320CT
M28W320CB
VSS
VDDQ VPP
TSOP48(N)x 20mm
μBGA47 (GB)x6 solder balls
μBGA
M28W320CT, M28W320CB2/42
Figure2. μBGA
Connections (Top view through package)AI026867654321A7VPPA8A11A13EDQ8DQ5DQ14A16
VSSDQ0DQ9DQ3DQ6DQ15VDDQ
DQ1DQ10VDD DQ7VSS
DQ2A5A17WA10A14A3A6A9A12A15 A18
DQ4 DQ13 G
DQ12
DQ11 A19
A20
Figure3. TSOP ConnectionsDQ3
DQ9
DQ2
DQ0
DQ6
DQ13
A17
A10 DQ14
DQ12
DQ10
DQ15
VDD
DQ4
DQ5
DQ7
VPP
AI03522
M28W320CT
M28W320CB 25
DQ8
A20
A19
A18
DQ1
DQ11
A12
A13
A16
A11
VDDQ
A15
A14
VSS
VSS
Table1. Signal NamesA0-A20 Address Inputs
DQ0-DQ7 Data Input/Output, Command Inputs
DQ8-DQ15 Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect
VDD Supply Voltage
VDDQ Power Supplyfor
Input/Output Buffers
VPP Optional Supply Voltagefor
Fast Program& Erase
VSS Ground Not Connected Internally
3/42
M28W320CT, M28W320CB
DESCRIPTIONThe M28W320Cisa32 Mbit non-volatile Flash
memory thatcanbe erased electricallyatthe block
level and programmed in-systemona Word-by-
Word basis. The deviceis offeredinthe TSOP48
(10x 20mm) andthe μBGA47, 0.75mm ball pitch
packages. When shipped, all bits of the
M28W320Careinthe1 state.
The array matrix organisation allows each blockto erased and reprogrammed without affecting
other blocks.All blocksare protected against pro-
gramming and eraseat Power UP. Blocks canbe
unprotectedto make changesinthe application
and then reprotected.A parameter block ”Security
Block” canbe permanently protected against pro-
gramming and erasein orderto increasethe data
security. Each block canbe programmed and
erased over 100,000 cycles. VDDQ allowsto drive
theI/Opin downto 1.65V.An optional 12V VPP
power supplyis providedto speedupthe program
phaseat customer production line environment. internal Command Interface (C.I.) decodesthe
instructionsto access/modifythe memory content.
The Program/Erase Controller (P/E.C.) automati-
cally executesthe algorithms taking careof the
timings necessaryfor program and erase opera-
tions. Verificationis performed too, unburdening
the microcontroller, while the Status Register
tracksthe statusofthe operation.
The following instructions are executedby the
M28W320C: Read Array, Read Electronic Signa-
ture, Read Status Register, Clear Status Register,
Program, Double Word Program, Block Erase,
Program/Erase Suspend, Program/Erase Re-
sume,CFI Query, Block Protect, Block Lock, Block
Unprotect, Protection Program.
OrganisationThe M28W320Cis organisedas2 Mbitby16 bits.
A0-A20arethe address lines; DQ0-DQ15arethe
Data Input/Output. Memory controlis providedby
Chip EnableE, Output EnableGand Write Enable inputs. The Program and Erase operationsare
managed automaticallybythe P/E.C. Block pro-
tection against Programor Erase provides addi-
tional data security.
Memory BlocksThe device featuresan asymmetrical blockedar-
chitecture. The M28W320C hasan arrayof71
blocks:8 Parameter Blocksof4 KWord and63
Main Blocksof32 KWord. M28W320CT hasthe
Parameter Blocksatthetopofthe memory ad-
dress space whilethe M28W320CB locatesthe
Parameter Blocks starting fromthe bottom. The
memory mapsare shownin Tables3 and4.
All Blocksare protectedat powerup. Instruction
are providedto protect, unprotect any blockinthe
application.A second register locksthe protection
status while WPis low (see Block Protection De-
scription). Each block canbe erased separately.
Erasecanbe suspendedin orderto perform either
reador programin any other block and thenre-
sumed. Programcanbe suspendedto read datain
any other block and then resumed.
The architecture includesa 128 bits Protection
register thatare divided into Two 64-bits segment.the first one, starting from address 81hto 84h, writtena unique device number, whilethe sec-
ond one, starting from 85hto 88h,is programma-
blebythe user. The user programmable segment
canbe permanently protected programmingthe
bit.1ofthe Protection Lock Register (see protec-
tion register and Security Block). The parameter
block(#0)isa security block.Itcanbe permanent- protectedbythe user programmingthe bit.2of
the Protection Lock Register (see protection regis-
ter and Security Block).
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating ”Operating Temperature Range”, stressesabove those listedinthe Table ”Absolute Maximum Ratings”may
cause permanent damagetothe device. Theseare stress ratingsonlyand operationofthe device attheseor anyother conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating condi-
tionsfor extended periodsmay affect device reliability. Referalsotothe STMicroelectronics SUREProgram andotherrelevantqual-
ity documents. Dependson range.
Symbol Parameter Value Unit Ambient Operating Temperature(2) –40to85 °C
TBIAS Temperature Under Bias –40to125 °C
TSTG Storage Temperature –55to155 °C
VIO Inputor Output Voltage –0.6to VDDQ+0.6 V
VDD,VDDQ Supply Voltage –0.6to4.1 V
VPP Program Voltage –0.6to13 V
M28W320CT, M28W320CB4/42
Table3. Top Boot Block Addresses,
M28W320CT Size
(KWord) Address Range 4 1FF000-1FFFFF 4 1FE000-1FEFFF 4 1FD000-1FDFFF 4 1FC000-1FCFFF 4 1FB000-1FBFFF 4 1FA000-1FAFFF 4 1F9000-1F9FFF 4 1F8000-1F8FFF 32 1F0000-1F7FFF 32 1E8000-1EFFFF 32 1E0000-1E7FFF 32 1D8000-1DFFFF 32 1D0000-1D7FFF 32 1C8000-1CFFFF 32 1C0000-1C7FFF 32 1B8000-1BFFFF 32 1B0000-1B7FFF 32 1A8000-1AFFFF 32 1A0000-1A7FFF 32 198000-19FFFF 32 190000-197FFF 32 188000-18FFFF 32 180000-187FFF 32 178000-17FFFF 32 170000-177FFF 32 168000-16FFFF 32 160000-167FFF 32 158000-15FFFF 32 150000-157FFF 32 148000-14FFFF 32 140000-147FFF 32 138000-13FFFF 32 130000-137FFF 32 128000-12FFFF 32 120000-127FFF 32 118000-11FFFF 32 110000-117FFF 32 108000-10FFFF 32 100000-107FFF 32 0F8000-0FFFFF 32 0F00000-F7FFF 32 0E8000-0EFFFF 32 0E0000-0E7FFF 32 0D8000-0DFFFF 32 0D0000-0D7FFF 32 0C8000-0CFFFF 32 0C0000-0C7FFF 32 0B8000-0BFFFF 32 0B0000-0B7FFF 32 0A8000-0AFFFF 32 0A0000-0A7FFF 32 098000-09FFFF 32 090000-097FFF 32 088000-08FFFF 32 080000-087FFF 32 078000-07FFFF 32 070000-077FFF 32 068000-06FFFF 32 060000-067FFF 32 058000-05FFFF 32 050000-057FFF 32 048000-04FFFF 32 040000-047FFF 32 038000-03FFFF 32 030000-037FFF 32 028000-02FFFF 32 020000-027FFF 32 018000-01FFFF 32 010000-017FFF 32 008000-00FFFF 32 000000-007FFF
5/42
M28W320CT, M28W320CB 32 0E8000-0EFFFF 32 0E0000-0E7FFF 32 0D8000-0DFFFF 32 0D0000-0D7FFF 32 0C8000-0CFFFF 32 0C0000-0C7FFF 32 0B8000-0BFFFF 32 0B0000-0B7FFF 32 0A8000-0AFFFF 32 0A0000-0A7FFF 32 098000-09FFFF 32 090000-097FFF 32 088000-08FFFF 32 080000-087FFF 32 078000-07FFFF 32 070000-077FFF 32 068000-06FFFF 32 060000-067FFF 32 058000-05FFFF 32 050000-057FFF 32 048000-04FFFF 32 040000-047FFF 32 038000-03FFFF 32 030000-037FFF 32 028000-02FFFF 32 020000-027FFF 32 018000-01FFFF 32 010000-017FFF 32 008000-00FFFF 4 007000-007FFF 4 006000-006FFF 4 005000-005FFF 4 004000-004FFF 4 003000-003FFF 4 002000-002FFF 4 001000-001FFF 4 000000-000FFF
Table4. Bottom Boot Block Addresses,
M28W320CB Size
(KWord) Address Range 32 1F8000-1FFFFF 32 1F0000-1F7FFF 32 1E8000-1EFFFF 32 1E0000-1E7FFF 32 1D8000-1DFFFF 32 1D0000-1D7FFF 32 1C8000-1CFFFF 32 1C0000-1C7FFF 32 1B8000-1BFFFF 32 1B0000-1B7FFF 32 1A8000-1AFFFF 32 1A0000-1A7FFF 32 198000-19FFFF 32 190000-197FFF 32 188000-18FFFF 32 180000-187FFF 32 178000-17FFFF 32 170000-177FFF 32 168000-16FFFF 32 160000-167FFF 32 158000-15FFFF 32 150000-157FFF 32 148000-14FFFF 32 140000-147FFF 32 138000-13FFFF 32 130000-137FFF 32 128000-12FFFF 32 120000-127FFF 32 118000-11FFFF 32 110000-117FFF 32 108000-10FFFF 32 100000-107FFF 32 0F8000-0FFFFF 32 0F0000-0F7FFF
M28W320CT, M28W320CB6/42
SIGNAL DESCRIPTIONSSee Figure1 and Table1.
Address Inputs (A0-A20). The address signals
are inputs driven with CMOS voltage levels. They
are latched duringa write operation.
Data Input/Output (DQ0-DQ15). The data in-
puts,a wordtobe programmedora commandto
the C.I.,are latchedonthe Chip EnableEor Write
EnableW rising edge, whichever occurs first. The
data output fromthe memory Array,the Electronic
Signature, the block protection statusor Status
Registeris valid when Chip EnableE and Output
EnableGare active. The outputis high impedance
whenthe chipis deselected,the outputsare dis-
abledorRPis tiedto VIL. Commandsare issued DQ0-DQ7.
Chip Enable (E). The Chip Enable input acti-
vatesthe memory control logic, input buffers,de-
coders and sense amplifiers.Eat VIH deselects
the memory and reducesthe power consumption thestand-by level.E can alsobe usedto control
writingtothe command register andtothe memo- array, whileW remainsat VIL.
Output Enable (G). The Output Enable controls
the data Input/Output buffers.
Write Enable (W). This input controls writingto
the Command Register, Input Address and Data
latches.
Write Protect (WP). This input givesan addition- hardware protection level against programor
erase when pulledatVIL, asdescribedinthe Block
Protection description.
Reset Input (RP). The RP input provides hard-
ware resetofthe memory. WhenRPisat VIL,the
memoryisin reset mode:the outputsareputto
High-Z andthe current consumptionis minimised.
WhenRPisat VIH,the deviceisin normal opera-
tion. Exiting reset modethe device enters readar-
ray mode.
VDD Supply Voltage (2.7Vto 3.6V). VDD pro-
videsthe power supplytothe internal coreofthe
memory device.Itisthe main power supplyforall
operations (Read, Program and Erase).It ranges
from 2.7Vto 3.6V.
VDDQ Supply Voltage (1.65Vto VDD). VDDQ
providesthe power supplytotheI/O pins anden-
ablesall Outputstobe powered independently
from VDD.VDDQ canbe tiedto VDDorit canusea
separate supply.It canbe powered either from
1.65Vto VDD.
VPP Program Supply Voltage (12V). VPPis both control input anda power supply pin. The two
functionsare selectedbythe voltage rangeap-
pliedtothe pin. VPPis keptinalow voltage range(0Vto 3.6V)
VPPis seenasa control input.In this casea volt-
age lower than VPPLK givesan absolute protection
against programor erase, while VPP >VPP1 en-
ables these functions. VPP valueis only sampledthe beginningofa programor erase;a changeits value afterthe operation has been started
doesnot haveany effect and programor eraseare
carriedon regularly. VPPis usedinthe range 11.4Vto 12.6V actsas power supply pin.In this condition VPP value
mustbe stable until P/E algorithmis completed
(see Table24 and 25).
VSS Ground. VSSisthe referenceforallthe volt-
age measurements.
7/42
M28W320CT, M28W320CB
DEVICE OPERATIONSFour control pins rulethe hardware accesstothe
Flash memory:E,G,W, RP. The following opera-
tions canbe performed usingthe appropriate bus
cycles: Read, Writethe Commandofan Instruc-
tion, Output Disable, Stand-by, Reset (see Table
5).
Read. Read operations are usedto output the
contentsofthe Memory Array,the Electronic Sig-
nature,the Status Register andthe CFI. Both Chip
Enable(E) and Output Enable(G) mustbeatVIL orderto performthe read operation. The Chip
Enable input shouldbe usedto enablethe device.
Output Enable shouldbe usedto gate data onto
the output independentlyofthe device selection.
The data read dependonthe previous command
writtentothe memory (see instructions RD, RSIG,
RSR, RCFI). Read Arrayisthe default stateofthe
device when exiting resetor after power-up.
Write. Write operations are usedto give Com-
mandstothe memoryorto latch Input Datatobe
programmed.A write operationis initiated when
Chip EnableE and Write EnableWareatVIL with
Output EnableGat VIH. Commands, Input Data
and Addressesare latchedonthe rising edgeofWE, whichever occur first.
Output Disable. The data outputs are highim-
pedance whenthe Output EnableGisat VIH.
Stand-by. Stand-by disables mostofthe internal
circuitry allowinga substantial reductionofthe cur-
rent consumption. The memoryisin stand-by
when Chip EnableEisatVIH andthe deviceisin
read mode. The power consumptionis reducedto
the stand-by level andthe outputsaresetto high
impedance, independently fromthe Output Enableor Write EnableW inputs.IfE switchestoVIH
during programor erase operation,the deviceen-
tersin stand-by when finished.
Reset. During Reset modeall internal circuitsare
switchedoff,the memoryis deselected and the
outputsareputin high impedance. The memoryis Reset mode whenRPisatVIL. The power con-
sumptionis reducedtothe stand-by level, inde-
pendently fromthe Chip EnableE, Out-put Enableor Write EnableW inputs.IfRPis pulledto VSS
duringa Programor Erase,this operationis abort- andthe memory contentisno longer validasit
has been compromisedbythe aborted operation.
Table5. User Bus Operations(1)Note:1.X=VILor VIH,VPPH=12V±5%.
Table6. Read Electronic Signature (RSIG Instruction)
Operation E G W RP WP VPP DQ0-DQ15Read VIL VIL VIH VIH X Don’t Care Data Output
Write VIL VIH VIL VIH X VDDor VPPH Data Input
Output Disable VIL VIH VIH VIH X Don’t Care Hi-Z
Stand-by VIH XX VIH X Don’t Care Hi-Z
Reset X X X VIL X Don’t Care Hi-Z
Code Device E G W A0 A1 A2-A7 A8-A11 A12-A20 DQ0-DQ7 DQ8-DQ15Manufact.
Code VIL VIL VIH VIL VIL 0 Don’t Care Don’t Care 20h 00h
Device
Code
M28W320CT VIL VIL VIH VIH VIL 0 Don’t Care Don’t Care BAh 88h
M28W320CB VIL VIL VIH VIH VIL 0 Don’t Care Don’t Care BBh 88h
M28W320CT, M28W320CB8/42
Table7. Read Block Signature (RSIG Instruction)Note:1.A Locked Blockcanbe protected ”DQ0=1”or unprotected ”DQ0=0”;see Block protection section.
Table8. Read Protection Register and Protection Register Lock (RSIG Instruction)
Block Status E G W A0 A1 A2-A7 A8-A11 A12-A20 DQ0 DQ1 DQ2-DQ15Protected Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address 1 0 00h
Unprotected Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address 0 0 00h
Locked Block VIL VIL VIH VIL VIH 0 Don’t Care Block AddressX(1) 1 00h
Word E G W A0-A7 A8-A20 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15Lock VIL VIL VIH 80h Don’t Care 0 OTP Prot.
data
Security
prot. data 00h 00h
UniqueId0 VIL VIL VIH 81h Don’t Care ID data ID data ID data ID data ID data
UniqueId1 VIL VIL VIH 82h Don’t Care ID data ID data ID data ID data ID data
UniqueId2 VIL VIL VIH 83h Don’t Care ID data ID data ID data ID data ID data
UniqueId3 VIL VIL VIH 84h Don’t Care ID data ID data ID data ID data ID data
OTP0 VIL VIL VIH 85h Don’t Care OTP data OTP data OTP data OTP data OTP data
OTP1 VIL VIL VIH 86h Don’t Care OTP data OTP data OTP data OTP data OTP data
OTP2 VIL VIL VIH 87h Don’t Care OTP data OTP data OTP data OTP data OTP data
OTP3 VIL VIL VIH 88h Don’t Care OTP data OTP data OTP data OTP data OTP data
9/42
M28W320CT, M28W320CB
INSTRUCTIONS AND COMMANDSSixteen instructions are available (see Tables9
and10)to perform Read Memory Array, Read Sta-
tus Register, Read Electronic Signature, CFI Que-
ry, Erase, Program, Double Word Program, Clear
Status Register, Program/Erase Suspend, Pro-
gram/Erase Resume, Block Protect, Block Unpro-
tect, Block Lockand Protection Register Program.
Status Register output maybe readat any time,
during programmingor erase,to monitor the
progressofthe operation. internal Command Interface (C.I.) decodesthe
instructions whilean internal Program/Erase Con-
troller (P/E.C.) handlesall timing and verifiesthe
correct executionof the Program and Erasein-
structions. P/E.C. providesa Status Register
whose bits indicate operation andexit status ofthe
internal algorithms.
The Command Interfaceis resetto Read Array
when poweris first applied, when exiting fromRe-
setor whenever VDDis lower than VLKO. Com-
mand sequence mustbe followed exactly. Any
invalid combinationof commandswill resetthede-
viceto Read Array.
Read (RD)The Read instruction consistsof one write cycle
(referto Device Operations section) giving the
command FFh. Next read operationswill readthe
addressed location and outputthe data. Whena
device reset occurs,the memoryisin Read Array default.
Read Status Register (RSR)The Status Register indicates whena programor
erase operationis complete andthe successor
failureof operation itself. Issuea Read Status
Register Instruction (70h)to readthe Status Reg-
ister content. The Read Status Register instruction
maybe issuedat any time, also whena Program/
Erase operationis ongoing. The following Read
operations outputthe contentofthe Status Regis-
ter. The Status Registeris latchedonthe falling
edgeofEorG signals, and canbe read untilEor returnsto VIH. EitherEorG mustbe toggledto
updatethe latched data. Additionally, any readat-
tempt during programor erase operationwill auto-
matically outputthe contentofthe Status Register.
Read Electronic Signature (RSIG)The Read Electronic Signature instruction con-
sistsof one write cycle (referto Device Operations
section) giving the command 90h.A subsequent
readwill outputthe Manufacturer Code,the De-
vice Code,the Block protection Status,orthe Pro-
tection Register. See Tables6,7 and8for the
valid address. The Electronic Signature canbe
read from the memory allowing programming
equipmentor applicationsto automatically match
their interface to the characteristics of
M28W320C.
CFI Query (RCFI)The Common Flash Interface Query modeisen-
teredby writing 98h. Next readoperationswill read
theCFI data. TheCFI data structure contains also security area;inthis section,a64bit uniquese-
curity numberis written, startingat this address
81h. This areacanbe accessed onlyin read mode
and thereareno waysof changingthe code afterhas been writtenbyST. Writea read instruction returnto Read mode (referto the Common
Flash Interface section).
Table9. Commands
Hex Code Command00h Invalid/Reserved
10h Alternative Program Set-up
20h Erase Set-up
30h Double Word Program Set-up
40h Program Set-up
50h Clear Status Register
70h Read Status Register
90hor98h Read Electronic Signature,or
CFI Query
B0h Program/Erase Suspend
D0h Program/Erase Resume, Erase
Confirmor Unprotect Confirm
FFh Read Array
01h Protect Confirm
2Fh Lock Confirm
C0h Protection Program
60h Protection Set-up
M28W320CT, M28W320CB10/42
Status Registerbitb7 returns’0’ whilethe erasurein progress and’1’ whenit has completed. After
completionthe Status Registerbitb5 returns’1’if
there has beenan Erase Failure. Status register
bitb1 returns’1’ifthe useris attemptingto pro-
grama protected block. Status Registerbitb3re-
turnsa’1’if VPPis below VPPLK.
Erase abortsifRP turnsto VIL.As data integrity
cannotbe guaranteed whenthe erase operationis
aborted,the erase mustbe repeated.A Clear Sta-
tus Register instruction must beissuedto resetb1,
b3,b4 andb5ofthe Status Register. Duringthe
executionofthe erasebythe P/E.C.,the memory
accepts onlythe RSR (Read Status Register) and
PES (Program/Erase Suspend) instructions.
Table10. InstructionsNote:1.X= Don’t Care.Thefirst cycleoftheRD, RSR, RSIGor RCFI instructionis followedbyread operationsin thememory arrayor specialregister.Any
numberofread cyclecan occurafterone command cycle.The signature address recognizedare listedinthe Tables6,7and8. Address1and Address2mustbe consecutive address differingonlyfor addressbitA0.Aread cycleaftera CLSR instructionwill outputthe memory array.
Mne-
monic Instruction Cycles 1st Cycle 2nd Cycle 3nd Cycle
Operat. Addr.(1) Data Operat. Addr. Data Operat. Addr. Data Read Memory
Array 1+ Write X FFh Read(2) Read
Address Data
RSR Read Status
Register 1+ Write X 70h Read(2) X Status
Register
RSIG
Read
Electronic
Signature Write X 90hor
98h Read(2) Signature
Address(3) Data
RCFI ReadCFI 1+ Write 55h 98hor
90h Read(2) CFI
Address Query Erase 2 Write X 20h Write Block
Address D0h Program 2 Write X 40hor
10h Write Address Data
Input
DPG(4) Double Word
Program 3 Write X 30h Write Address1 Data
Input Write Address2 Data
Input
CLRS(5) Clear Status
Register 1 Write X 50h
PES
Program/
Erase
Suspend Write X B0h
PER
Program/
Erase
Resume Write X D0h Block Protect 2 Write X 60h Write Block
Address 01h Block
Unprotect 2 Write X 60h Write Block
Address D0h Block Lock 2 Write X 60h Write Block
Address 2Fh
PRP
Protection
Register
Program Write X C0h Write Address Data
Input
Erase (EE)Block erasure setsallthebits withinthe selected
blockto’1’. One blockata time canbe erased.Itnot necessaryto programthe block with 00has
the P/E.C.willdoit automatically before erasing.
This instruction uses two write cycles. The first
command writtenis the Erase Setup command
20h. The second commandisthe Erase Confirm
command D0h.An address withinthe blocktobe
erasedis given and latched intothe memory dur-
ingthe inputofthe second command.Ifthe sec-
ond command givenisnotan erase confirm,the
status register bitsb4 andb5areset andthein-
struction aborts.
Read operations output the status register after
erasure has started.
11/42
M28W320CT, M28W320CB
Table11. Protection States(1)Note:1.All blocksare protectedat power-up,sothe default configurationis001or101 accordingtoWP status. Current stateandNextstate givesthe protection statusofa block.The protection statusis definedby thewrite protectpinandby
DQ1(=1fora locked block)andDQ0(=1fora protected block)asreadinthe Read ElectronicSignatureinstructionwithA1=VIH
andA0=VIL. Nextstateis theprotection statusof ablockafter aProtect orUnprotect orLock commandhasbeen issuedor afterWP haschanged
itslogic value.AWP transitiontoVIHona locked blockwill restorethe previousDQ0 value, givinga111or110.
Table12. Status Register BitsNote: Logiclevel’1’is High,’0’isLow.
Current State(2) Next State After Event(3)
(WP,DQ1, DQ0) Program/Erase
Allowed Protect Unprotect Lock WP transition100 yes 101 100 111 000
101 no 101 100 111 001
110 yes 111 110 111 011
111 no 111 110 111 011
000 yes 001 000 011 100
001 no 001 000 011 101
011 no 011 011 011 111or110(4)
Mnemonic Bit Name Logic
Level Definition NoteP/ECS 7 P/E.C. Status
’1’ Ready Indicatesthe P/E.C. status, check during
Programor Erase,andon completion before
checkingbitsb4orb5for Programor Erase
Success.’0’ Busy
ESS 6
Erase
Suspend
Status
’1’ Suspended Onan Erase Suspend instruction P/ECSand
ESSbitsaresetto’1’. ESSbit remains ’1’untilan
Erase Resume instructionis given.’0’ In progressor
Completed 5 Erase Status
’1’ Erase Error ESbitissetto’1’if P/E.C.has appliedthe
maximum numberof erase pulsestothe block
without achievingan erase verify.’0’ Erase Success 4 Program
Status
’1’ Program Error PSbitsetto’1’ifthe P/E.C.has failedto program word.’0’ Program Success
VPPS 3 VPPStatus
’1’ VPP Invalid, Abort VPPSbitissetiftheVPP voltageis below VPPLK
whena Programor Erase instructionis executed.
VPPis sampled onlyatthe beginningofthe
erase/program operation.’0’ VPPOK
PSS 2
Program
Suspend
Status
’1’ Suspended Ona Program Suspend instruction P/ECSand
PSSbitsaresetto’1’. PSS remains ’1’untila
Program Resume Instructionis given.’0’ In Progressor
Completed
BPS 1
Block
Protection
Status
’1’
Program/Eraseon
protected Block,
Abort BPSbitissetto’1’ifa Programor Erase
operationhas been attemptedona protected
block.
’0’ No operationto
protected blocks Reserved
M28W320CT, M28W320CB12/42
Program (PG)The memory array canbe programmed word-by-
word. This instruction uses two write cycles. The
first command writtenisthe Program Set-up com-
mand 40h(or 10h).A second write operation latch- the Address and the Datatobe written and
startsthe P/E.C.
Read operations outputthe Status Register con-
tent afterthe programming has started. The Status
Registerbitb7 returns’0’ whilethe programmingin progress and’1’ whenit has completed. After
completionthe Status registerbitb4 returns’1’if
there has beena Program Failure. Status register
bitb1 returns’1’ifthe useris attemptingto pro-
grama protected block. Status Registerbitb3re-
turnsa’1’if VPPis below VPPLK. Programming
abortsifRP goesto VIL.As data integrity cannot guaranteed when the program operationis
aborted,the memory location mustbe erased and
reprogrammed.A Clear Status Register instruc-
tion mustbe issuedto resetb4,b3 andb1ofthe
Status Register.
Duringthe executionofthe programbythe P/E.C.,
the memory accepts onlythe RSR (Read Status
Register) and PES (Program/Erase Suspend)in-
structions.
Double Word Program (DPG)This featureis offeredto improvethe programming
throughput, writinga pageof two adjacent words parallel.Thetwo words must differ onlyforthe
addressA0. Programming shouldnotbe attempt- when VPPisnotat VPPH. The operation can
alsobe executedif VPPis below VPPHbut result
couldbe uncertain. This instruction uses three
write cycles. The first command writtenisthe Dou-
ble Word Program Set-Up command 30h.A sec-
ond write operation latchesthe Address andthe
Dataofthe first wordtobe written,the third write
operation latchesthe Address andthe Dataofthe
second wordtobe written and startsthe P/E.C.
Read operations outputthe Status Register con-
tent afterthe programming has started. The Status
Registerbitb7 returns’0’ whilethe programmingin progress and’1’ whenit has completed. After
completionthe Status registerbitb4 returns’1’if
there has beena Program Failure. Status register
bitb1 returns’1’ifthe useris attemptingto pro-
grama protected block. Status Registerbitb3re-
turnsa’1’if VPPis below VPPLK. Programming
abortsifRP goesto VIL.As data integrity cannot guaranteed when the program operationis
aborted,the memory location mustbe erased and
reprogrammed.A Clear Status Register instruc-
tion mustbe issuedto resetb4,b3 andb1ofthe
Status Register.
Duringthe executionofthe programbythe P/E.C.,
the memory accepts onlythe RSR (Read Status
Register) and PES (Program/Erase Suspend)in-
structions.
Clear Status Register (CLRS)The Clear Status Register usesa single writeop-
eration which clearsbitsb1,b3,b4 andb5to0.Its
useis necessary before any new operation when error has been detected.
The Clear Status Registeris executed writingthe
command 50h.
Program/Erase Suspend (PES)Program/Erase suspendis accepted only during
the Program Erase instruction execution. Whena
Program/Erase Suspend commandis writtento
the C.I.,the P/E.C. freezesthe Program/Eraseop-
eration. Program/Erase Resume (PER) continues
the Program/Erase operation. Program/Erase
Suspend consistsof writing the command B0h
without any specific address.
The Status Registerbitb2issetto’1’ (within 5μs)
whenthe program has been suspended.b2isset’0’in case the programis completedorin
progress. The Status Registerbitb6issetto’1’
(within 30μs) whenthe erase has been suspend-
ed.b6issetto’0’in casethe eraseis completedin progress. The valid commands while eraseis
suspended are: Program/Erase Resume, Pro-
gram, Read Array, Read Status Register, Read
Identifier, CFI Query, Block Protect, Block Unpro-
tect, Block Lockand Protection Program. The user
can protect the Block being erased issuing the
Block Protect, Block Lockor Protection Program
commands.In this casethe protection statusbit
will change immediately,but whenthe eraseisre-
sumed,the operationwill complete The valid com-
mands while programis suspended are: Program/
Erase Resume, Read Array, Read Status Regis-
ter, Read Identifier, CFI Query.
During program/erase suspend mode, the chip
canbe placedina pseudo-stand-by modeby tak-
ingEtoVIH This reduces active current consump-
tion. Program/Eraseis abortedifRP turnstoVIL.
Program/Erase Resume (PER)a Program/Erase Suspend instruction was previ-
ously executed,the program/erase operation may resumedby issuing the command D0h. The
status registerbit b2/b6is cleared when program/
erase resumes. Read operations outputthe status
register afterthe program/eraseis resumed.
13/42
M28W320CT, M28W320CBThe suggested flow chartsfor programs that use
the programming, erasure and program/erase
suspend/resume featuresof the memories are
shown from Figures11,12,13,14 and15.
Protection Register Program (PRP)The Protection Register Program uses two write
cycles. Thefirst command writtenisthe protection
program command C0h. The second write opera-
tion latchesthe Address andthe Datatobe writtenthe Protection Register (see Protection Register
and Security Block) and startthe PE/C. Readop-
erations outputthe Status Register content after
the programming has started. The64 bits user
programmable Segment (85hto 88h) are pro-
grammed16 bitsata time,it canbe protectedby
the user programmingbit1ofthe Protection Lock
register. Thebit1ofthe Protection Lock register
protectthebit2ofthe Protection Lock Register.
Writingthebit2ofthe Protection Lock Registerwill
resultina permanent protectionof the Security
Block. Attemptingto programa previously protect- protection Registerwill resultina status regis-
ter error(bit1andbit4ofthe status registerwillbe
setto’1’). The protectionofthe Protection Register
and/orthe Security Blockisnot reversible.
The Protection Register Program cannotbe sus-
pended.
Block Protect (BP)TheBP instruction use two write cycles. The first
command writtenisthe protection setup 60h. The
second commandis block Protect command 01h.
The address withinthe block being protected must givenin orderto writethe protection state.Ifthe
second commandisnot recognizedbytheC.Ithe
bit4 andbit5ofthe status registerwillbesettoin-
dicatea wrong sequenceof commands.To read
the status register writethe RSR command.
Block Unprotect (BU)The instructionusetwo write cycles. The first com-
mand writtenisthe protection setup 60h. The sec-
ond commandis block Unprotect command d0h.
The address withinthe block being unprotected
mustbe givenin orderto writethe unprotection
state.Ifthe second commandisnot recognizedby
theC.Ithebit4 andbit5ofthe status registerwill setto indicatea wrong sequenceof com-
mands.To readthe status register writethe RSR
command.
Block Lock (BL)The instructionusetwo write cycles. The first com-
mand writtenisthe protection setup 60h. The sec-
ond commandis block Lock command 2Fh. The
address withinthe block being Locked mustbe
givenin orderto writethe Locking state.Ifthe sec-
ond commandisnot recognizedbythe C.Ithebit4
andbit5ofthe status registerwillbesetto indicate wrong sequenceof commands.To readthe sta-
tus register writethe RSR command.
Table13. Program, Erase Times and Program/Erase Endurance Cycles(TA=0to 70°Cor –40to 85°C; VDD= 2.7Vto 3.6V)
Note:TA =25°C.
Parameter Test Conditions
M28W320C
Unit
Min Typ(1) MaxWord Program VPP =VDD 10 200 μs
Double Word Program VPP=12V ±5% 10 200 μs
Main Block Program
VPP=12V ±5% 0.16 5 sec
VPP =VDD 0.32 5 sec
Parameter Block Program
VPP=12V ±5% 0.02 4 sec
VPP =VDD 0.04 4 sec
Main Block Erase
VPP=12V ±5% 1 10 sec
VPP =VDD 110 sec
Parameter Block Erase
VPP=12V ±5% 0.8 10 sec
VPP =VDD 0.8 10 sec
Program/Erase Cycles(per Block) 100,000 cycles
M28W320CT, M28W320CB14/42
BLOCK PROTECTIONThe M28W320C providea flexible protectionofall
the memory providingthe protection unprotection
and lockingofany blocks.All blocksare protected power-up. Each blockofthe array hastwo lev-
elsof protection against programor erase opera-
tion. The first levelissetby the Block Protect
instruction;a protected block cannot be pro-
grammedor erased untila Block Unprotectin-
structionis givenfor that block.A second levelof
protectionissetbythe Block Lock instruction, and
requiresthe useofthe WP pin, accordingtothe
following scheme: whenWPisat VIH,the Lock statusis overridden
andall blocks canbe protectedor unprotected; when WPisat VIL, Lock statusis enabled;the
locked blocksare protected, regardlessof their
previous protect state, and protection status
cannotbe changed. Blocks thatarenot locked
canstill change their protection status; the lock statusis clearedforall blocksat power
up.
The protection and lock status canbe monitored
for each block usingthe Read Electronic Signature
(RSIG) instruction. Protected blockswill outputa
’1’on DQ0 and locked blockswill outputa’1’in
DQ1.
PROTECTION REGISTER
and SECURITY BLOCKThe M28W320C featuresa 128-bit protection reg-
ister anda security Blockin orderto increasethe
protectionofa system design. The Protection
Registeris dividedin two 64-bit segment. The first
segment (81hto 84h)isa unique device number,
while the second one (85hto 88h) canbe pro-
grammedbythe user. When shippedthe user pro-
grammable segmentis readat’1’.It canbe only
programmedat’0’;
The user programmable segment canbe protect- writingthebit1ofthe Protection Lock register
(80h). Thebit1 protect alsothebit2ofthe Protec-
tion Lock Register. The M28W320C featurease-
curity Block. The security Blockis locatedat
1FF000-1FFFFF (M28W320CT)orat 000000-
000FFF (M28W320CB)ofthe device. This block
canbe permanently protectedby the user pro-
grammingthebit2ofthe Protection Lock Register.
The protection Register andthe Protection Lock
Register canbe read usingthe RSIG command.A
subsequent readinthe address starting from 80h 88h,the userwill retrieve respectivelythe Pro-
tection Lock register, the unique device number
segment andthe OTP user programmable register
segment (see Table8).
Figure4. Security Block Memory MapAI03523
Parameter Block#0
User ProgrammableOTP
Unique device number
Protection RegisterLock 210
88h
85h
84h
81h
80h
15/42
M28W320CT, M28W320CB
POWER CONSUMPTIONThe M28W320C puts itselfin oneof four different
modes dependingonthe statusofthe control sig-
nals: Active Power, Automatic Stand-by, Stand-by
and Reset define decreasing levelsof current con-
sumption. These allowthe memory powertobe
minimised,in turn decreasingthe overall system
power consumption.As different recovery timeare
linkedtothe different modes, please refertothe timing Tableto design your system.
Active PowerWhenEisatVIL andRPisat VIH,the deviceisin
active mode. Referto DC Characteristicstoget
the valuesofthe current supply consumption.
Automatic Stand-byAutomatic Stand-by providesa low power con-
sumption state during read mode. Followinga
read operation, aftera delay closetothe memory
access time,the device enters Automatic Stand-
by:the Supply Currentis reducedto ICC1 values.
The device keepsthelast output data stable,tilla
new locationis accessed.
Stand-byor ResetRefertothe Device Operations section.
PowerUpThe Supply voltage VDD andthe Program Supply
voltage VPP canbe appliedin any order. The
memory Command Interfaceis reseton powerup Read Memory Array,buta negative transitionof
Chip EnableEora changeofthe addressesisre-
quiredto ensure valid data outputs. Care mustbe
takento avoid writestothe memory when VDDis
above VLKO. Writes canbe inhibitedby drivingei-
therEorWto VIH. The memoryis disabledifRPat VIL.
Supply RailsNormal precautions mustbe takenfor supply volt-
age decoupling, each deviceina system should
have the VDD and VPP rails decoupled witha
0.1μF capacitor closetothe VDD and VPP pins.The
PCB trace widths shouldbe sufficientto carrythe
required VPP program and erase currents.
M28W320CT, M28W320CB16/42
COMMON FLASH INTERFACE (CFI)The Common Flash Interface (CFI) specificationis JEDEC approved, standardised data structure
that canbe read fromthe Flash memory device.
CFI allowsa system softwareto querythe flash
deviceto determine various electrical and timing
parameters, density information and functions
supportedbythe device. CFI allowsthe systemto
easily interfaceto the Flash memory,to learn
aboutits features and parameters, enablingthe
softwareto configure itself when necessary.
Tables14,15,16,17,18 and19 showthe address
usedto retrieve each data.
The CFI data structure gives informationonthe
device, suchas the sectorization,the command
set and some electrical specifications. Tables14,
15,16 and17 showthe addresses usedto retrieve
each data. TheCFI data structure contains alsoa
security area;inthis section,a64bit unique secu-
rity numberis written, startingat address 81h. This
areacanbe accessed onlyin read mode and there
areno waysof changingthe code afterit has been
writtenby ST. Writea read instructionto returnto
Read mode. Refertothe CFI Query instructionto
understand how the M28W320C enters the CFI
Query mode.
Table14. Query Structure OverviewNote:The Flash memory displaytheCFIdata structure whenCFI Query commandis issued.Inthis tableare listedthe main sub-sections
detailedin Tables 15,16,17,18and19. Querydataare always presentedonthe lowest orderdata outputs.
Table15. CFI Query Identification StringNote: Querydataare always presentedonthe lowest- orderdata outputs (DQ7-DQ0)only. DQ8-DQ15are‘0’.
Offset Sub-section Name Description00h Reserved Reservedfor algorithm-specific information
10h CFI Query Identification String CommandsetIDand algorithm data offset
1Bh System Interface Information Device timing& voltage information
27h Device Geometry Definition Flash device layout Primary Algorithm-specific Extended Query table Additional information specifictothe Primary
Algorithm (optional) Alternate Algorithm-specific Extended Query table Additional information specifictothe Alternate
Algorithm (optional)
Offset Data Description00h 0020h Manufacturer Code
01h 88BAh-top
88BBh- bottom Device Code
02h-0Fh reserved Reserved
10h 0051h Query Unique ASCII String ”QRY”
11h 0052h Query Unique ASCII String ”QRY”
12h 0059h Query Unique ASCII String ”QRY”
13h 0003h Primary Algorithm CommandSetand Control InterfaceID code16bitID code
defininga specific algorithm14h 0000h
15h offset=P= 0035h
Addressfor Primary Algorithm extended Query table
16h 0000h
17h 0000h Alternate Vendor CommandSetand Control InterfaceID Code second vendor specified algorithm supported (note: 0000h means none exists)18h 0000h
19h value=A= 0000h Addressfor Alternate Algorithm extended Query table
note: 0000h means none exists1Ah 0000h
17/42
M28W320CT, M28W320CB
Table16. CFI Query System Interface Information
Offset Data Description1Bh 0027h
VDD Logic Supply Minimum Program/Eraseor Write voltage
bit7to4 BCD valuein volts
bit3to0 BCD valuein100mV
1Ch 0036h
VDD Logic Supply Maximum Program/Eraseor Write voltage
bit7to4 BCD valuein volts
bit3to0 BCD valuein100mV
1Dh 00B4h
VPP [Programming] Supply Minimum Program/Erase voltage
bit7to4 HEX valuein volts
bit3to0 BCD valuein100mV
Note: This value mustbe 0000hifnoVPPpinis present
1Eh 00C6h
VPP [Programming] Supply Maximum Program/Erase voltage
bit7to4 HEX valuein volts
bit3to0 BCD valuein100mV
Note: This value mustbe 0000hifnoVPPpinis present
1Fh 0004h Typical timeoutper single byte/word program (multi-byte program count=1),2nμs
(if supported; 0000h=not supported)
20h 0000h Typical timeoutfor maximum-size multi-byte programor page write,2nμs
(if supported; 0000h=not supported)
21h 000Ah Typical timeoutper individual block erase,2nms
(if supported; 0000h=not supported)
22h 0000h Typical timeoutforfullchip erase,2nms
(if supported; 0000h=not supported)
23h 0004h Maximum timeoutfor byte/word program,2n times typical (offset 1Fh)
(0000h=not supported)
24h 0000h Maximum timeoutfor multi-byte programor page write,2n times typical (offset 20h)
(0000h=not supported)
25h 0003h Maximum timeoutper individual block erase,2n times typical (offset 21h)
(0000h=not supported)
26h 0000h Maximum timeoutforchip erase,2n times typical (offset 22h)
(0000h=not supported)
M28W320CT, M28W320CB18/42
Table17. Device Geometry Definition
Offset Word
Mode Data Description27h 0016h Device Size=2nin numberof bytes
28h 0001h Flash Device Interface Code description: Asynchronousx1629h 0000h
2Ah 0000h
Maximum numberof bytesin multi-byte programor page=2n
2Bh 0000h
2Ch 0002h Numberof Erase Block Regions within device
bit7to0=x= number ofErase Block Regions
Note:1.x=0 meansno erase blocking,i.e.the device erasesat oncein ”bulk.”x specifiesthe numberof regions withinthe device containingoneor more con-
tiguous Erase Blocksofthe same size. For example,a 128KB device (1Mb)
having blockingof 16KB, 8KB,four 2KB,two 16KB,andone 64KBis consid-
eredto have5 Erase Block Regions. Even thoughtwo regions both contain
16KB blocks,thefactthat theyarenot contiguous means theyare separate
Erase Block Regions.By definition, symmetrically block devices have onlyone blocking region.
M28W320CT M28W320CT Erase Block Region Information
bit31to16=z, wherethe Erase Block(s) withinthis Regionare(z) times256 bytesin
size. The valuez=0is usedfor128 byte block size.
e.g.for 64KB block size,z= 0100h=256=>256*256=64K
bit15to0=y, wherey+1= Numberof Erase Blocksof identicalsize withinthe Erase
Block Region:
e.g.y= D15-D0= FFFFh=>y+1=64K blocks [maximum number]=0 meansno blocking(# blocks=y+1=”1 block”)
Note:y=0 value mustbe usedwith numberof block regionsofoneas indicated(x)=0
2Dh 001Eh
2Eh 0000h
2Fh 0000h
30h 0001h
31h 0007h
32h 0000h
33h 0020h
34h 0000h
M28W320CB M28W320CB
2Dh 0007h
2Eh 0000h
2Fh 0020h
30h 0000h
31h 001Eh
32h 0000h
33h 0000h
34h 0001h
19/42
M28W320CT, M28W320CB
Table18. Primary Algorithm-Specific Extended Query Table
Table19. Security Code Area
Offset Data Description(P)h=35h 0050h
Primary Algorithm extended Query table unique ASCII string “PRI”0052h
0049h
(P+3)h=38h 0031h Major version number, ASCII
(P+4)h=39h 0030h Minor version number, ASCII
(P+5)h=3Ah 0006h Extended Query table contentsfor Primary Algorithm
bit0 Chip Erase supported (1= Yes,0=No)
bit1 Erase Suspend supported (1= Yes,0=No)
bit2 Program Suspend (1= Yes,0=No)
bit3 Lock/Unlock supported (1= Yes,0=No)
bit4 Quequed Erase supported (1= Yes,0=No)
bit31to5 Reserved; undefinedbitsare‘0’
0000h
(P+7)h 0000h
(P+8)h 0000h
(P+9)h=3Eh 0001h Supported Functions after Suspend
Read Array, Read Status RegisterandCFI Queryare always supported during Eraseor
Program operation
bit0 Program supported after Erase Suspend(1= Yes,0=No)
bit7to1 Reserved; undefinedbitsare‘0’
(P+A)h=3Fh 0000h Block Lock Status
Defines whichbitsinthe Block Status Register sectionofthe Queryare implemented.
bit0 Block Lock StatusRegister Lock/Unlockbit active(1= Yes,0=No)
bit1 Block Lock StatusRegister Lock-Downbit active(1= Yes,0=No)
bit15to2 Reservedfor futureuse; undefinedbitsare‘0’
(P+B)h 0000h
(P+C)h=41h 0027h VDD Logic Supply Optimum Program/Erase voltage (highest performance)
bit7to4 HEX valuein volts
bit3to0 BCD valuein100mV
(P+D)h=42h 00C0h VPP Supply Optimum Program/Erase voltage
bit7to4 HEX valuein volts
bit3to0 BCD valuein100mV
(P+E)h 0000h Reserved
Offset Data Description80h 00XX Protection Register Lock
81h XXXX bits: unique device number82h XXXX
83h XXXX
84h XXXX
85h XXXX bits: User Programmable OTP86h XXXX
87h XXXX
88h XXXX
M28W320CT, M28W320CB20/42
Table20.DC Characteristics(TA=0to 70°Cor –40to 85°C; VDD =VDDQ= 2.7Vto 3.6V)
Symbol Parameter Test Condition Min Typ Max UnitILI Input Leakage Current 0V≤VIN≤ VDDQ ±1 μA
ILO Output Leakage Current 0V≤ VOUT ≤VDDQ ±10 μA
ICC Supply Current (Read) E= VSS,G=VIH,f= 5MHz 10 20 mA
ICC1 Supply Current (Stand-byor
Automatic Stand-by) VDDQ± 0.2V,= VDDQ± 0.2V 15 50 μA
ICC2 Supply Current
(Reset) RP=VSS± 0.2V 15 50 μA
ICC3 Supply Current (Program)
Programin progress
VPP=12V±5% 10 20 mA
Programin progress
VPP =VDD 10 20 mA
ICC4 Supply Current (Erase)
Erasein progress
VPP=12V±5% 520 mA
Erasein progress
VPP =VDD 520 mA
ICC5 Supply Current
(Program/Erase Suspend)
E=VDDQ± 0.2V,
Erase suspended 50 μA
IPP Program Current
(Reador Stand-by) VPP >VDD 400 μA
IPP1 Program Current
(Reador Stand-by) VPP≤ VDD 5 μA
IPP2 Program Current (Reset) RP=VSS± 0.2V 5 μA
IPP3 Program Current (Program)
Programin progress
VPP=12V±5% 10 mA
Programin progress
VPP =VDD 5 μA
IPP4 Program Current (Erase)
Erasein progress
VPP=12V±5% 10 mA
Erasein progress
VPP =VDD 5 μA
VIL Input Low Voltage –0.5 0.4 V
VDDQ≥ 2.7V –0.5 0.8 V
VIH Input High Voltage
VDDQ –0.4 VDDQ +0.4 V
VDDQ≥ 2.7V 0.7 VDDQ VDDQ +0.4 V
VOL OutputLow Voltage IOL= 100μA,VDD =VDD min,
VDDQ =VDDQmin 0.1 V
VOH Output High Voltage IOH= –100μA,VDD =VDDmin,
VDDQ =VDDQmin VDDQ –0.1 V
VPP1 Program Voltage(Programor
Erase operations) 1.65 3.6 V
VPPH
Program Voltage
(Programor Erase
operations)
11.4 12.6 V
VPPLK Program Voltage
(Programand Erase lock-out) 1V
VLKO VDD Supply Voltage (Program
and Erase lock-out) 2V
21/42
M28W320CT, M28W320CB
Figure6.AC Testing Load CircuitAI00609BDDQ/2
OUT= 50pFL includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table21.AC Measurement ConditionsInput RiseandFall Times ≤ 10ns
Input Pulse Voltages 0to VDDQ
Inputand Output Timing Ref. Voltages VDDQ/2
Figure5.AC Testing Input Output WaveformAI00610
VDDQ
VDDQ/2
Table22. Capacitance(1)(TA =25°C,f=1 MHz)
Note:1. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min Max UnitCIN Input Capacitance VIN =0V 6pF
COUT Output Capacitance VOUT =0V 12 pF
