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M28F101-120P1 |M28F101120P1N/a22avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-100K1 |M28F101100K1STN/a550avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-100K1 |M28F101100K1GSN/a288avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-120K1 |M28F101120K1STMN/a30avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-120K6 |M28F101120K6STN/a21avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-120N1 |M28F101120N1STN/a2000avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-120N3 |M28F101120N3STN/a2000avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-120N6 |M28F101120N6STN/a2000avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-120P1 |M28F101120P1STN/a303avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-150K1 |M28F101150K1STN/a5120avaiMemory configuration 128Kx8 Memory type Flash Memory size 1 M-bit 1Mb (128K8) FLASH memory
M28F101-150K6 |M28F101150K6STN/a6250avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-150P1 |M28F101150P1STN/a2160avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-150P6 |M28F101150P6STN/a4avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-200K1 |M28F101200K1STN/a200avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-200K6 |M28F101200K6STN/a15avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-90K1 |M28F10190K1STN/a2000avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-90K3 |M28F10190K3STN/a2000avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-90K6 |M28F10190K6STN/a2000avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101-90N1 |M28F10190N1STN/a674avai1 Mb 128K x 8/ Chip Erase FLASH MEMORY


M28F101-150K6 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYM28F1011 Mb (128K x 8, Chip Erase) FLASH MEMORY5V ±10% SUPPLY VOLTAGE12V PROGRAMMING VOLTAGEFAST AC ..
M28F101-150P1 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYM28F1011 Mb (128K x 8, Chip Erase) FLASH MEMORY5V ±10% SUPPLY VOLTAGE12V PROGRAMMING VOLTAGEFAST AC ..
M28F101-150P6 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYAbsolute Maximum RatingsSymbol Parameter Value UnitT Ambient Operating Temperature –40 to 125 °CATS ..
M28F101-200K1 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYLogic Diagramchip level and programmed byte-by-byte. It is or-ganisedas 128K bytes of 8 bits.It use ..
M28F101-200K6 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYapplications where the memory has to be repro-V VCC PPgrammed in the equipment. The access time of7 ..
M28F101-90K1 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYAbsolute Maximum RatingsSymbol Parameter Value UnitT Ambient Operating Temperature –40 to 125 °CATS ..
M4N26 ,6-Pin DIP Optoisolators Transistor Output
M4N37 ,6-Pin DIP Optoisolators Transistor Output
M4T28-BR12SH ,TIMEKEEPER SNAPHAT Battery & CrystalAbsolute Maximum Ratings . 7DC and AC PARAMETERS . . 8Table 3. DC and AC Measurement Co ..
M4T28-BR12SH1 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)M4T28-BR12SHM4T32-BR12SH® ®TIMEKEEPER SNAPHAT (Battery & Crystal)
M4T32-BR12SH1 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)Logic Diagram Table 1. Signal NamesX1 Crystal InputX2 Crystal OutputX1 X2V Negative VoltageBAT–V Po ..
M4T32-BR12SH6 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)TABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..


M28F101-100K1-M28F101-120K1-M28F101-120K6-M28F101-120N1-M28F101-120N3-M28F101-120N6-M28F101-120P1-M28F101-150K1-M28F101-150K6-M28F101-150P1-M28F101-150P6-M28F101-200K1-M28F101-200K6-M28F101-90K1-M28F101-90K3-M28F101-90K6-M28F101-90N1
1 Mb 128K x 8/ Chip Erase FLASH MEMORY
M28F101 Mb (128Kx8, Chip Erase) FLASH MEMORY
April 1997 1/23
AI00666B
A0-A16
DQ0-DQ7
VPPVCC
M28F101
VSS
Figure1. Logic Diagram
±10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 70ns
BYTE PROGRAMING TIME: 10μs typical
ELECTRICALCHIP ERASEin1s RANGE
LOW POWER CONSUMPTION Stand-by Current: 100μAmax
10,000 ERASE/PROGRAM CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and PINOUTS
ELECTRONIC SIGNATURE ManufacturerCode: 20h Device Code: 07h
DESCRIPTION

The M28F101 FLASH Memoryisa non-volatile
memory which maybe erased electricallyatthe
chip level and programmed byte-by-byte.Itisor-
ganisedas128Kbytesof8 bits.It usesa command
register architectureto selectthe operating modes
and thus providesa simple microprocessor inter-
face. The M28F101 FLASH Memoryis suitablefor
applications wherethe memory hastobe repro-
grammedin the equipment. The access timeof
70ns makes the device suitablefor usein high
speed microprocessor systems.
A0-A16 Address Inputs
DQ0-DQ7 Data Inputs/ Outputs Chip Enable Output Enable Write Enable
VPP Program Supply
VCC SupplyVoltage
VSS Ground
Table1. Signal Names

PLCC32(K)
PDIP32(P)
TSOP32(N)x20mm
AI00668
A13
A10
DQ5
DQ0
DQ1DQ2 DQ3DQ4
A16
DQ7
A12
A14
M28F101
A15
A11
DQ6
Figure2B. LCCPin Connections

DQ0
A13
A10
DQ7
A14
A11
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6A16
A12
VPP VCC
A15
AI00667
M28F1018
Figure2A. DIPPin Connections

DQ0 A3
A13
A10
DQ7
A14
A11 G
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A16
A12
VPP
VCC
A15
AI00669B
M28F101
(Normal) 17
VSS
Figure2C. TSOPPin Connections

DQ0A3
A13
A10
DQ7
A14
A11G
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A16
A12PP
VCC
A15
AI00670C
M28F101
(Reverse) 17SS
Figure2D. TSOPReversePin Connections
Warning:
NC=Not Connected.
Warning:
NC=Not Connected. Warning:NC=Not Connected.
Warning:
NC=Not Connected.
2/23
M28F101
Symbol Parameter Value Unit Ambient Operating Temperature –40to125 °C
TSTG Storage Temperature –65 to150 °C
VIO Inputor Output Voltages –0.6to7 V
VCC Supply Voltage –0.6to7 V
VA9 A9 Voltage –0.6to13.5 V
VPP Program Supply Voltage, during Erase Programming –0.6to14 V
Note:
Exceptforthe rating ”Operating Temperature Range”, stresses above those listedinthe Table”AbsoluteMaximum Ratings”may
cause permanentdamage tothe device. Theseare stress ratingsonlyand operation ofthe deviceat theseorany other conditions above
those indicatedinthe Operating sectionsofthis specificationis notimplied. Exposureto AbsoluteMaximum Rating conditionsfor extended
periodsmay affect device reliability.Referalsotothe SGS-THOMSON SURE Programand otherrelevant quality documents.
Table2. Absolute Maximum Ratings
DEVICE OPERATION

The M28F101 FLASH Memory employs atechnol-
ogy similartoa1 Megabit EPROMbut addstothe
device functionalityby providing electrical erasure
and programming. These functionsare manageda command register. The functions that are
addressedvia the command register dependon
the voltage appliedtothe VPP, program voltage,
input. When VPPis less thanor equalto 6.5V,the
command registeris disabled and M28F101 func-
tionsasa read only memory providing operating
modes similartoan EPROM (Read, Output Dis-
able, Electronic Signature Read and Standby).
When VPPis raisedto 12Vthe command regsiter enabled andthis provides,in addition, Eraseand
Program operations.
READ ONLY MODES, VPP
6.5V
Forall Read Only Modes, except Standby Mode,
the Write Enable inputW shouldbe High.Inthe
StandbyModethis inputis don’t care.
Read Mode.
TheM28F101 hastwo enable inputs, andG, bothof which mustbe Lowin orderto
output data fromthe memory. The Chip Enable(E)the power control and shouldbe usedfor device
selection. Output Enable(G)isthe output control
and shouldbe usedto gate dataontothe output,
independantofthe device selection.
Standby Mode.
Inthe Standby Modethe maxi-
mum supply currentis reduced. The deviceis
placedinthe StandbyModeby applyinga Highto
the Chip Enable(E) input. Wheninthe Standby
Modethe outputsareina high impedance state,
independantofthe Output Enable(G) input.
Output Disable Mode.
Whenthe Output Enable
(G)is Highthe outputsareina high impedance
state.
ElectronicSignature Mode.
This mode allowsthe
read outoftwo binary codes fromthe device which
identify the manufacturer and device type. This
modeis intendedfor useby programming equip-
mentto automatically selectthe correct erase and
programming algorithms. The Electronic Signature
Modeis active whena high voltage (11.5Vto 13V)
isappliedto addresslineA9withE andG Low.With Lowthe output dataisthe manufacturercode,
whenA0is Highthe outputisthe device type code.
All other address lines shouldbe maintainedLow
while readingthe codes. The electronic signature
may alsobe accessedin Read/Write modes.
READ/WRITE MODES, 11.4V
VPP 12.6V
When VPPis High both read and write operations
maybe performed. Theseare definedbythe con-
tentsofan internal command register. Commands
maybe writtento this registerto set-up and exe-
cute, Erase, Erase Verify, Program,ProgramVerify
and Reset modes. Eachof these modes needs2
cycles. Eah mode starts witha write operationto
set-upthe command,thisis followed byeither read write operations. The device expectsthe first
cycletobea write operation and doesnot corrupt
dataat any locationinthe memory. Read modeis
set-up with one cycle only and maybe followedby
any numberof read operationsto output data.
Electronic Signature Read modeis set-up with one
cycle and followedbya read cycleto outputthe
manufactureror device codes.
3/23
M28F101
Command Cycles 1st Cycle 2nd Cycle
Operation A0-A16 DQ0-DQ7 Operation A0-A16 DQ0-DQ7

Read 1 Write X 00h
Electronic
Signature(2) 2 Write X 90h Read 00000h 20h
Read 00001h 07h
Setup Erase/ 2 Write X 20h
Erase Write X 20h
Erase Verify 2 Write A0-A16 A0h Read X Data Output
Setup Program/ 2 Write X 40h
Program Write A0-A16 Data Input
Program Verify 2 Write X C0h Read X Data Output
Reset 2 Write X FFh Write X FFh
Notes:
1.X=VILorVIH. Referalsotothe Electronic Signature table.
Table5. Commands(1)
Identifier A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex Data

Manufacturer’s Code VIL 001 00 00 0 20h
Device Code VIH 000 00 11 1 07h
Table4. Electronic Signature
VPP Operation E G W A9 DQ0- DQ7

Read Only VPPL
Read VIL VIL VIH A9 Data Output
Output Disable VIL VIH VIH X Hi-Z
Standby VIH X X X Hi-Z
Electronic Signature VIL VIL VIH VID Codes
Read/Write(2) VPPH
Read VIL VIL VIH A9 Data Output
Write VIL VIH VIL Pulse A9 Data Input
Output Disable VIL VIH VIH X Hi-Z
Standby VIH X X X Hi-Z
Notes:
1.X=VILorVIH. Referalsotothe Command table.
Table3. Operations(1)

4/23
M28F101
AI01275
SRAM Interface
1.5V
2.4V
EPROM Interface
0.45V
2.0V
0.8V
Figure3.AC TestingInput Output Waveform

AI01276
1.3V
OUT= 30pFor 100pFL= 30pFfor SRAM Interface= 100pF forEPROM Interface includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Figure4.AC Testing Load Circuit
SRAM Interface Levels EPROM Interface Levels

Input RiseandFall Times ≤ 10ns ≤ 10ns
Input Pulse Voltages 0to3V 0.45Vto 2.4V
Inputand Output TimingRef. Voltages 1.5V 0.8Vand2V
Table6. AC Measurement Conditions
Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6 pF
COUT Output Capacitance VOUT =0V 12 pF
Note:
1. Sampledonly,not 100% test.ed
Table7. Capacitance(1)
(TA =25°C,f=1 MHz)
Awriteto thecommand registerismadeby bringing
WLow while EisLow. The falling edge ofW latches
Addresses, while the rising edge latches Data,
whichare usedfor those commands that require
address inputs, command inputor provide data
output.
The supply voltage VCC andthe program voltage
VPP canbe appliedin any order. Whenthe device poweredupor when VPPis≤ 6.5Vthe contents the command register defaultsto 00h, thus
automatically setting-up Read operations.In addi-
tiona specific command maybe usedtosetthe
command registerto 00hfor readingthe memory.
The system designer may choseto providea con-
stant high VPP and usethe register commandsfor
all operations,orto switchthe VPP fromlowto high
only when needingto eraseor programthe mem-
ory.All command register accessis inhibited when
VCC falls belowthe Erase/Write Lockout Voltage
(VLKO)of 2.5V.the deviceis deselected during Erasure, Pro-
grammingor Verificationitwill draw active supply
currents untilthe operationsare terminated.
The deviceis protected against stress causedby
long eraseor program times.Ifthe endof Eraseor
Programming operationsarenot terminatedbya
Verify cycle withina maximum time permitted,an
internal stop timer automatically stopsthe opera-
tion. The device remainsinan inactive state, ready starta Verifyor Reset Mode operation.
READ/WRITE MODES
(cont’d)
5/23
M28F101
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤VIN≤VCC ±1 μA
ILO Output Leakage Current 0V≤ VOUT≤VCC ±10 μA
ICC Supply Current (Read) E=VIL,f= 6MHz 30 mA
ICC1 Supply Current (Standby)TTL E=VIH 1mA
Supply Current (Standby) CMOS E=VCC± 0.2V 50 μA
ICC2(1) Supply Current (Programming) DuringProgramming 10 mA
ICC3(1) Supply Current (Program Verify) During Verify 15 mA
ICC4(1) Supply Current (Erase) During Erasure 15 mA
ICC5(1) Supply Current (Erase Verify) During Erase Verify 15 mA
ILPP Program Leakage Current VPP≤VCC ±10 μA
IPP Program Current (Reador
Standby)
VPP >VCC 120 μA
VPP≤VCC ±10 μA
IPP1(1) Program Current (Programming) VPP =VPPH, During Programming 30 mA
IPP2(1) Program Current (Program
Verify) VPP =VPPH, During Verify 5 mA
IPP3(1) Program Current (Erase) VPP =VPPH, During Erase 30 mA
IPP4(1) Program Current (Erase Verify) VPP =VPPH, During Erase Verify 5 mA
VIL InputLow Voltage –0.5 0.8 V
VIH Input High VoltageTTL 2 VCC+0.5 V
Input High Voltage CMOS 0.7VCC VCC+0.5 V
VOL OutputLow Voltage IOL= 5.8mA (grade1) 0.45 V
IOL= 2.1mA (grade6) 0.45 V
VOH Output High Voltage CMOS IOH= –100μA 4.1 V
IOH= –2.5mA 0.85VCC V
Output High VoltageTTL IOH= –2.5mA 2.4 V
VPPL Program Voltage (Read
Operations) 0 6.5 V
VPPH Program Voltage (Read/Write
Operations) 11.4 12.6 V
VID A9 Voltage (Electronic Signature) 11.5 13 V
IID(1) A9 Current (Electronic Signature) A9=VID 200 μA
VLKO Supply Voltage, Erase/Program
Lock-out 2.5 V
Note:
1.Not 100% tested.CharacterisationData available.
Table8. DC Characteristics

(TA=0to70°C, –40to85°Cor –40to 125°C; VCC =5V± 10%)
6/23
M28F101
Read Mode. The Read Modeis the defaultat
powerupor maybe set-upby writing 00htothe
command register. Subsequent read operations
output data fromthe memory. Thememory remainsthe Read Mode untila new commandis writtenthe command register.
Electronic Signature Mode.
In orderto selectthe
correct erase and programming algorithmsforon-
board programming,the manufacturerand device
codes maybe read directly.Itisnot neccessaryto
applya high voltagetoA9 when usingthe com-
mand register. The Electronic Signature Modeis
set-upby writing 90htothe command register. The
following read cycles, with address inputs00000h 00001h, outputthe manufactureror device type
codes. The commandis terminatedby writingan-
other valid commandtothe command register(for
example Reset).
Symbol Alt Parameter Test Condition
M28F101
Unit
-70 -90 -100
VCC=5V±5% VCC=5V±10% VCC=5V±10%
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min Max Min Max Min Max

tWHGL Write Enable Highto
Output EnableLow 66 6 μs
tAVAV tRC Read Cycle Time E= VIL,G=VIL 70 90 100 ns
tAVQV tACC Address Validto
Output Valid E=VIL,G=VIL 70 90 100 ns
tELQX(1) tLZ Chip EnableLowto
Output Transition G=VIL 00 0 ns
tELQV tCE Chip EnableLowto
Output Valid G=VIL 70 90 100 ns
tGLQX(1) tOLZ Output EnableLowto
Output Transition E=VIL 00 0 ns
tGLQV tOE Output EnableLowto
Output Valid E=VIL 40 40 45 ns
tEHQZ(1) Chip Enable Highto
Output Hi-Z G=VIL 0 30 0 45 0 45 ns
tGHQZ(1) tDF Output EnableHighto
Output Hi-Z E=VIL 0 30 0 30 0 30 ns
tAXQX tOH Address Transitionto
Output Transition E=VIL,G=VIL 00 0 ns
Note:
1. Sampledonly,not 100% tested
Table9A. Read Only ModeAC Characteristics

(TA=0to70°C, –40to85°Cor –40to 125°C;0V≤ VPP≤ 6.5V)
7/23
M28F101
Symbol Alt Parameter Test Condition
M28F101
Unit
-120 -150 -200
VCC=5V±10% VCC=5V±10% VCC=5V±10%
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min Max Min Max Min Max

tWHGL Write Enable Highto
Output EnableLow 66 6 μs
tAVAV tRC Read Cycle Time E= VIL,G=VIL 120 150 200 ns
tAVQV tACC Address Validto
Output Valid E=VIL,G=VIL 120 150 200 ns
tELQX(1) tLZ Chip Enable Lowto
Output Transition G=VIL 00 0 ns
tELQV tCE Chip Enable Lowto
Output Valid G=VIL 120 150 200 ns
tGLQX(1) tOLZ Output EnableLowto
Output Transition E=VIL 00 0 ns
tGLQV tOE Output EnableLowto
Output Valid E=VIL 50 55 60 ns
tEHQZ(1) Chip Enable Highto
Output Hi-Z G=VIL 055 0 55 060 ns
tGHQZ(1) tDF Output Enable Highto
Output Hi-Z E=VIL 030 0 35 040 ns
tAXQX tOH Address Transitionto
Output Transition E=VIL,G=VIL 00 0 ns
Note:
1. Sampledonly,not 100% tested
Table9B. Read Only ModeAC Characteristics

((TA=0to70°C, –40to85°Cor –40to 125°C;0V≤ VPP≤ 6.5V)
Erase and Erase Verify Modes.
The memoryis
erasedby first Programmingall bytesto 00h,the
Erase command then erases themto FFh. The
Erase Verify commandis then usedto readthe
memory byte-by-bytefora contentof FFh. The
Erase Modeis set-upby writing 20htothe com-
mand register. The write cycleis then repeatedto
startthe erase operation. Erasure startson the
rising edgeofW duringthis second cycle. Eraseis
followedbyan Erase Verify which readsan ad-
dressed byte.
Erase Verify Modeis set-upby writing A0htothe
command register andatthe same time supplying
the addressofthe bytetobe verified. The rising
edgeofW duringthe set-upofthefirst EraseVerify
Mode stops the Erase operation. The following
read cycleis made withan internally generated
margin voltage applied; readingFFh indicates that
allbitsofthe addressed byteare fully erased. The
whole contentsofthe memoryare verifiedbyre-
peatingthe Erase Verify Operation,first writingthe
set-up code A0h withthe addressofthe bytetobe
verified and then readingthe byte contentsina
second read cycle.
8/23
M28F101
AI00672
tWHGL
tVPHEL
VALID
tELQV tEHQZ
tAVQV
A0-A16
DQ0-DQ7 DATAOUTCOMMAND
VPP
tAXQX
tGHQZ
tGLQV
READREAD SET-UP
tWLWH
tWHDXtDVWH
tGHWL
tELWL tWHEH
Figure6. Read Command Waveforms

AI00671
tAVAV
tAVQV tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATAOUT
A0-A16
DQ0-DQ7
Figure5. Read ModeAC Waveforms

9/23
M28F101
AI00673
tWHGL
tVPHEL
00000h-00001h
tELQV tEHQZ
tAVQV
A0-A16
DQ0-DQ7 DATAOUTCOMMAND
VPP
tAXQX
tGHQZ
tGLQV
READ
MANUFACTURER DEVICE
READ ELECTRONIC
SIGNATURE SET-UP
tWLWH
tWHDXtDVWH
tGHWL
tELWL tWHEH
Figure7. Electronic Signature Command Waveforms
the Erase algorithmflow chart shows, whenthe
data read during Erase Verifyisnot FFh, another
Erase operationis performedand verification con-
tinuesfromthe addressof thelastverifiedbyte. The
commandis terminatedby writing another valid
commandtothe command register (for example
Programor Reset).
Program and Program Verify Modes.
The Pro-
gram Modeisset-upbywriting 40hto thecommand
register. Thisis followedbya second write cycle
which latchesthe address and dataofthe byteto programmed. The rising edgeofW duringthis
secind cycle starts the programming operation.
Programmingis followedbya Program Verifyofthe
data written.
ProgramVerify Modeis set-upby writing C0htothe
command register. The rising edgeofW duringthe
set-upofthe Program Verify Mode stopsthe Pro-
gramming operation. The following read cycle,of
the address already latched during programming, made withan internally generated margin volt-
age applied,reading valid dataindicates thatallbits
have been programmed.
ResetMode.
This commandis usedto safelyabort
Eraseor Program Modes. The Reset Modeis
set-up and performedby writing FFh two timesto
the command register. The command shouldbe
followedby writinga valid commandto the the
command register(for example Read).
READ/WRITE MODES
(cont’d)
10/23
M28F101
Symbol Alt Parameter
M28F101
Unit
-70 -90 -100
VCC=5V±5% VCC=5V±10% VCC=5V±10%
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min Max Min Max Min Max

tVPHEL VPP Highto Chip EnableLow 1 1 1 μs
tVPHWL VPP Highto Write Enable Low 1 1 1 μs
tWHWH3 tWC Write Cycle Time 70 90 100 ns
tAVWL tAS Address Validto Write EnableLow 0 0 0 ns
tAVEL Address Validto Chip EnableLow 0 0 0 ns
tWLAX tAH Write Enable Lowto Address Transition 40 40 40 ns
tELAX Chip EnableLowto Address Transition 50 60 60 ns
tELWL tCS Chip EnableLowto Write Enable Low 10 15 15 ns
tWLEL Write Enable Lowto Chip Enable Low 0 0 0 ns
tGHWL Output Enable Highto Write Enable
Low 000 μs
tGHEL Output Enable Highto Chip Enable Low 0 0 0 μs
tDVWH tDS Input Validto WriteEnable High 30 40 40 ns
tDVEH Input Validto Chip Enable High 30 35 40 ns
tWLWH tWP Write Enable Lowto Write Enable High
(Write Pulse) 35 40 40 ns
tELEH Chip EnableLowto Chip Enable High
(Write Pulse) 35 45 45 ns
tWHDX tDH Write Enable Highto Input Transition 10 10 10 ns
tEHDX Chip Enable Highto Input Transition 10 10 10 ns
tWHWH1 Durationof Program Operation 9.5 9.5 9.5 μs
tEHEH1 Durationof Program Operation 9.5 9.5 9.5 μs
tWHWH2 Durationof Erase Operation 9.5 9.5 9.5 ms
tWHEH tCH Write Enable Highto Chip Enable High 0 0 0 ns
tEHWH Chip Enable Highto WriteEnable High 0 0 0 ns
tWHWL tWPH Write Enable Highto Write Enable Low 20 20 20 ns
tEHEL Chip Enable Highto Chip EnableLow 20 20 20 ns
tWHGL Write Enable Highto Output Enable
Low 666 μs
tEHGL Chip Enable Highto Output Enable Low 6 6 6 μs
tAVQV tACC Addess Validto data Output 70 90 100 ns
tELQX(1) tLZ Chip EnableLowto OutputTransition 0 0 0 ns
tELQV tCE Chip EnableLowto Output Valid 70 90 100 ns
tGLQX(1) tOLZ Output EnableLowto OutputTransition 0 0 0 ns
tGLQV tOE Output EnableLowto Output Valid 40 40 45 ns
tEHQZ(1) Chip Enable Highto Output Hi-Z 30 40 40 ns
tGHQZ(1) tDF Output Enable Highto OutputHi-Z 30 30 30 ns
tAXQX tOH Address Transitionto Output Transition 0 0 0 ns
Note:
1. Sampledonly,not 100% tested.
Table 10A. Read/Write ModeAC Characteristics,W andE Controlled

(TA=0to70°C, –40to85°Cor –40to 125°C)
11/23
M28F101
Symbol Alt Parameter
M28F101
Unit
-120 -150 -200
VCC=5V±10% VCC=5V±10% VCC=5V±10%
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min Max Min Max Min Max

tVPHEL VPP Highto Chip EnableLow 1 1 1 μs
tVPHWL VPP Highto Write Enable Low 1 1 1 μs
tWHWH3 tWC Write Cycle Time 120 150 200 ns
tAVWL tAS Address Validto Write EnableLow 0 0 0 ns
tAVEL Address Validto Chip EnableLow 0 0 0 ns
tWLAX tAH Write Enable Lowto Address Transition 60 60 75 ns
tELAX Chip EnableLowto Address Transition 80 80 80 ns
tELWL tCS Chip EnableLowto Write Enable Low 20 20 20 ns
tWLEL Write Enable Lowto Chip EnableLow 0 0 0 ns
tGHWL Output Enable Highto Write Enable
Low 00 0 μs
tGHEL Output Enable Highto Chip Enable Low 0 0 0 μs
tDVWH tDS Input Validto WriteEnable High 50 50 50 ns
tDVEH Input Validto Chip Enable High 50 50 50 ns
tWLWH tWP Write Enable Lowto Write Enable High
(Write Pulse) 60 60 60 ns
tELEH Chip EnableLowto Chip EnableHigh
(Write Pulse) 70 70 70 ns
tWHDX tDH Write Enable High toInput Transition 10 10 10 ns
tEHDX Chip Enable Highto Input Transition 10 10 10 ns
tWHWH1 Durationof Program Operation 9.5 9.5 9.5 μs
tEHEH1 Durationof Program Operation 9.5 9.5 9.5 μs
tWHWH2 Durationof Erase Operation 9.5 9.5 9.5 ms
tWHEH tCH Write Enable High toChip Enable High 0 0 0 ns
tEHWH Chip Enable Highto Write Enable High 0 0 0 ns
tWHWL tWPH Write Enable High toWrite EnableLow 20 20 20 ns
tEHEL Chip Enable Highto Chip EnableLow 20 20 20 ns
tWHGL Write Enable High toOutput Enable
Low 66 6 μs
tEHGL Chip Enable Highto Output EnableLow 6 6 6 μs
tAVQV tACC Addess Validto data Output 120 150 200 ns
tELQX(1) tLZ Chip EnableLowto Output Transition 0 0 0 ns
tELQV tCE Chip EnableLowto Output Valid 120 150 200 ns
tGLQX(1) tOLZ Output EnableLowto Output Transition 0 0 0 ns
tGLQV tOE Output EnableLowto Output Valid 50 55 60 ns
tEHQZ(1) Chip Enable Highto Output Hi-Z 50 55 60 ns
tGHQZ(1) tDF Output Enable Highto OutputHi-Z 30 35 40 ns
tAXQX tOH Address Transitionto Output Transition 0 0 0 ns
Note:
1. Sampled only,not 100% tested.
Table 10B. Read/Write ModeAC Characteristics,W andE Controlled

(TA=0to70°C, –40to85°Cor –40to 125°C)
12/23
M28F101
ic,good price


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