M28256 Fast Delivery |IC PHOENIX CO.,LIMITED

M28256 ,256 Kbit (32Kb x8) Parallel EEPROM with Software Data ProtectionLogic DiagramADDRESS and DATA LATCHED ON-CHIPSOFTWARE DATA PROTECTIONVCCDESCRIPTIONThe M28256and M2 ..
M28C16 ,16K (2K X 8) PARALLEL EEPROM WITH SOFTWARE DATA PROTECTIONAbsolute Maximum Ratings” maycause permanent damage to the device. These are stress ratings only an ..
M28C16-150N6T ,16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTIONLogic DiagramDESCRIPTIONThe M28C16 is a 2K x 8 low power ParallelEEPROM fabricatedwith SGS-THOMSON ..
M28C16-150WK1TR ,16 Kbit 2K x 8 Parallel EEPROM With Software Data ProtectionAbsolute Maximum Ratings” maycause permanent damage to the device. These are stress ratings only an ..
M28C16A ,16 Kbit (2Kb x8) Parallel EEPROMAbsolute Maximum RatingsSymbol Parameter Value UnitTA Ambient Operating Temperature – 40 to 125 °CT ..
M28C64-30WNS6T ,64 Kbit 8K x 8 Parallel EEPROM With Software Data ProtectionLogic Diagram– 10 Years for M28C64-AVCCTable 1. Signal Names13 8A0-A12 Address InputA0-A12 DQ0-DQ7D ..
M48T86 ,5 VOLT PC REAL TIME CLOCKAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....6DC AND AC ..
M48T86MH1 ,5 VOLT PC REAL TIME CLOCKBlock Diagram . . 6OPERATION . . . . . . 7Signal Description . . . . . . 7V , ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKFEATURES SUMMARY■ DROP-IN REPLACEMENT FOR PC Figure 1. 24-pin PCDIP, CAPHAT™ PackageCOMPUTER CLOCK/ ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKAbsolute Maximum Ratings . . . . . . . 20DC AND AC PARAMETERS . 21Table 10. Operating and ..
M48T86-MH1 ,5 VOLT PC REAL TIME CLOCKLogic Diagram . . 5Table 1. Signal Names . . 5Figure 4. 24-pin DIP Connections . ..
M48T86MH1E ,5 VOLT PC REAL TIME CLOCKM48T865.0V PC Real-Time Clock

M28256
1 Mbit 128K x 8 Parallel EEPROM With Software Data Protection
M28256
256 Kbit (32Kb x8) Parallel EEPROM
with Software Data Protection
PRELIMINARY DATA
January 1999 1/21
AI01885
A0-A14
DQ0-DQ7
VCC
M28256
VSS
Figure1. Logic Diagram
PDIP28 (BS) PLCC32 (KA)
A0-A14 Address Input
DQ0-DQ7 Data Input/ Output Write Enable Chip Enable Output Enable
VCC Supply Voltage
VSS Ground
Table1. SignalNames
FASTACCESSTIME: 90nsat 5V 120nsat 3V
SINGLE SUPPLY VOLTAGE:
–5V± 10%for M28256 2.7Vto 3.6Vfor M28256-xxW
LOW POWER CONSUMPTION
FASTWRITE CYCLE: 64 Bytes Page Write Operation Byteor Page Write Cycle
ENHANCED ENDof WRITE DETECTION: Data Polling ToggleBit
STATUS REGISTER
HIGHRELIABILITYDOUBLE POLYSILICON,
CMOS TECHNOLOGY: Endurance >100,000 Erase/Write Cycles Data Retention>10 Years
JEDEC APPROVED BYTEWIDE PIN OUT
ADDRESS and DATA LATCHED ON-CHIP
SOFTWAREDATA PROTECTION
DESCRIPTION
The M28256and M28256-Ware 32Kx8 low power
ParallelEEPROMfabricatedwithSTMicroelectron-
ics proprietary double polysilicon CMOS technol-
ogy.
TSOP28 (NS) x13.4mm
SO28 (MS)
300 mils
DQ0
A13
A10
DQ7
A11
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6
A12
A14 VCC
AI01886
M282568
Figure 2A. DIP Pin Connections
AI01887
A13
A10
DQ4
DQ0
DQ1DQ2
DQ3
A14
A11
DQ6
DQ7V
M28256
A12
DQ5
Figure 2B. LCC Pin Connections
Warning: NC= Not Connected, DU= Don’t Use.
DQ0
A11
DQ7
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A13
A12
A14
VCC
AI01889
M2825628SS
A10
Figure 2D. TSOPPin Connections
DQ0
DQ1
A10
A13
DQ7
DQ5
VCC
DQ4
A14
AI01888
M282568
DQ2
VSS
DQ6 A11
DQ3
A12
Figure 2C. SO Pin Connections
2/21
M28256
Symbol Parameter Value Unit Ambient Operating Temperature(2) –40to85 °C
TSTG Storage Temperature Range –65to 150 °C
VCC Supply Voltage – 0.3to 6.5 V
VIO Input/Output Voltage –0.3to VCC +0.6 V Input Voltage – 0.3to 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model)(3) 4000 V
Notes:1. Exceptfor therating ”OperatingTemperature Range”, stresses above those listedin theTable ”Absolute Maximum Ratings”may
cause permanent damagetothe device. Theseare stressratings only andoperation ofthedeviceat theseorany other conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied.Exposure toAbsolute Maximum Rating
conditionsfor extendedperiodsmay affectdevice reliability.Refer alsotothe STMicroelectronics SURE Programand other
relevant qualitydocuments. Dependson range.
3.100pF through 1500Ω; MIL-STD-883C, 3015.7
Table2. Absolute Maximum Ratings(1)
AI01697
ADDRESS
LATCHA6-A14
(Page Address)
DECODE
CONTROL LOGIC
256K ARRAY
ADDRESS
LATCHA0-A5 DECODEPP GEN RESET
SENSE AND DATA LATCH
I/O BUFFERS W
PAGE LOAD
TIMERSTATUS
TOGGLEBIT
DATA POLLING
DQ0-DQ7
Figure3. Block Diagram
3/21
M28256
Mode E G W DQ0- DQ7
Read VIL VIL VIH Data Out
Write VIL VIH VIL DataIn
Standby/ Write Inhibit VIH X X Hi-Z
Write Inhibit X X VIH Data Outor Hi-Z
Write Inhibit X VIL X Data Outor Hi-Z
Output Disable X VIH X Hi-Z
Notes:1.X=VIHorVIL.
Table3. Operating Modes(1)
The devices offer fast access time with low power
dissipationand requiresa 5Vor 3V power supply.
The circuit has been designedto offera flexible
microcontroller interface featuring both hardware
and software handshaking with Data Polling and
Toggle Bit and accesstoa status register. The
devices supporta64 byte page write operation.A
Software Data Protection (SDP)is also possible
using the standard JEDEC algorithm.
PIN DESCRIPTION
Addresses (A0-A14). The address inputs select 8-bit memory location duringa reador write
operation.
Chip Enable (E). The chip enable input mustbe
lowto enableall read/writeoperations.When Chip
Enableis high, power consumptionis reduced.
Output Enable (G). The Output Enableinput con-
trols the data output buffers andis usedto initiate
read operations.
DataIn/ Out (DQ0-DQ7). Datais writtentoor read
from the memory through the I/O pins.
Write Enable (W). TheWrite Enableinput controls
the writingof datato the memory.
OPERATIONS
Write Protection orderto prevent data corruption and inadvertent
write operations;an internal VCC comparatorinhib-
its Write operationsif VCCis below VWI (see Table andTable 9).Accessto thememoryinwritemode allowed aftera power-upas specifiedin Table7
and Table9.
Read
The deviceis accessed likea static RAM. WhenE
andG are low withW high, the data addressedis
presentedon the I/O pins. The I/O pins are high
impedance when eitherGorEis high.
Write
Write operations are initiated when bothW andE
are low andGis high.The device supports bothE
and W controlled write cycles. The Addressis
latchedby the falling edge ofEorW which ever
occurs last and the Dataon the rising edgeofEor which ever occurs first. Once initiated the write
operationis internally timed until completion and
the statusof the Data Polling and the Toggle Bit
functionson DQ7 and DQ6is controlled accord-
ingly.
Page Write
Page write allowsupto 64 bytes within the same
pagetobe consecutivelylatched into the memory
priorto initiatinga programming cycle. All bytes
must be locatedina single page address, thatis
A14-A6 mustbe the sameforall bytes;if not,the
Page Write instructionis not executed. The page
writecanbe initiatedby any byte write operation. page writeis composedof successive Write
instructions which haveto be sequenced witha
specific periodof time between two consecutive
Write instructions, periodof time which hasto be
smaller than the tWHWH value (see Table12 and
Table 13). this periodof time exceedsthe tWHWH value, the
internal programmingcyclewill start. Once initiated
the write operationis internally timed until comple-
tion and the statusof the Data Polling and the
ToggleBit functionson DQ7and DQ6is controlled
accordingly.
DESCRIPTION (Cont’d)
4/21
M28256
Status Register
The devicesprovide severalWrite operationstatus
flags that canbe usedto minimize the application
write time. These signals are availableon the I/O
port bits during programming cycle only.
Data Polling bit (DQ7). During the internal write
cycle, any attemptto read the last bytewritten will
produceon DQ7 the complementary valueof the
previously latched bit. Once the write cycleis fin-
ished the true logic value appearson DQ7in the
read cycle.
Toggle bit (DQ6). The devices offer another way
for determining when the internal write cycleis
completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0”to ”1” and ”1”to ”0” (the
first read valueis ”0”)on subsequent attemptsto
read any byteof the memory. When the internal
cycleis completed the toggling will stop and the
data readon DQ7-DQ0is the addressed memory
byte. The deviceis nowaccessiblefora newRead Writeoperation.
PageLoadTimerStatusbit(DQ5). Duringa Page
Write instruction, the devices expectto receive the
streamof data witha minimum periodof time
between each data byte. This periodof time
(tWHWH)is definedby the on-chip Page Load timer
which running/overflowstatusis availableon DQ5.
DQ5 Low indicates that the timeris running, DQ5
High indicates the time-out after which the internal
write cycle will start.
Software Data Protection
The devices offera software controlled write pro-
tectionfacility thatallows theuserto inhibitall write
modesto the device. This canbe usefulin protect-
ing the memory from inadvertentwrite cycles that
may occur dueto uncontrolledbus conditions.
Thedevicesareshippedas standardin the”unpro-
tected” state meaning that the memory contents
canbe changedas requiredby the user.After the
Software Data Protection enable algorithmisis-
sued, the device enters the ”Protect Mode”of
operation whereno further write commands have
any effecton the memorycontents.
The devices remainin this mode untila valid
Software Data Protection(SDP) disable sequence received whereby the device revertstoits ”un-
protected”state. The Software Data Protectionis
fully non-volatile andis not changed by power
on/off sequences.To enable the Software Data
Protection (SDP) the device requires the userto
write (witha Page Write addressing three specific
databytes tothree specific memorylocations,each
locationina different page)as per Figure6. Simi-
larlyto disable the Software Data Protection the
user hasto write specific data bytes intosix differ-
ent locationsas per Figure5 (witha Page Write
adressing different bytesin differentpages).
Thiscomplexseriesensuresthatthe userwill never
enableor disable the Software Data Protection
accidentally. write into the devices when SDPis set, the
sequence shownin Figure6 mustbe used. This
sequence providesan unlock keyto enable the
write action, andat the same time SDP continuesbe set.
Anextensionto thisis where SDPis requiredtobe
set, and dataistobe written.
Using the same sequenceas above, the data can written and SDPis setat the same time, giving
both these actionsin the same Write cycle (tWC).
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 TB PLTS X X X X X = DataPolling = ToggleBit
PLTS= Page Load TimerStatus
Figure4. Status Bit Assignment
5/21
M28256
AI01698B
WRITE AAhin
Address 5555h
WRITE 55hin
Address 2AAAh
WRITE A0hin
Address 5555h
SDP isset
WRITE AAhin
Address 5555h
WRITE 55hin
Address 2AAAh
WRITE A0hin
Address 5555h
WRITE Datato Writtenin
any Address
SDP ENABLE ALGORITHM
Page
Write
Instruction
Page
Write
Instruction
WRITE enabled
SDP
Set
SDP
notSet
Write Memory
Write Data
SDPSet
after tWC
Figure5. Software Data Protection Enable Algorithm and Memory Write
AI01699B
WRITE AAhin
Address 5555h
WRITE 55hin
Address 2AAAh
WRITE 80hin
Address 5555h
Unprotected State
after
tWC (Write Cycletime)
WRITE AAhin
Address 5555h
WRITE 55hin
Address 2AAAh
WRITE 20hin
Address 5555h
Page
Write
Instruction
Figure6. Software Data Protection Disable Algorithm
6/21
M28256
Input Rise and FallTimes ≤ 20ns
Input Pulse Voltages (M28256) 0.4Vto 2.4V
Input Pulse Voltages (M28256-W) 0Vto VCC –0.3V
Input and Output Timing Ref. Voltages (M28256) 0.8Vto 2.0V
Input and Output Timing Ref. Voltages (M28256-W) 0.5 VCC
Table4. AC Measurement Conditions
AI02101B
4.5Vto 5.5V Operating Voltage
2.7Vto 3.6V Operating Voltage
VCC– 0.3V
0.5 VCC
2.4V
0.4V
2.0V
0.8V
Figure7. AC TestingInput Output Waveforms
AI02102B
OUT= 100pF includes JIGcapacitance
IOL
DEVICE
UNDER
TEST
IOH
Figure8. AC Testing Equivalent Load Circuit
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6 pF
COUT Output Capacitance VOUT =0V 12 pF
Note:1. Sampled only,not 100% tested.
Table5. Capacitance(1) (TA =25 °C,f=1 MHz)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤ VIN≤ VCC 10 μA
ILO Output Leakage Current 0V≤ VIN≤ VCC 10 μA
ICC(1) Supply Current (TTL inputs) E= VIL,G=VIL,f= 5MHz 30 mA
Supply Current (CMOS inputs) E= VIL,G=VIL,f= 5MHz 25 mA
ICC1(1) Supply Current (Standby) TTL E= VIH 1mA
ICC2(1) Supply Current (Standby) CMOS E> VCC –0.3V 100 μA
VIL Input Low Voltage – 0.3 0.8 V
VIH Input High Voltage 2 VCC+0.5 V
VOL Output Low Voltage IOL= 2.1 mA 0.4 V
VOH Output High Voltage IOH= –400μA 2.4
Note:1.All I/O’sopen circuit.
Table6. Read Mode DC Characteristicsfor M28256
(TA=0to 70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
7/21
M28256
Symbol Parameter Min Max Unit
tPUR Time Delayto Read Operation 1 μs
tPUW Time Delayto Write Operation (once VCC≥ VWI)5 ms
VWI Write Inhibit Threshold 3.0 4.2 V
Note:1. Sampled only,not 100% tested.
Table7. PowerUp Timingfor M28256(1)
(TA=0to 70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤ VIN≤ VCC 10 μA
ILO Output Leakage Current 0V≤ VIN≤ VCC 10 μA
ICC(1) Supply Current (CMOS inputs) E=VIL,G= VIL,f=5 MHz, VCC= 3.3V 15 mA
E=VIL,G= VIL,f=5 MHz, VCC= 3.6V 15 mA
ICC2(1) Supply Current (Standby) CMOS E> VCC –0.3V 20 μA
VIL Input Low Voltage –0.3 0.6 V
VIH Input High Voltage 2 VCC+0.5 V
VOL Output Low Voltage IOL= 2.1 mA 0.2 VCC V
VOH Output High Voltage IOH= –400μA 0.8 VCC V
Note:1.All I/O’sopen circuit.
Table8. Read Mode DC Characteristicsfor M28256-W
(TA=0to 70°Cor –40to 85°C; VCC= 2.7Vto 3.6V)
Symbol Parameter Min Max Unit
tPUR Time Delayto Read Operation 1 μs
tPUW Time Delayto Write Operation (once VCC≥ VWI)10 ms
VWI Write Inhibit Threshold 1.5 2.5 V
Note:1. Sampled only,not 100% tested.
Table9. PowerUp Timingfor M28256-W(1)
(TA=0to 70°Cor –40to 85°C; VCC= 2.7Vto 3.6V)
8/21
M28256
Symbol Alt Parameter Test Condition
M28256
Unit-90 -12 -15 -20
min max min max min max min max
tAVQV tACC Address Validto
Output Valid E= VIL,G=VIL 90 120 150 200 ns
tELQV tCE Chip Enable Lowto
Output Valid G=VIL 90 120 150 200 ns
tGLQV tOE Output EnableLow Output Valid E=VIL 40 45 50 50 ns
tEHQZ(1) tDF Chip Enable Highto
Output Hi-Z G=VIL 0 40 0 45 0 50 0 50 ns
tGHQZ(1) tDF Output EnableHigh Output Hi-Z E=VIL 0 40 0 45 0 50 0 50 ns
tAXQX tOH Address Transition Output Transition E=VIL,G=VIL 0000 ns
Note:1. OutputHi-Zis definedasthe pointat which dataisno longerdriven.
Table 10. ReadMode AC Characteristics
(TA=0to 70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
Symbol Alt Parameter Test Condition
M28256-W
Unit-12 -15 -20 -25
min max min max min max min max
tAVQV tACC Address Validto
Output Valid E= VIL,G=VIL 120 150 200 250 ns
tELQV tCE Chip Enable Lowto
Output Valid G=VIL 120 150 200 250 ns
tGLQV tOE Output EnableLow Output Valid E=VIL 45 70 80 100 ns
tEHQZ(1) tDF Chip Enable Highto
Output Hi-Z G=VIL 0 45 0 50 0 55 0 60 ns
tGHQZ(1) tDF Output EnableHigh Output Hi-Z E=VIL 0 45 0 50 0 55 0 60 ns
tAXQX tOH Address Transition Output Transition E=VIL,G=VIL 0000 ns
Note:1. OutputHi-Zis definedasthe pointat which dataisno longerdriven.
Table 11. Read Mode AC Characteristics
(TA=0to 70°Cor –40to 85°C; VCC= 2.7Vto 3.6V)
9/21
M28256
Symbol Alt Parameter TestCondition M28256 Unit
Min Max
tAVWL tAS Address Validto WriteEnable Low E= VIL,G= VIH 0ns
tAVEL tAS Address Validto Chip Enable Low G= VIH,W=VIL 0ns
tELWL tCES Chip Enable Lowto Write Enable Low G=VIH 0ns
tGHWL tOES Output Enable Highto Write Enable
Low E=VIL 0ns
tGHEL tOES Output Enable Highto Chip Enable Low W=VIL 0ns
tWLEL tWES Write Enable Lowto Chip Enable Low G=VIH 0ns
tWLAX tAH Write Enable Lowto Address Transition 50 ns
tELAX tAH Chip Enable Lowto Address Transition 50 ns
tWLDV tDV Write Enable Lowto Input Valid E= VIL,G= VIH 1 μs
tELDV tDV Chip Enable Lowto Input Valid G= VIH,W=VIL 1 μs
tELEH tWP Chip Enable Lowto Chip Enable High 50 ns
tWHEH tCEH Write Enable Highto Chip Enable High 0 ns
tWHGL tOEH Write Enable Highto Output Enable
Low 0ns
tEHGL tOEH Chip Enable Highto Output Enable Low 0 ns
tEHWH tWEH Chip Enable Highto Write Enable High 0 ns
tWHDX tDH Write Enable Highto Input Transition 0 ns
tEHDX tDH Chip Enable Highto Input Transition 0 ns
tWHWL tWPH Write Enable Highto Write Enable Low 100 ns
tWLWH tWP Write Enable Lowto Write Enable High 50 ns
tWHWH tBLC Byte Load Repeat Cycle Time 0.15 150 μs
tWHRH tWC Write Cycle Time 5 ms
tEL,tWL EorW Input Filter Pulse Width Note1 10 ns
tDVWH tDS Data Validbefore WriteEnable High 50 ns
tDVEH tDS Data Validbefore Chip Enable High 50 ns
Note:1. Characterized onlybutnot testedin production.
Table 12. Write Mode AC Characteristics
(TA=0to 70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
10/21
M28256
Symbol Alt Parameter TestCondition M28256-W Unit
Min Max
tAVWL tAS Address Validto WriteEnable Low E= VIL,G= VIH 0ns
tAVEL tAS Address Validto Chip Enable Low G= VIH,W=VIL 0ns
tELWL tCES Chip Enable Lowto Write Enable Low G=VIH 0ns
tGHWL tOES Output Enable Highto Write Enable
Low E=VIL 0ns
tGHEL tOES Output Enable Highto Chip Enable Low W=VIL 0ns
tWLEL tWES Write Enable Lowto Chip Enable Low G=VIH 0ns
tWLAX tAH Write Enable Lowto Address Transition 70 ns
tELAX tAH Chip Enable Lowto Address Transition 70 ns
tWLDV tDV Write Enable Lowto Input Valid E= VIL,G= VIH 1 μs
tELDV tDV Chip Enable Lowto Input Valid G= VIH,W=VIL 1 μs
tELEH tWP Chip Enable Lowto Chip Enable High 100 ns
tWHEH tCEH Write Enable Highto Chip Enable High 0 ns
tWHGL tOEH Write Enable Highto Output Enable
Low 0ns
tEHGL tOEH Chip Enable Highto Output Enable Low 0 ns
tEHWH tWEH Chip Enable Highto Write Enable High 0 ns
tWHDX tDH Write Enable Highto Input Transition 0 ns
tEHDX tDH Chip Enable Highto Input Transition 0 ns
tWHWL tWPH Write Enable Highto Write Enable Low 100 ns
tWLWH tWP Write Enable Lowto Write Enable High 100 ns
tWHWH tBLC Byte Load Repeat Cycle Time 0.2 150 μs
tWHRH tWC Write Cycle Time 5 ms
tEL,tWL EorW Input Filter Pulse Width Note1 10 ns
tDVWH tDS Data Validbefore WriteEnable High 50 ns
tDVEH tDS Data Validbefore Chip Enable High 50 ns
Note:1. Characterized onlybutnot testedin production.
Table 13. Write Mode AC Characteristics
(TA=0to 70°Cor –40to 85°C; VCC= 2.7Vto 3.6V)
11/21
M28256

Partno	Mfg	Dc	Qty	Available	Descript
M28256	ST	N/a	1562	avai	256 Kbit (32Kb x8) Parallel EEPROM with Software Data Protection