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M27V160-100K1 |M27V160100K1N/a43avai16 MBIT (2MB X8 OR 1MB X16) LOW VOLTAGE UV EPROM AND OTP EPROM
M27V160-100XB1 |M27V160100XB1STN/a710avai16 MBIT (2MB X8 OR 1MB X16) LOW VOLTAGE UV EPROM AND OTP EPROM


M27V160-100XB1 ,16 MBIT (2MB X8 OR 1MB X16) LOW VOLTAGE UV EPROM AND OTP EPROMapplications where the content is programmed Gonly one time and erasure is not required, theM27V160 ..
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M27V160-100K1-M27V160-100XB1
16 MBIT (2MB X8 OR 1MB X16) LOW VOLTAGE UV EPROM AND OTP EPROM
1/17March 2002
M27V160
Mbit (2Mb x8 or 1Mb x16)
Low Voltage UV EPROM and OTP EPROM3Vto 3.6V LOW VOLTAGEin READ
OPERATION ACCESS TIME: 100ns BYTE-WIDEor WORD-WIDE
CONFIGURABLE16 Mbit MASK ROM REPLACEMENT LOW POWER CONSUMPTION Active Current 30mAat 8MHz Standby Current 60μA PROGRAMMING VOLTAGE: 12.5V± 0.25V PROGRAMMING TIME: 50μs/word ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: B1h
DESCRIPTION

The M27V160isalow voltage16 Mbit EPROMof-
feredinthe two rangesUV (ultra violet erase) and
OTP (one time programmable).Itis ideally suited
for microprocessor systems requiring large dataor
program storage.Itis organisedas either2 Mbit
wordsof8bitor1 Mbit wordsof16bit. The pin-out compatible witha16 Mbit Mask ROM.
The M27V160 operatesinthe read mode witha
supply voltageaslowas3V. The decreaseinop-
erating power allows eithera reductionofthe sizethe batteryoran increaseinthe time between
battery recharges.
The FDIP42W (window ceramic frit-seal package)
hasa transparentlid which allowsthe usertoex-
posethe chipto ultraviolet lightto erasethebit pat-
tern.A new pattern can thenbe written rapidlyto
the deviceby followingthe programming proce-
dure.
For applications wherethe contentis programmed
only one time and erasureis not required, the
M27V160is offeredin PDIP42, SDIP42, PLCC44
and SO44 packages.
M27V160
2/17
Table1. Signal Names
3/17
M27V160
Table2. Absolute Maximum Ratings(1)

Note:1. Exceptforthe rating "Operating Temperature Range", stresses above those listedinthe Table "Absolute Maximum Ratings"may
cause permanent damagetothe device. Theseare stress ratingsonlyand operationofthe deviceat theseorany otherconditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periodsmay affect device reliability.Referalsotothe STMicroelectronics SUREProgramand otherrelevantqual-
ity documents. MinimumDC voltageon Inputor Outputis –0.5Vwith possible undershootto –2.0Vfora periodlessthan 20ns. MaximumDC
voltageon OutputisVCC +0.5V withpossibleovershoot toVCC+2Vfora periodlessthan 20ns. Dependson range.
Table3. Operating Modes

Note:X= VIHor VIL,VID=12V ±0.5V.
Table4. Electronic Signature
M27V160
4/17
DEVICE OPERATION

The operating modesofthe M27V160are listedin
the Operating Modes Table.A single power supply requiredinthe read mode.All inputsare TTL
compatible exceptfor VPP and 12VonA9forthe
Electronic Signature.
Read Mode

The M27V160 has two organisations, Word-wide
and Byte-wide. The organisationis selectedbythe
signal levelonthe BYTEVPP pin. When BYTEVPPat VIHthe Word-wide organisationis selected
andthe Q15A–1pinis usedfor Q15 Data Output.
Whenthe BYTEVPPpinisatVILthe Byte-wideor-
ganisationis selected andthe Q15A–1pinis used
forthe Address Input A–1. Whenthe memoryis
logically regardedas16bit wide,but readinthe
Byte-wide organisation, then with A–1atVILthe
lower8bitsofthe16bit dataare selected and with
A–1atVIHthe upper8 bitsofthe16bit dataare
selected.
The M27V160 has two control functions, bothof
which mustbe logically activein orderto obtain
dataatthe outputs.In additionthe Word-wideor
Byte- wide organisation mustbe selected.
Chip Enable(E)isthe power controland shouldbe
usedfor device selection. Output Enable (G)isthe
output control and shouldbe usedto gate datato
the output pins independentof device selection.
Assuming thatthe addresses are stable,thead-
dress access time (tAVQV)is equalto the delay
fromEto output (tELQV). Datais availableatthe
output aftera delayof tGLQV fromthe falling edgeG, assuming thatE has beenlow andthead-
dresses have been stableforat least tAVQV-tGLQV.
Table5.AC Measurement Conditions
Table6. Capacitance(1)
(TA=25 °C,f=1 MHz)
Note:1. Sampledonly,not 100% tested.
5/17
M27V160
Table7. Read ModeDC Characteristics(1)

(TA=0to 70°Cor –40to 85°C; VCC =3.3V± 10%; VPP =VCC)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. MaximumDC voltageon OutputisVCC +0.5V.
Standby Mode

The M27V160hasa standby mode which reduces
the active current from 20mAto 20μA withlow volt-
age operation VCC≤ 3.6V, see Read ModeDC
Characteristics tablefor details.The M27V160is
placedinthe standby modeby applyinga CMOS
high signalto theE input. Wheninthe standby
mode,the outputsareina high impedance state,
independentoftheG input.
Two Line Output Control

Because EPROMs are usually usedin larger
memory arrays,this product featuresa2line con-
trol function which accommodatesthe useof mul-
tiple memory connection. The two line control
function allows:the lowest possible memory power dissipation, complete assurance that output bus contention
willnot occur.
For the most efficient useof these two control
lines,E shouldbe decoded and usedasthe prima- device selecting function, whileG shouldbe
madea common connectiontoall devicesinthe
array and connectedto the READ line fromthe
system control bus. This ensures thatall deselect- memory devicesarein theirlow power standby
mode and that the output pins are only active
when datais required froma particular memory
device.
System Considerations

The power switching characteristicsof Advanced
CMOS EPROMs require careful decouplingofthe
suppliesto the devices. The supply current ICC
has three segmentsof importancetothe system
designer:the standby current,the active current
andthe transient peaks thatare producedbythe
falling and rising edgesofE. The magnitudeofthe
transient current peaksis dependentontheca-
pacitive and inductive loadingofthe device out-
puts. The associated transient voltage peaks can suppressedby complying withthetwoline out-
put control andby properly selected decoupling
capacitors.Itis recommended thata 0.1μF ceram- capacitoris usedon every device between VCC
and VSS. This shouldbea high frequency typeof
low inherent inductance and shouldbe placedas
closeas possibleto the device.In addition,a
4.7μF electrolytic capacitor shouldbe used be-
tween VCC and VSSfor every eight devices. This
capacitor shouldbe mounted nearthe power sup-
ply connection point. The purposeofthis capacitorto overcomethe voltage drop causedbythein-
ductive effectsof PCB traces.
M27V160
6/17
Table8. Read ModeAC Characteristics(1)

(TA=0to 70°Cor –40to 85°C; VCC =3.3V± 10%; VPP =VCC)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP Sampledonly,not 100% tested. Speed obtainedwithHigh Speed measurement conditions.
7/17
M27V160
M27V160
8/17
Table9. Programming ModeDC Characteristics(1)

(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.5V± 0.25V)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP.
Table10. Programming ModeAC Characteristics(1)

(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.5V± 0.25V)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. Sampledonly,not 100% tested.
Programming

The M27V160 has been designedtobe fully com-
patible with the M27C160. Asa result the
M27V160 canbe programmedasthe M27C160the same programming equipments applying
12.75Von VPP and 6.25Von VCCbythe useofthe
same PRESTOIII algorithm. When delivered (and
after each erasureforUV EPROM),all bitsofthe
M27V160areinthe'1' state. Datais introducedby
selectively programming'0'stothe desiredbitlo-
cations. Although only '0'swillbe programmed,
both'1's and'0's canbe presentinthe data word.
The only wayto changea'0'toa'1'isbydie expo-
sureto ultraviolet light (UV EPROM). The
M27V160isinthe programming mode when Vpp
inputisat 12.5V,GisatVIH andEis pulsedtoVIL.
The datatobe programmedis appliedto16bitsin
paralleltothe data output pins. The levels required
forthe address and data inputsare TTL. VCCis
specifiedtobe6.25V± 0.25V.
9/17
M27V160
PRESTOIII Programming Algorithm

The PRESTOIII Programming Algorithm allows
the whole arraytobe programed witha guaran-
teed marginina typical timeof 52.5 seconds. Pro-
gramming with PRESTOIII consistsof applyinga
sequenceof 50μs program pulsesto each word
untila correct verify occurs (see Figure9).
During programing and verify operationa MAR-
GIN MODE circuitis automatically activatedto
guaranteethat eachcellis programed with enough
margin.No overprogram pulseis applied sincethe
verifyin MARGIN MODEat VCC much higher than
3.6V providesthe necessary marginto each pro-
grammed cell.
Program Inhibit

Programmingof multiple M27V160sin parallel
with different datais also easily accomplished.Ex-
ceptforE,alllike inputs includingGofthe parallel
M27V160 maybe common.A TTLlow level pulse
appliedtoa M27V160'sE input and VPPat 12.5V,
will program that M27V160.A high levelE inputin-
hibits the other M27V160s from being pro-
grammed.
Program Verify
verify (read) shouldbe performedonthe pro-
grammedbitsto determine that they were correct- programmed. The verifyis accomplished withE VIH andGat VIL,VPPat 12.5V and VCCat
6.25V.
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