LPC3220FET296 ,ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controllerFeatures and benefits ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz. Vector Flo ..
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LPC3220FET296-LPC3230FET296-LPC3250FET296
ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller
1. General descriptionThe LPC3220/30/40/50 embedded microcontrollers were designed for low power, high
performance applications. NXP achieved their performance goals using a 90 nanometer
process to implement an ARM926EJ-S CPU core with a vector floating point co-processor
and a large set of standard peripherals including USB On-The-Go. The
LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz.
The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture,
5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides
the virtual memory capabilities needed to support the multi-programming demands of
modern operating systems. The ARM926EJ-S also has a hardware based set of DSP
instruction extensions, which includes single cycle MAC operations, and hardware based
native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB
instruction cache and a 32 kB data cache.
For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced
technology development to optimize intrinsic power and uses software controlled
architectural enhancements to optimize application based power management.
The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash
interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an
external bus interface that supports SDR and DDR SDRAM as well as static devices. In
addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs,
two I2 C-bus interfaces, two SPI/SSP ports, two I2 S-bus interfaces, two single output
PWMs, a motor control PWM, six general purpose timers with capture inputs and compare
outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC)
with a touch screen sense option.
2. Features and benefits ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz. Vector Floating Point (VFP) coprocessor. 32 kB instruction cache and 32 kB data cache. Up to 256 kB of Internal SRAM (IRAM). Selectable boot-up from various external devices: NAND flash, SPI memory, USB,
UART, or static memory. Multi-layer AHB system that provides a separate bus for each AHB master, including
both an instruction and data bus for the CPU, two data busses for the DMA controller,
and another bus for the USB controller, one for the LCD, and a final one for the
Ethernet MAC. There are no arbitration delays in the system unless two masters
attempt to access the same slave at the same time.
LPC3220/30/40/50
16/32-bit ARM microcontrollers; hardware floating-point
coprocessor, USB On-The-Go, and EMC memory interface
Rev. 2 — 20 October 2011 Product data sheet
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers External memory controller for DDR and SDR SDRAM as well as for static devices. Two NAND flash controllers: One for single-level NAND flash devices and the other for
multi-level NAND flash devices. Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting
74 interrupt sources. Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be
used with the SD card port, the high-speed UARTs, I2 S-bus interfaces, and SPI
interfaces, as well as memory-to-memory transfers. Serial interfaces: 10/100 Ethernet MAC with dedicated DMA Controller. USB interface supporting either device, host (OHCI compliant), or On-The-Go
(OTG) with an integral DMA controller and dedicated PLL to generate the required
48 MHz USB clock. Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One
of the standard UARTs supports IrDA. Three additional high-speed UARTs intended for on-board communications that
support baud rates up to 921 600 when using a 13 MHz main oscillator. All
high-speed UARTs provide 64 byte FIFOs. Two SPI controllers. Two SSP controllers. Two I2 C-bus interfaces with standard open-drain pins. The I2 C-bus interfaces
support single master, slave, and multi-master I2 C-bus configurations. Two I2 S-bus interfaces, each with separate input and output channels. Each
channel can be operated independently on three pins, or both input and output
channels can be used with only four pins and a shared clock. Additional peripherals: LCD controller supporting both STN and TFT panels, with dedicated DMA
controller. Programmable display resolution up to 1024 768. Secure Digital (SD) memory card interface, which conforms to the SD Memory
Card Specification Version 1.01. General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24
GP output pins, and 51 GP I/O pins. 10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from
three pins. Optionally, the ADC can operate as a touch screen controller. Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator.
NXP implemented the RTC in an independent on-chip power domain so it can
remain active while the rest of the chip is not powered. The RTC also includes a
32-byte scratch pad memory. 32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer
includes one external capture input pin and a capture connection to the RTC clock.
Interrupts may be generated using three match registers. Six enhanced timer/counters which are architecturally identical except for the
peripheral base address. Two capture inputs and two match outputs are pinned out
to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all
four match outputs, timer 4 has one match output, and timer 5 has no inputs or
outputs. 32-bit millisecond timer driven from the RTC clock. This timer can generate
interrupts using two match registers.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers WatchDog timer clocked by the peripheral clock. Two single-output PWM blocks. Motor control PWM. Keyboard scanner function allows automatic scanning of an up to 8 8 key matrix. Up to 18 external interrupts. Standard ARM test/debug interface for compatibility with existing tools. Emulation Trace Buffer (ETB) with 2048 24 bit RAM allows trace via JTAG. Stop mode saves power while allowing many peripheral functions to restart CPU
activity. On-chip crystal oscillator. An on-chip PLL allows CPU operation up to the maximum CPU rate without the
requirement for a high frequency crystal. Another PLL allows operation from the kHz RTC clock rather than the external crystal. Boundary scan for simplified board testing. User-accessible unique serial ID number for each chip. TFBGA296 package with a 15 mm 15 mm 0.7 mm body.
3. Applications Consumer Medical Industrial Network control
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
4. Ordering information[1] F = 40 C to +85 C temperature range. Note that Revision “A” parts with and without the /01 suffix are identical. For example,
LPC3220FET296 Revision “A” is identical to LPC3220FET296/01 Revision “A”.
[2] Available starting with Revision “A”.
4.1 Ordering options
Table 1. Ordering informationLPC3220FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
LPC3230FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
LPC3240FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
LPC3250FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
Table 2. Part optionsLPC3220FET296/01 128 0 0 40 to +85 TFBGA296
LPC3230FET296/01 256 0 1 40 to +85 TFBGA296
LPC3240FET296/01 256 1 0 40 to +85 TFBGA296
LPC3250FET296/01 256 1 1 40 to +85 TFBGA296
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
5. Block diagramNXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
6. Pinning information
6.1 Pinning
Table 3. Pin allocation table (TFBGA296)
Row A I2C2_SCL I2S1TX_CLK/MAT3[0] A5 I2C1_SCL A6 MS_BS/MAT2[1] MS_DIO1/MAT0[1] A8 MS_DIO0/MAT0[0] A9 SPI2_DATIO/MOSI1/LCDVD[20][1]
A10 SPI2_DATIN/MISO1/
LCDVD[21][1]
A11 GPIO_1 A12 GPIO_0
A13 GPO_21/U4_TX/LCDVD[3][1] A14 GPO_15/MCOA1/LCDFP[1] A15 GPO_7/LCDVD[2][1]
A16 GPO_6/LCDVD[18][1]
Row B GPO_20 B3 GPO_5 I2S1TX_WS/CAP3[0] B5 P0[0]/I2S1RX_CLK B6 I2C1_SDA MS_SCLK/MAT2[0] B8 MS_DIO2/MAT0[2] B9 SPI1_DATIO/MOSI0/MCI2
B10 SPI2_CLK/SCK1/LCDVD[23][1] B11 GPIO_4/SSEL1/LCDVD[22][1] B12 GPO_12/MCOA2/LCDLE[1]
B13 GPO_13/MCOB1/LCDDCLK[1] B14 GPO_2/MAT1[0]/LCDVD[0][1] B15 GPI_19/U4_RX
B16 GPI_8/KEY_COL6/
SPI2_BUSY/ENET_RX_DV[2] B17 n.c.
Row C C2 GPO_19 C3 GPO_0/TST_CLK1 C5 USB_SE0_VM/U5_TX C6 TST_CLK2 C8 MS_DIO3/MAT0[3] C9 SPI1_CLK/SCK0
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollersC10 SPI1_DATIN/MISO0/GPI_25/
MCI1
C11 GPIO_3/KEY_ROW7/
ENET_MDIO[2] C12 GPO_9/LCDVD[9][1]
C13 GPO_8/LCDVD[8][1] C14 GPI_2/CAP2[0]/
ENET_RXD3[2] C15 GPI_1/SERVICE
C16 GPI_0/I2S1RX_SDA C17 KEY_ROW4/ENET_TXD0[2] C18 KEY_ROW5/ENET_TXD1[2]
Row D FLASH_RDY D2 FLASH_ALE D3 GPO_14 GPO_1 D5 USB_DAT_VP/U5_RX D6 USB_OE_TP P0[1]/I2S1RX_WS D8 GPO_4 D9 GPIO_2/KEY_ROW6/ENET_MDC[2]
D10 GPO_16/MCOB0/LCDENAB[1]/
LCDM[1] D11 GPO_18/MCOA0/LCDLP[1] D12 GPO_3/LCDVD[1][1]
D13 GPI_7/CAP4[0]/MCABORT D14 PWM_OUT1/LCDVD[16][1] D15 PWM_OUT2/INTSTAT/LCDVD[19][1]
D16 KEY_ROW3/ENET_TX_EN[2] D17 KEY_COL2/ENET_RX_ER[2] D18 KEY_COL3/ENET_CRS[2]
Row E FLASH_IO[3] E2 FLASH_IO[7] E3 FLASH_CE I2C2_SDA E5 USB_I2C_SCL E6 USB_I2C_SDA I2S1TX_SDA/MAT3[1] E8 GPO_11 E9 GPIO_5/SSEL0/MCI0
E10 GPO_22/U7_HRTS/
LCDVD[14][1] E11 GPO_10/MCOB2/LCDPWR[1] E12 GPI_9/KEY_COL7/ENET_COL[2]
E13 GPI_4/SPI1_BUSY E14 KEY_ROW1/ENET_TXD2[2] E15 KEY_ROW0/ENET_TX_ER[2]
E16 KEY_COL1/ENET_RX_CLK[2]/
ENET_REF_CLK[2] E17 U7_RX/CAP0[0]/
LCDVD[10][1] /GPI_23
E18 U7_TX/MAT1[1]/LCDVD[11][1]
Row F FLASH_IO[2] F2 FLASH_WR F3 FLASH_CLE GPI_3 F5 VSS_IOC F6 VSS_IOB VDD_IOC F8 VDD_IOB F9 VDD_IOD
F10 VSS_IOD F11 VSS_IOD F12 VSS_IOD
F13 VDD_IOD F14 KEY_ROW2/ENET_TXD3[2] F15 KEY_COL0/ENET_TX_CLK[2]
F16 KEY_COL5/ENET_RXD1[2] F17 U6_IRRX/GPI_21 F18 U5_RX/GPI_20
Row G EMC_DYCS1 G2 FLASH_IO[5] G3 FLASH_IO[6] RESOUT G5 VSS_IOC G6 VDD_IOC VDD_CORE G8 VSS_CORE G9 VDD_CORE
G10 VSS_CORE G11 VDD_CORE G12 VSS_CORE
G13 U7_HCTS/CAP0[1]/
LCDCLKIN[1] /GPI_22
G14 DBGEN G15 KEY_COL4/ENET_RXD0[2]
G16 U6_IRTX G17 SYSCLKEN/LCDVD[15][1] G18 JTAG_TMS
Row H EMC_OE H2 FLASH_IO[0] H3 FLASH_IO[1] FLASH_IO[4] H5 VSS_IOC H6 VDD_IOC VSS_CORE
H12 VSS_IOD
H13 VDD_IOA H14 JTAG_TCK H15 U5_TX
Table 3. Pin allocation table (TFBGA296)
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollersH16 HIGHCORE/LCDVD[17][1] H17 JTAG_NTRST H18 JTAG_RTCK
Row J EMC_A[20]/P1[20] J2 EMC_A[21]/P1[21] J3 EMC_A[22]/P1[22] EMC_A[23]/P1[23] J5 VDD_IOC J6 VDD_EMC VDD_CORE
J12 VDD_CORE
J13 VDD_IOA J14 U3_RX/GPI_18 J15 JTAG_TDO
J16 JTAG_TDI J17 U3_TX J18 U2_HCTS/U3_CTS/GPI_16
Row K EMC_A[19]/P1[19] K2 EMC_A[18]/P1[18] K3 EMC_A[16]/P1[16] EMC_A[17]/P1[17] K5 VSS_EMC K6 VDD_EMC VDD_EMC
K12 VSS_CORE
K13 VSS_IOA K14 VDD_RTC K15 U1_RX/CAP1[0]/GPI_15
K16 U1_TX K17 U2_TX/U3_DTR K18 U2_RX/U3_DSR/GPI_17
Row L EMC_A[15]/P1[15] L2 EMC_CKE1 L3 EMC_A[0]/P1[0] EMC_A[1]/P1[1] L5 VSS_EMC L6 VDD_EMC VSS_CORE
L12 VDD_COREFXD
L13 VDD_RTCCORE L14 VSS_RTCCORE L15 P0[4]/I2S0RX_WS/LCDVD[6][1]
L16 P0[5]/I2S0TX_SDA/LCDVD[7][1] L17 P0[6]/I2S0TX_CLK/
LCDVD[12][1] L18 P0[7]/I2S0TX_WS/LCDVD[13][1]
Row M EMC_A[2]/P1[2] M2 EMC_A[3]/P1[3] M3 EMC_A[4]/P1[4] EMC_A[8]/P1[8] M5 VSS_EMC M6 VDD_EMC VDD_CORE M8 VDD_EMC M9 VSS_CORE
M10 VSS_CORE M11 VDD_CORE M12 VSS_CORE
M13 VDD_COREFXD M14 RESET M15 ONSW
M16 GPO_23/U2_HRTS/U3_RTS M17 P0[2]/I2S0RX_SDA/
LCDVD[4][1] M18 P0[3]/I2S0RX_CLK/LCDVD[5][1]
Row N EMC_A[5]/P1[5] N2 EMC_A[6]/P1[6] N3 EMC_A[7/P1[7] EMC_A[12]/P1[12] N5 VSS_EMC N6 VSS_EMC VDD_EMC N8 VDD_EMC N9 VDD_EMC
N10 VDD_EMC N11 VDD_EMC N12 VDD_AD
N13 VDD_AD N14 VDD_FUSE N15 VDD_RTCOSC
N16 GPI_5/U3_DCD N17 GPI_28/U3_RI N18 GPO_17
Row P EMC_A[9]/P1[9] P2 EMC_A[10]/P1[10] P3 EMC_A[11]/P1[11] EMC_DQM[1] P5 EMC_DQM[3] P6 VSS_EMC
Table 3. Pin allocation table (TFBGA296)
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers[1] LCD on LPC3230 and LPC3250 only.
[2] Ethernet on LPC3240 and LPC3250 only. VSS_EMC P8 VSS_EMC P9 VSS_EMC
P10 VSS_EMC P11 VSS_EMC P12 EMC_BLS[3]
P13 VSS_AD P14 VSS_OSC P15 VDD_PLLUSB
P16 RTCX_IN P17 RTCX_OUT P18 VSS_RTCOSC
Row R EMC_A[13]/P1[13] R2 EMC_A[14]/P1[14] R3 EMC_DQM[0] EMC_WR R5 EMC_CAS R6 EMC_DYCS0 EMC_D[1] R8 EMC_D[7] R9 EMC_D[17]/EMC_DQS1
R10 EMC_D[24]/P2[5] R11 EMC_CS1 R12 EMC_BLS[2]
R13 TS_XP R14 PLL397_LOOP R15 SYSX_OUT
R16 VSS_PLLUSB R17 VDD_PLLHCLK R18 VSS_PLLHCLK
Row T EMC_DQM[2] T2 EMC_RAS T3 EMC_CLK EMC_CLKIN T5 EMC_D[2] T6 EMC_D[6] EMC_D[11] T8 EMC_D[14] T9 EMC_D[20]/P2[1]
T10 EMC_D[23]/P2[4] T11 EMC_D[27]/P2[8] T12 EMC_CS2
T13 EMC_BLS[1] T14 ADIN1/TS_XM T15 VSS_PLL397
T16 VDD_PLL397 T17 SYSX_IN T18 VDD_OSC
Row U n.c. U3 EMC_CKE0 EMC_D[0] U5 EMC_D[3] U6 EMC_D[9] EMC_D[12] U8 EMC_D[15] U9 EMC_D[19]/P2[0]
U10 EMC_D[22]/P2[3] U11 EMC_D[26]/P2[7] U12 EMC_D[30]/P2[11]
U13 EMC_CS0 U14 EMC_BLS[0] U15 ADIN0/TS_YM
U16 TS_YP U17 n.c.
Row V EMC_D[4] EMC_D[5] V5 EMC_D[8] V6 EMC_D[10] EMC_D[13] V8 EMC_D[16]/EMC_DQS0 V9 EMC_D[18]/EMC_CLK
V10 EMC_D[21]/P2[2] V11 EMC_D[25]/P2[6] V12 EMC_D[28]/P2[9]
V13 EMC_D[29]/P2[10] V14 EMC_D[31]/P2[12] V15 EMC_CS3
V16 ADIN2/TS_AUX_IN
Table 3. Pin allocation table (TFBGA296)
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
6.2 Pin description
Table 4. Pin description
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
GPI_9/KEY_COL7/
ENET_COL
E12 VDD_IOD I General purpose input 9 Keyscan column 7 input Ethernet collision input (LPC3240 and LPC3250
only)
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
ONSW M15 VDD_RTC O RTC match output for external power control
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
VDD_AD N12,
N13
VDD_AD power 3.3 V supply for ADC/touch screen
VDD_CORE G7,
G9,
G11,
J7,
J12,
M7,
M11
VDD_CORE power 1.2 V or 0.9 V supply for core
VDD_COREFXD L12,
M13
VDD_COREFXD power Fixed 1.2 V supply for digital portion of the analog
block
VDD_EMC J6,
K6,
K7,
L6,
M6,
M8,
N7,
N8,
N9,
N10,
N11
VDD_EMC power 1.8 V or 2.5 V or 3.3 V supply for
External Memory Controller (EMC)
VDD_IOA H13,
J13
VDD_IOA power 1.8 V or 3.3 V supply for IOA domain
VDD_IOB F8 VDD_IOB power 1.8 V or 3.3 V supply for IOB domain
VDD_IOC F7,
G6,
H6, J5
VDD_IOC power 1.8 V or 3.3 V supply for IOC domain
VDD_IOD F13,
VDD_IOD power 1.8 V to 3.3 V supply for IOD domain
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
[1] The PWM2_CTRL register controls this pin function (see LPC32x0 User manual).
VDD_FUSE N14 VDD_FUSE power 1.2 V supply
VSS_CORE G8,
G10,
G12,
H7,
K12,
L7,
M9,
M10,
M12 power Ground for core
VSS_EMC K5,
L5,
M5,
N5,
N6,
P6,
P7,
P8,
P9,
P10,
P11 power Ground for EMC
VSS_IOA K13 - power Ground VDD_IOA domain
VSS_IOB F6 - power Ground VDD_IOB domain
VSS_IOC F5,
G5, power Ground VDD_IOC domain
VSS_IOD F10,
F11,
F12,
H12 power Ground VDD_IOD domain
VSS_OSC P14 - power Ground for main oscillator
Table 4. Pin description …continued
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
[1] See LPC32x0 User manual for details.
Table 5. Digital I/O pad types[1]
I/O type I = input.
O = output.
I/O = bidirectional.
I/O T = bidirectional or high impedance.
Pin detail BK: pin has a bus keeper function that weakly retains the last logic
level driven on an I/O pin.
Bus keeper current for different I/O pin voltages:
0 V= 1 A (max)
VDD_x = 1 A (max)
2/3 VDD_x = 55 A (max)
1/3 VDD_x = 60 A (max)
PU: pin has a nominal 50 A internal pull-up connected.
PD: pin has a nominal 50 A internal pull-down connected.
P: pin has programmable input characteristics.
Table 6. Supply domains
VDD_CORE 0.9 V to 1.39 V VDD_CORE Core power domain.
VDD_COREFXD 1.2 V VDD_COREFXD Fixed 1.2 V supply for digital portion of
the analog block.
other core
domains
1.2 V VDD_PLL397,
VDD_PLLHCLK,
VDD_PLLUSB,
VDD_FUSE,
VDD_OSC
1.2 V supplies, tied to
VDD_COREFXD.
VDD_RTC 0.9 V to 1.39 V VDD_RTC,
VDD_RTCCORE,
VDD_RTCOSC
RTC supply domain. Can be
connected to a battery backed-up
power source.
VDD_AD 2.7 V to 3.6 V VDD_AD 3.3 V supply for ADC and touch
screen.
VDD_EMC 1.7 V to 1.95 V
2.3 V to 2.7 V
2.7 V to 3.6 V
VDD_EMC External memory interface IO pins in
1.8 V range, 2.5 V range, or 3.3 V
range.
VDD_IOA[1] 1.7 V to 1.95 V or
2.7 V to 3.6 V
VDD_IOA Peripheral supply.
VDD_IOB[1] 1.7 V to 1.95 V or
2.7 V to 3.6 V
VDD_IOB Peripheral supply.
VDD_IOC[1] 1.7 V to 1.95 V or
2.3 V to 3.6 V
VDD_IOC Peripheral supply.
VDD_IOD[1] 1.7 V to 1.95 V or
2.7 V to 3.6 V
VDD_IOD Peripheral supply.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
[1] The VDD_IOA, VDD_IOB, VDD_IOC, and VDD_IOD supply domains can be operated at a voltage
independent of the other domains as long as all pins connected to the same peripheral are at the same
voltage level. There are two special cases for determining supply domain voltages (for details see
application note AN10777): Ethernet configured in MII mode: VDD_IOD must be the same as VDD_IOB. UART 3 when used with hardware flow control or when sharing an RS-232 transceiver with another
UART: VDD_IOA must be the same as VDD_IOD.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
7. Functional description
7.1 CPU and subsystems
7.1.1 CPU
NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a
Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented a 32 kB
instruction cache, a 32 kB data cache and a Vector Floating Point coprocessor. The
ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the
virtual memory capabilities required to support the multi-programming demands of
modern operating systems. The basic ARM926EJ-S core V5TE instruction set includes
DSP instruction extensions for native Jazelle Java Byte-code execution in hardware. The
LPC3220/30/40/50 operates at CPU frequencies up to 266 MHz.
7.1.2 Vector Floating Point (VFP) coprocessor
The LPC3220/30/40/50 includes a VFP co-processor providing full support for
single-precision and double-precision add, subtract, multiply, divide, and
multiply-accumulate operations at CPU clock speeds. It is compliant with the IEEE 754
standard for binary Floating-Point Arithmetic. This hardware floating point capability
makes the microcontroller suitable for advanced motor control and DSP applications. The
VFP has 3 separate pipelines for floating-point MAC operations, divide or square root
operations, and Load/Store operations. These pipelines operate in parallel and can
complete execution out of order. All single-precision instructions execute in one cycle,
except the divide and square root instructions. All double-precision multiply and
multiply-accumulate instructions take two cycles. The VFP also provides format
conversions between floating-point and integer word formats.
7.1.3 Emulation and debugging
The LPC3220/30/40/50 supports emulation and debugging via a dedicated JTAG serial
port. An Embedded Trace Buffer allows tracing program execution. The dedicated JTAG
port allows debugging of all chip features without impact to any pins that may be used in
the application.
7.1.3.1 Embedded ICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
Embedded ICE protocol converter. The Embedded ICE protocol converter converts the
Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel (DCC) function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or entering the
debug state.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.1.3.2 Embedded trace buffer
The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses
the trace information and exports it through a narrow trace port. An internal Embedded
Trace Buffer (ETB) of 2048 24 bits captures the trace information under software
debugger control. Data from the ETB is recovered by the debug software through the
JTAG port.
The trace contains information about when the ARM core switches between states.
Instruction shows the flow of execution of the processor and provides a list of all the
instructions that were executed. Instruction trace is significantly compressed by only
broadcasting branch addresses as well as a set of status signals that indicate the pipeline
status on a cycle by cycle basis. For data accesses either data or address or both can be
traced.
7.2 AHB matrix
The LPC3220/30/40/50 has a multi-layer AHB matrix for inter-block communication. AHB
is an ARM defined high-speed bus, which is part of the ARM bus architecture. AHB is a
high-bandwidth low-latency bus that supports multi-master arbitration and a bus
grant/request mechanism. For systems that have only one (CPU), or two (CPU and DMA)
bus masters a simple AHB works well. However, if a system requires multiple bus masters
and the CPU needs access to external memory, a single AHB bus can cause a bottleneck.
To increase performance, the LPC3220/30/40/50 uses an expanded AHB architecture
known as Multi-layer AHB. A Multi-layer AHB replaces the request/grant and arbitration
mechanism used in a simple AHB with an interconnect matrix that moves arbitration out
toward the slave devices. Thus, if a CPU and a DMA controller want access to the same
memory, the interconnect matrix arbitrates between the two when granting access to the
memory. This advanced architecture allows simultaneous access by bus masters to
different resources with an increase in arbitration complexity. In this architectural
implementation, removing guaranteed central arbitration and allowing more than one bus
master to be active at the same time provides better overall microcontroller performance.
In the LPC3220/30/40/50, the multi-Layer AHB system has a separate bus for each of
seven AHB Masters: CPU data bus CPU instruction bus General purpose DMA Master 0 General purpose DMA Master 1 Ethernet controller USB controller LCD controller
There are no arbitration delays unless two masters attempt to access the same slave at
the same time.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.2.1 APB
Many peripheral functions are accessed by on-chip APBs that are attached to the higher
speed AHB. The APB performs reads and writes to peripheral registers in three peripheral
clocks.
7.2.2 FAB
Some peripherals are placed on a special bus called FAB that allows faster CPU access
to those peripheral functions. A write access to FAB peripherals takes a single AHB clock
and a read access to FAB peripherals takes two AHB clocks.
7.3 Physical memory map
The physical memory map incorporates several distinct regions, as shown in Figure3.
When an application is running, the CPU interrupt vectors are re-mapped to allow them to
reside in on-chip SRAM (IRAM).
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.4 Internal memory
7.4.1 On-chip ROM
The built-in 16 kB ROM contains a program which runs a boot procedure to load code
from one of four external sources, UART 5, SSP0 (SPI mode), EMC Static CS0 memory,
or NAND FLASH.
After reset, execution always begins from the internal ROM. The bootstrap software first
reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot
and can download a program over serial link UART 5 to IRAM and transfer execution to
the downloaded code.
If the SERVICE pin is HIGH, the bootstrap routine jumps to normal boot. The normal boot
process first tests SPI memory for boot information if present it uploads the boot code and
transfers execution to the uploaded software. If the SPI is not present or no software is
loaded, the bootloader will test the EMC Static CS0 memory for the presence of boot code
and if present boots from static memory, If this test fails the boot loader will test external
NAND flash for boot code and boot if code is present.
The boot loader consumes no user memory space because it is in ROM.
7.4.2 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8, 16, or 32 bit memory. The LPC3220/30/40/50 provides 256 kB of internal SRAM.
7.5 External memory interfaces
The LPC3220/30/40/50 includes three external memory interfaces, NAND Flash
controllers, Secure Digital Memory Controller, and an external memory controller for
SDRAM, DDR SDRAM, and Static Memory devices.
7.5.1 NAND flash controllers
The LPC3220/30/40/50 includes two NAND flash controllers, one for multi-level cell
NAND flash devices and one for single-level cell NAND flash devices. The two NAND
flash controllers use the same pins to interface to external NAND flash devices, so only
one interface is active at a time.
7.5.1.1 Multi-Level Cell (MLC) NAND flash controller
The MLC NAND flash controller interfaces to either multi-level or single-level NAND flash
devices. An external NAND flash device is used to allow the bootloader to automatically
load a portion of the application code into internal SRAM for execution following reset.
The MLC NAND flash controller supports small (528 byte) and large (2114 byte) pages.
Programmable NAND timing parameters allow support for a variety of NAND flash
devices. A built-in Reed-Solomon encoder/decoder provides error detection and
correction capability. A 528 byte data buffer reduces the need for CPU supervision during
loading. The MLC NAND flash controller also provides DMA support.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.5.1.2 Single-Level Cell (SLC) NAND flash controller
The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page
transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support
for ECC (Error Checking and Correction) is included for the main data area. Software can
correct a single bit error.
7.5.2 SD card controller
The SD interface allows access to external SD memory cards. The SD card interface
conforms to the SD Memory Card Specification Version 1.01.
7.5.2.1 Features 1-bit and 4-bit data line interface support. DMA is supported through the system DMA controller. Provides all functions specific to the SD memory card. These include the clock
generation unit, power management control, command and data transfer.
7.5.3 External memory controller
The LPC3220/30/40/50 includes a memory controller that supports data bus SDRAM,
DDR SDRAM, and static memory devices. The memory controller provides an interface
between the system bus and external (off-chip) memory devices.
The controller supports 16-bit and 32-bit wide SDR SDRAM devices of 64 Mbit, 128 Mbit,
128 Mbit, 256 Mbit, and 512 Mbit sizes, as well as 16-bit wide data bus DDR SDRAM
devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes. Two dynamic
memory chip selects are supplied, supporting two groups of SDRAM: DYCS0 in the address range 0x8000 0000 to 0x9FFF FFFF DYCS1 in the address range 0xA000 0000 to 0xBFFF FFFF
The memory controller also supports 8-bit, 16-bit, and 32-bit wide asynchronous static
memory devices, including RAM, ROM, and flash, with or without asynchronous page
mode. Four static memory chip selects are supplied for SRAM devices: CS0 in the address range 0xE000 0000 to 0xE0FF FFFF CS1 in the address range 0xE100 0000 to 0xE1FF FFFF CS2 in the address range 0xE200 0000 to 0xE2FF FFFF CS3 in the address range 0xE300 0000 to 0xE3FF FFFF
The SDRAM controller uses three data ports to allow simultaneous requests from multiple
on-chip AHB bus masters and has the following features. Dynamic memory interface supports SDRAM, DDR-SDRAM, and low-power variants. Read and write buffers to reduce latency and improve performance. Static memory features include asynchronous page mode read programmable wait states bus turnaround cycles output enable and write enable delays
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers extended wait Power-saving modes dynamically control EMC_CKE[1:0] and EMC_CLK. Dynamic memory self-refresh mode supported by software. Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is,
typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16, or 32 data bits per
device. Two reset domains enable dynamic memory contents to be preserved over a soft
reset. This controller does not support synchronous static memory devices (burst mode
devices).
7.6 AHB master peripherals
The LPC3220/30/40/50 implements four AHB master peripherals, which include a
General Purpose Direct Memory Access (GPDMA) controller, a 10/100 Ethernet Media
Access Controller (MAC), a Universal Serial Bus (USB) controller, and an LCD controller.
Each of these four peripherals contain an integral DMA controller optimized to support the
performance demands of the peripheral.
7.6.1 General Purpose DMA (GPDMA) controller
The GPDMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the same AHB master, or one area by each master. The DMA
controller supports the following peripheral device transfers. Secure Digital (SD) Memory interface High-speed UARTsI2 S0 and I2 S1 ports SPI1 and SPI2 interfaces SSP0 and SSP1 interfaces Memory
The DMA controls eight DMA channels with hardware prioritization. The DMA controller
interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width.
DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either
big-endian or little-endian. Incrementing or non-incrementing addressing for source and
destination are supported, as well as programmable DMA burst size. Scatter or gather
DMA is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas of memory.
7.6.2 Ethernet MAC
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can
access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces
between an off-chip Ethernet PHY using the Media Independent Interface (MII) or
Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management
(MIIM) serial bus.
7.6.2.1 Features Ethernet standards support: Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4. Fully compliant with IEEE standard 802.3. Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure. Flexible transmit and receive frame options. Virtual Local Area Network (VLAN) frame support. Memory management: Independent transmit and receive buffers memory mapped to SRAM. DMA managers with scatter/gather DMA and arrays of frame descriptors. Memory traffic optimized by buffering and pre-fetching. Enhanced Ethernet features: Receive filtering. Multicast and broadcast frame support for both transmit and receive. Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit. Selectable automatic transmit frame padding. Over-length frame support for both transmit and receive allows any length frames. Promiscuous receive mode. Automatic collision back-off and frame retransmission. Includes power management by clock switching. Wake-on-LAN power
management support allows system wake-up using the receive filters or a magic
frame detection filter. Physical interface Attachment of external PHY chip through standard MII or RMII interface. PHY register access is available via the MIIM interface.
7.6.3 USB interface
The LPC3220/30/40/50 supports USB in either device, host, or OTG configuration.
7.6.3.1 USB device controller
The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory and DMA
controller. The serial interface engine decodes the USB data stream and writes data to the
appropriate end point buffer memory. The status of a completed USB transfer or error
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
condition is indicated via status registers. An interrupt is also generated if enabled. The
DMA controller when enabled transfers data between the endpoint buffer and the USB
RAM.
Features Fully compliant with USB 2.0 full-speed specification. Supports 32 physical (16 logical) endpoints. Supports control, bulk, interrupt and isochronous endpoints. Scalable realization of endpoints at run time. Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time. RAM message buffer size based on endpoint realization and maximum packet size. Supports bus-powered capability with low suspend current. Supports DMA transfer on all non-control endpoints. One duplex DMA channel serves all endpoints. Allows dynamic switching between CPU controlled and DMA modes. Double buffer implementation for bulk and isochronous endpoints.
7.6.3.2 USB host controller
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
Features OHCI compliant. OHCI specifies the operation and interface of the USB host controller and software
driver. The host controller has four USB states visible to the software driver: USBOperational: Process lists and generate SOF tokens. USBReset: Forces reset signaling on the bus, SOF disabled. USBSuspend: Monitor USB for wake-up activity. USBResume: Forces resume signaling on the bus. HCCA register points to interrupt and isochronous descriptors list. ControlHeadED and BulkHeadED registers point to control and bulk descriptors list.
7.6.3.3 USB OTG controller
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals.
Features Fully compliant with On-The-Go supplement to the USB Specification 2.0 Revision
1.0.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for
dual-role devices under software control. HNP is partially implemented in hardware. Provides programmable timers required for HNP and SRP. Supports slave mode operation through AHB slave interface. Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG
specification compliant ATX.
7.6.4 LCD controller
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
7.6.4.1 Features AHB bus master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces. Supports single and dual-panel color STN displays. Supports Thin Film Transistor (TFT) color displays. Programmable display resolution including, but not limited to: 320 200, 320 240,
640 200, 640 240, 640 480, 800 600, and 1024 768. Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 k color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized, for color STN and TFT. 24 bpp true-color non-palettized, for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128 32 bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock or from a clock input pin.
NXP Semiconductors LPC3220/30/40/50
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7.7 System functions
To enhance the performance of the LPC3220/30/40/50 incorporates the following system
functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and
several power control features. These functions are described in the following sections
7.7.1 Interrupt controller
The interrupt controller is comprised of three basic interrupt controller blocks, supporting a
total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled
and configured for high or low level triggering, or rising or falling edge triggering. Each
interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt
status and masked interrupt status registers allow versatile condition evaluation. In
addition to peripheral functions, each of the six general purpose input/output pins and of the 22 general purpose input pins are connected directly to the interrupt controller.
7.7.2 Watchdog timer
The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit
counter. A match register is compared to the Timer. When configured for watchdog
functionality, a match drives the match output low. The match output is gated with an
enable signal that gives the opportunity to generate two type of reset signal: one that only
resets chip internally, and another that goes through a programmable pulse generator
before it goes to the external pin RESOUT and to the internal chip reset.
7.7.2.1 Features Programmable 32-bit timer. Internally resets the device if not periodically reloaded. Flag to indicate that a watchdog reset has occurred. Programmable watchdog pulse output on RESOUT pin. Can be used as a standard timer if watchdog is not used. Pause control to stop counting when core is in debug state.
7.7.3 Millisecond timer
The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to
obtain a lower count rate.
The millisecond timer includes three match registers that are compared to the
Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter
either continue to run, stop, or be reset.
7.7.3.1 Features 32-bit Timer/Counter, running from the 32 kHz RTC clock. Counter or Timer operation. Three 32-bit match registers that allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation. Pause control to stop counting when core is in debug state.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.7.4 Clocking and power control features
7.7.4.1 Clocking
Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and
peripheral requirements may be met, while allowing optimization of power consumption.
Clocks to most functions may be turned off if not needed and some peripherals do this
automatically.
The LPC3220/30/40/50 supports three operational modes, two of which are specifically
designed to reduce power consumption. The modes are: Run mode, Direct run mode, and
Stop mode.These three operational modes give control over processing speed and power
consumption. In addition, clock rates to different functional blocks may be changed by
switching clock sources, changing PLL values, or altering clock divider configurations.
This allows a trade-off of power versus processing speed based on application
requirements.
7.7.4.2 Crystal oscillator
The main oscillator is the basis for the clocks most chip functions use by default.
Optionally, many functions can be clocked instead by the output of a PLL (with a fixed
397x rate multiplication) which runs from the RTC oscillator. In this mode, the main
oscillator may be turned off unless the USB interface is enabled. If a SYSCLK frequency
other than 13 MHz is required in the application, or if the USB block is not used, the main
oscillator may be used with a frequency of between 1 MHz and 20 MHz.
7.7.4.3 PLLs
The LPC3220/30/40/50 includes three PLLs: The 397x PLL allows boosting the RTC
frequency to 13.008896 MHz for use as the primary system clock. The USB PLL provides
the 48 MHz clock required by the USB block, and the HCLK PLL provides the basis for the
CPU clock, the AHB bus clock, and the main peripheral clock.
The 397x PLL multiplies the 32768 Hz RTC clock by 397 to obtain a 13.008896 MHz
clock. The 397x PLL is designed for low power operation and low jitter. This PLL requires
an external RC loop filter for proper operation.
The HCLK PLL accepts an input clock from either the main oscillator or the output of the
397x PLL. The USB PLL only accepts an input clock from the main oscillator.The USB
input clock runs through a divide-by-N pre-divider before entering the USB PLL.
The input to the HCLK and USB PLLs may initially be divided down by a pre-divider value
‘N’, which may have the values 1, 2, 3, or 4. This pre-divider can allow a greater number of
possibilities for the output frequency. Following the PLL input divider is the PLL multiplier.
This can multiply the pre-divider output by a value ‘M’, in the range of 1 through 256. The
resulting frequency must be in the range of 156 MHz to 320 MHz. The multiplier works by
dividing the output of a Current Controlled Oscillator (CCO) by the value of M, then using
a phase detector to compare the divided CCO output to the pre-divider output. The error
value is used to adjust the CCO frequency.
At the PLL output, there is a post-divider that can be used to bring the CCO frequency
down to the desired PLL output frequency. The post-divider value can divide the CCO
output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
output to be used directly. The maximum PLL output frequency supported by the CPU is
266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock
has strict requirements for nominal frequency (500 ppm) and jitter (500 ps).
7.7.4.4 Power control modes
The LPC3220/30/40/50 supports three operational modes, two of which are specifically
designed to reduce power consumption. The modes are: Run mode, Direct Run mode,
and Stop mode.
Run mode is the normal operating mode for applications that require the CPU, AHB bus,
or any peripheral function other than the USB block to run faster than the main oscillator
frequency. In Run mode, the CPU can run at up to 266 MHz and the AHB bus can run at
up to 133 MHz.
Direct Run mode allows reducing the CPU and AHB bus rates in order to save power.
Direct Run mode can also be the normal operating mode for applications that do not
require the CPU, AHB bus, or any peripheral function other than the USB block to run
faster than the main oscillator frequency. Direct Run mode is the default mode following
chip reset.
Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals
other than the USB block.
7.7.4.5 Reset
Reset is accomplished by an active LOW signal on the RESET input pin. A reset pulse
with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to
guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the
oscillator to start up and stabilize after VDD reaches operational voltage. An internal reset
with a minimum duration of 10 clock pulses will also be applied if the watchdog timer
generates an internal device reset.
The RESET pin is located in the RTC power domain. This means that the RTC power
must be present for an external reset to have any effect. The RTC power domain
nominally runs from 1.2 V, but the RESET pin can be driven as high as 1.95V.
7.8 Communication peripheral interfaces
In addition to the Ethernet MAC and USB interfaces there are many more serial
communication peripheral interfaces available on the LPC3220/30/40/50. Here is a list of
the serial communication interfaces: Seven UARTs; four standard UARTs and three high-speed UARTs Two SPI serial I/O controllers Two SSP serial I/O controllers Two I2 C serial I/O controllers Two I2 S audio controllers
A short functional description of each of these peripherals is provided in the following
sections.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.8.1 UARTs
The LPC3220/30/40/50 contains seven UARTs. Four are standard UART s, and three are
high-speed UARTs.
7.8.1.1 Standard UARTs
The four standard UARTs are compatible with the INS16Cx50. These UART s support
rates up to 460800 bit/s from a 13 MHz peripheral clock.
Features Each standard UART has 64 byte Receive and Transmit FIFOs. Receiver FIFO trigger points at 16, 32, 48, and 60 Bytes. Transmitter FIFO trigger points at 0, 4, 8, and 16 Bytes. Register locations conform to the “550” industry standard. Each standard UART has a fractional rate pre-divider and an internal baud rate
generator. The standard UARTs support three clocking modes: on, off, and auto-clock. The
auto-clock mode shuts off the clock to the UART when it is idle. UART 6 includes an IrDA mode to support infrared communication. The standard UARTs are designed to support data rates of (2400, 4800, 9600,
19200, 38400, 57600, 115200, 230400, 460800) bit/s. Each UART includes an internal loopback mode.
7.8.1.2 High-speed UARTs
The three high-speed UARTs are designed to support rates up to 921600 bit/s from a MHz peripheral clock for on-board communication in low noise conditions. This is
accomplished by changing the over sampling from 16 to 14 and altering the rate
generation logic.
Features Each high-speed UART has 64-byte Receive and Transmit FIFOs. Receiver FIFO trigger points at 1, 4, 8, 16, 32, and 48B. Transmitter FIFO trigger points at 0, 4, and 8B. Each high-speed UART has an internal baud rate generator. The high-speed UARTs are designed to support data rates of (2400, 4800, 9600,
19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s. The three high speed UART s only support (8N1) 8-bit data word length, 1-stop bit, no
parity, and no flow control as a the communications protocol. Each UART includes an internal loopback mode.
7.8.2 SPI serial I/O controller
The LPC3220/30/40/50 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire
serial interface that is able to interface with a large range of serial peripheral or memory
devices (SPI mode 0 to 3 compatible slave devices).
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
Only a single master and a single slave can communicate on the interface during a given
data transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master. The SPI implementation on the
LPC3220/30/40/50 does not support operation as a slave.
7.8.2.1 Features Supports slaves compatible with SPI modes 0 to 3. Half duplex synchronous transfers. DMA support for data transmit and receive. 1-bit to 16-bit word length. Choice of LSB or MSB first data transmission. 64 16-bit input or output FIFO. Bit rates up to 52 Mbit/s. Busy input function. DMA time out interrupt to allow detection of end of reception when using DMA. Timed interrupt to facilitate emptying the FIFO at the end of a transmission. SPI clock and data pins may be used as general purpose pins if the SPI is not used. Slave selects can be supported using GPO or GPIO pins
7.8.3 SSP serial I/O controller
The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.8.3.1 Features Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame Maximum SPI bus data bit rate of 1 ⁄2 (Master mode) and 1 ⁄2 (Slave mode) of the input
clock rate DMA transfers supported by GPDMA
7.8.4I2 C-bus serial I/O controller
There are two I2 C-bus interfaces in the LPC32x0 family of controllers. These I2 C blocks
can be configured as a master, multi-master or slave supporting up to 400 kHz. The I2C
blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit
and receive. An interrupt signal is available from each block.
NXP Semiconductors LPC3220/30/40/50
16/32-bit ARM microcontrollers
There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are
only available when the controller is configured as a Master/Slave device and is operating
in a multi-master environment. Separate TX FIFOs are needed in a multi-master because
a controller might have a message queued for transmission when an external master
addresses it to be come a slave-transmitter, a second source of data is needed.
Note that the I2 C clock must be enabled in the I2CCLK_CTRL register before using the 2 C. The I2 C clock can be disabled between communications, if used as a single master 2 C-bus interface, software has full control of when I2 C communication is taking place on
the bus.
7.8.4.1 Features The two I2 C-bus blocks are standard I2 C-bus compliant interfaces that may be used in
Single-master, Multi-master or Slave modes. Programmable clock to allow adjustment of I2 C-bus transfer rates. Bidirectional data transfer. Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus. Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
7.8.5I2 S-bus audio controller
The I2 S-bus provides a standard communication interface for digital audio applications
The I2 S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. Each I2 S connection can act as a master or a slave. The
master connection determines the frequency of the clock line and all other slaves are
driven by this clock source. The two I2 S-bus interfaces on the LPC3220/30/40/50 provides
a separate transmit and receive channel, providing a total of two transmit channels and
two receive channels. Each I2 S channel supports monaural or stereo formatted data.
7.8.5.1 Features The interface has separate input/output channels each of which can operate in master
or slave mode. Capable of handling 8-bit, 16-bit, and 32-bit word sizes. Mono and stereo audio data supported. Supports standard sampling frequencies (8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, kHz, 44.1 kHz, 48 kHz, 96 kHz). Word select period can be configured in master mode (separately for I2 S input and
output). Two eight-word FIFO data buffers are provided, one for transmit and one for receive. Generates interrupt requests when buffer levels cross a programmable boundary. Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block. Controls include reset, stop, and mute options separately for I2 S input and I2 S output.
