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LPC2939FBD208NXPN/a10avaiARM9 microcontroller with CAN, LIN, and USB


LPC2939FBD208 ,ARM9 microcontroller with CAN, LIN, and USBFeatures and benefits ARM968E-S processor running at frequencies of up to 125 MHz maximum. Multil ..
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LPC2939FBD208
ARM9 microcontroller with CAN, LIN, and USB
1. General description
The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocks
operating at frequencies of up to 125 MHz, Full-speed USB 2.0 Host/OTG/Device
controller, CAN and LIN, 56 kB SRAM, 768 kB flash memory, external memory interface,
three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at
consumer, industrial, medical, and communication markets. T o optimize system power
consumption, the LPC2939 has a very flexible Clock Generation Unit (CGU) that provides
dynamic clock gating and scaling.
2. Features and benefits
ARM968E-S processor running at frequencies of up to 125 MHz maximum. Multilayer AHB system bus at 125 MHz with four separate layers. On-chip memory: Two Tightly Coupled Memories (TCM), 32 kB Instruction (ITCM), 32 kB Data TCM
(DTCM) Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM 8 kB ETB SRAM, also usable for code execution and data 768 kB high-speed flash program memory 16 kB true EEPROM, byte-erasable/programmable Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus Serial interfaces: USB 2.0 full-speed Host/OTG/Device controller with dedicated DMA controller and
on-chip device PHY Two-channel CAN controller supporting FullCAN and extensive message filtering Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces. Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, modem
control, and RS-485/EIA-485 (9-bit) support Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO Two I2 C-bus interfaces
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Rev. 03 — 7 April 2010 Product data sheet
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Other peripherals: One 10-bit ADC with 5.0 V measurement range and eight input channels with
conversion times as low as 2.44 s per channel Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide an
additional 16 analog inputs with conversion times as low as 2.44 s per channel.
Each channel provides a compare function to minimize interrupts. Multiple trigger-start option for all ADCs: timer, PWM, other ADC, and external
signal input Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality Two dedicated 32-bit timers to schedule and synchronize PWM and ADC Quadrature encoder interface that can monitor one external quadrature encoder 32-bit watchdog with timer change protection, running on safe clock Up to 152 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper Vectored Interrupt Controller (VIC) with 16 priority levels Up to 22 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up
features Configurable clock-out pin for driving external system clocks Processor wake-up from power-down via external interrupt pins and CAN or LIN
activity Flexible Reset Generator Unit (RGU) able to control resets of individual modules Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
modules: On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring On-chip crystal oscillator with a recommended operating range from 10 MHz to MHz. PLL input range 10 MHz to 25 MHz. On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz Generation of up to 11 base clocks Seven fractional dividers Second, dedicated CGU with its own PLL generates USB clocks and a configurable
clock output Highly configurable system Power Management Unit (PMU): clock control of individual modules allows minimization of system operating power consumption in any configuration Standard ARM test and debug interface with real-time in-circuit emulator Boundary-scan test supported ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage Dual power supply: CPU operating voltage: 1.8V 5% I/O operating voltage: 2.7Vto 3.6 V; inputs tolerant up to 5.5V 208-pin LQFP package
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
40 C to +85 C ambient operating temperature range
3. Ordering information

3.1 Ordering options

Table 1. Ordering information

LPC2939FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1
Table 2. Part options

LPC2939FBD208 768 kB 56 kB +
2  32 kB TCM
32-bit yes 2 2 2 LQFP208
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
4. Block diagram

NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
5. Pinning information
5.1 Pinning

5.2 Pin description
5.2.1 General description

The LPC2939 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each,
port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins. The pin to which each
function is assigned is controlled by the SFSP registers in the SCU. The functions
combined on each port pin are shown in the pin description tables in this section.
5.2.2 LQFP208 pin assignment

Table 3. LQFP208 pin assignment

TDO 1[1] IEEE 1149.1 test data out
P2[21]/SDI2/
PCAP2[1]/D19[1] GPIO 2, pin 21 SPI2 SDI PWM2 CAP1 EXTBUS D19
P0[24]/TXD1/
TXDC1/SCS2[0][1] GPIO 0, pin 24 UART1 TXD CAN1 TXD SPI2 SCS0
P0[25]/RXD1/
RXDC1/SDO2[1] GPIO 0, pin 25 UART1 RXD CAN1 RXD SPI2 SDO
P0[26]/TXD1/SDI2 5[1] GPIO 0, pin 26 - UART1 TXD SPI2 SDI
P0[27]/RXD1/SCK2 6[1] GPIO 0, pin 27 - UART1 RXD SPI2 SCK
P0[28]/CAP0[0]/
MAT0[0][1] GPIO 0, pin 28 - TIMER0 CAP0 TIMER0 MAT0
P0[29]/CAP0[1]/
MAT0[1][1] GPIO 0, pin 29 - TIMER0 CAP1 TIMER0 MAT1
VDD(IO) 9 3.3 V power supply for I/O
P2[22]/SCK2/
PCAP2[2]/D20[1] GPIO 2, pin 22 SPI2 SCK PWM2 CAP2 EXTBUS D20
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

P2[23]/SCS1[0]/
PCAP3[0]/D21[1] GPIO 2, pin 23 SPI1 SCS0 PWM3 CAP0 EXTBUS D21
P3[6]/SCS0[3]/
PMAT1[0]/TXDL1[1] GPIO 3, pin 6 SPI0 SCS3 PWM1 MAT0 LIN1/UART TXD
P3[7]/SCS2[1]/
PMAT1[1]/RXDL1[1] GPIO 3, pin 7 SPI2 SCS1 PWM1 MAT1 LIN1/UART RXD
P0[30]/CAP0[2]/
MAT0[2][1] GPIO 0, pin 30 - TIMER0 CAP2 TIMER0 MAT2
P0[31]/CAP0[3]/
MAT0[3][1] GPIO 0, pin 31 - TIMER0 CAP3 TIMER0 MAT3
P2[24]/SCS1[1]/
PCAP3[1]/D22[1] GPIO 2, pin 24 SPI1 SCS1 PWM3 CAP1 EXTBUS D22
P2[25]/SCS1[2]/
PCAP3[2]/D23[1] GPIO 2, pin 25 SPI1 SCS2 PWM3 CAP2 EXTBUS D23
VSS(IO) 18 ground for I/O
P5[19]/USB_D+1 19[2] GPIO 5, pin 19 USB_D+1 - -
P5[18]/USB_D120[2] GPIO 5, pin 18 USB_D1- -
P5[17]/USB_D+2 21[2] GPIO 5, pin 17 USB_D+2 - -
P5[16]/USB_D222[2] GPIO 5, pin 16 USB_D2- -
VDD(IO) 23 3.3 V power supply for I/O
VDD(CORE) 24 1.8 V power supply for digital core
VSS(CORE) 25 ground for core
P1[31]/CAP0[1]/
MAT0[1]/EI5[1] GPIO 1, pin 31 TIMER0 CAP1 TIMER0 MAT1 EXTINT5
VSS(IO) 27 ground for I/O
P4[0]/A8 28[1] GPIO 4, pin 0 EXTBUS A8 - -
P1[30]/CAP0[0]/
MAT0[0]/EI4[1] GPIO 1, pin 30 TIMER0 CAP0 TIMER0 MAT0 EXTINT4
P5[0]/D8 30[1] GPIO 5, pin 0 EXTBUS D8 - -
P3[8]/SCS2[0]/
PMAT1[2]/
USB_OVRCR1[1] GPIO 3, pin 8 SPI2 SCS0 PWM1 MAT2 USB_OVRCR1
P3[9]/SDO2/
PMAT1[3]/
USB_PPWR1[1] GPIO 3, pin 9 SPI2 SDO PWM1 MAT3 USB_PPWR1
P1[29]/CAP1[0]/
TRAP0/ PMAT3[5][1] GPIO 1, pin 29 TIMER1 CAP0/
ADC0 EXTSTART
PWM TRAP0 PWM3 MAT5
VDD(IO) 34 3.3 V power supply for I/O
P4[16]/CS6/
U1OUT1[1] GPIO 4, pin 16 EXTBUS CS6 UART1 OUT1 -
P1[28]/CAP1[1]/
TRAP1/PMAT3[4][1] GPIO 1, pin 28 TIMER1 CAP1/
ADC1 EXTSTART
PWM TRAP1 PWM3 MAT4
P2[26]/CAP0[2]/
MAT0[2]/EI6[1] GPIO 2, pin 26 TIMER0 CAP2 TIMER0 MAT2 EXTINT6
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

P4[8]/A22/DSR1 38 GPIO 4, pin 8 EXTBUS A22 UART1 DSR -
VSS(IO) 39 ground for I/O
P2[27]/CAP0[3]/
MAT0[3]/EI7[1] GPIO 2, pin 27 TIMER0 CAP3 TIMER0 MAT3 EXTINT7
P5[8]/D20/U0OUT2 41[1] GPIO 5, pin 8 EXTBUS D20 UART0 OUT2 -
P1[27]/CAP1[2]/
TRAP2/PMAT3[3][1] GPIO 1, pin 27 TIMER1 CAP2, ADC2
EXTSTART
PWM TRAP2 PWM3 MAT3
P1[26]/PMAT2[0]/
TRAP3/PMAT3[2][1] GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2
P4[20]/
USB_VBUS2[1] GPIO 4, pin 20 USB_VBUS2 - -
VDD(IO) 45 3.3 V power supply for I/O
P1[25]/PMAT1[0]/
USB_VBUS1/
PMAT3[1][1] GPIO 1, pin 25 PWM1 MAT0 USB_VBUS1 PWM3 MAT1
VSS(CORE) 47 ground for core
VDD(CORE) 48 1.8 V power supply for digital core
P1[24]/PMAT0[0]/
USB_CONNECT1/
PMAT3[0][1] GPIO 1, pin 24 PWM0 MAT0 USB_CONNECT1 PWM3 MAT0
P1[23]/RXD0/
USB_SSPND1/
CS5[1] GPIO 1, pin 23 UART0 RXD USB_SSPND1 EXTBUS CS5
P1[22]/TXD0/
USB_UP_LED1/CS4[1] GPIO 1, pin 22 UART0 TXD USB_UP_LED1 EXTBUS CS4
TMS 52[1] IEEE 1149.1 test mode select, pulled up internally
TCK 53[1] IEEE 1149.1 test clock
P1[21]/CAP3[3]/
CAP1[3]/D7[1] GPIO 1, pin 21 TIMER3 CAP3 TIMER1 CAP3,
MSCSS PAUSE
EXTBUS D7
P1[20]/CAP3[2]/
SCS0[1]/D6[1] GPIO 1, pin 20 TIMER3 CAP2 SPI0 SCS1 EXTBUS D6
P1[19]/CAP3[1]/
SCS0[2]/D5[1] GPIO 1, pin 19 TIMER3 CAP1 SPI0 SCS2 EXTBUS D5
P1[18]/CAP3[0]/
SDO0/D4[1] GPIO 1, pin 18 TIMER3 CAP0 SPI0 SDO EXTBUS D4
P1[17]/CAP2[3]/
SDI0/D3[1] GPIO 1, pin 17 TIMER2 CAP3 SPI0 SDI EXTBUS D3
VSS(IO) 59 ground for I/O
P4[4]/A12 60[1] GPIO 4, pin 4 EXTBUS A12 - -
P1[16]/CAP2[2]/
SCK0/D2[1] GPIO 1, pin 16 TIMER2 CAP2 SPI0 SCK EXTBUS D2
P5[4]/D16 62[1] GPIO 5, pin 4 EXTBUS D16 - -
P2[0]/MAT2[0]/
TRAP3/D8[1] GPIO 2, pin 0 TIMER2 MAT0 PWM TRAP3 EXTBUS D8
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

P4[12]/BLS0 64[1] GPIO 4, pin 12 EXTBUS BLS0 --
P2[1]/MAT2[1]/
TRAP2/D9[1] GPIO 2, pin 1 TIMER2 MAT1 PWM TRAP2 EXTBUS D9
P5[12]/D24 66[1] GPIO 5, pin 12 EXTBUS D24 - -
VDD(IO) 67 3.3 V power supply for I/O
P4[1]/A9 68[1] GPIO 4, pin 1 EXTBUS A9 - -
P3[10]/SDI2/
PMAT1[4]/
USB_PWRD1[1] GPIO 3, pin 10 SPI2 SDI PWM1 MAT4 USB_PWRD1
VSS(CORE) 70 ground for core
VDD(CORE) 71 1.8 V power supply for digital core
P5[1]/D9 72[1] GPIO 5, pin 1 EXTBUS D9 - -
P3[11]/SCK2/
PMAT1[5]/USB_LS1[1] GPIO 3, pin 11 SPI2 SCK PWM1 MAT5 USB_LS1
P4[17]/CS7/U1OUT2 74[1] GPIO 4, pin 17 EXTBUS CS7 UART1 OUT2 -
P1[15]/CAP2[1]/
SCS0[0]/D1[1] GPIO 1, pin 15 TIMER2 CAP1 SPI0 SCS0 EXTBUS D1
P4[9]/A23/DCD1 76[1] GPIO4, pin 9 EXTBUS A23 UART1 DCD -
VSS(IO) 77 ground for I/O
P5[9]/D21/DTR0 78[1] GPIO 5, pin 9 EXTBUS D21 UART0 DTR -
P1[14]/CAP2[0]/
SCS0[3]/D0[1] GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0
P4[21]/
USB_OVRCR2[1] GPIO 4, pin 21 USB_OVRCR2 --
P1[13]/EI3/SCL1/WE 81[1] GPIO 1, pin 13 EXTINT3 I2 C1 SCL EXTBUS WE
P4[5]/A13 82[1] GPIO 4, pin 5 EXTBUS A13 - -
P1[12]/EI2/SDA1/OE 83[1] GPIO 1, pin 12 EXTINT2 I2 C1 SDA EXTBUS OE
P5[5]/D17 84[1] GPIO 5, pin 5 EXTBUS D17 - -
VDD(IO) 85 3.3 V power supply for I/O
P2[2]/MAT2[2]/
TRAP1/D10[1] GPIO 2, pin 2 TIMER2 MAT2 PWM TRAP1 EXTBUS D10
P2[3]/MAT2[3]/
TRAP0/D11[1] GPIO 2, pin 3 TIMER2 MAT3 PWM TRAP0 EXTBUS D11
P1[11]/SCK1/
SCL0/CS3[1] GPIO 1, pin 11 SPI1 SCK I2 C0 SCL EXTBUS CS3
P1[10]/SDI1/
SDA0/CS2[1] GPIO 1, pin 10 SPI1 SDI I2 C0 SDA EXTBUS CS2
P3[12]/SCS1[0]/EI4/
USB_SSPND1[1] GPIO 3, pin 12 SPI1 SCS0 EXTINT4 USB_SSPND1
VSS(CORE) 91 ground for digital core
VDD(CORE) 92 1.8 V power supply for digital core
P3[13]/SDO1/
EI5/IDX0[1] GPIO 3, pin 13 SPI1 SDO EXTINT5 QEI0 IDX
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

P2[4]/MAT1[0]/
EI0/D12[1] GPIO 2, pin 4 TIMER1 MAT0 EXTINT0 EXTBUS D12
P2[5]/MAT1[1]/
EI1/D13[1] GPIO 2, pin 5 TIMER1 MAT1 EXTINT1 EXTBUS D13
P1[9]/SDO1/
RXDL1/CS1[1] GPIO 1, pin 9 SPI1 SDO LIN1 RXD/UART RXD EXTBUS CS1
VSS(IO) 97 ground for I/O
P1[8]/SCS1[0]/
TXDL1/CS0[1] GPIO 1, pin 8 SPI1 SCS0 LIN1 TXD/ UART TXD EXTBUS CS0
P1[7]/SCS1[3]/RXD1/[1] GPIO 1, pin 7 SPI1 SCS3 UART1 RXD EXTBUS A7
P1[6]/SCS1[2]/
TXD1/A6
100[1] GPIO 1, pin 6 SPI1 SCS2 UART1 TXD EXTBUS A6
P2[6]/MAT1[2]/
EI2/D14
101[1] GPIO 2, pin 6 TIMER1 MAT2 EXTINT2 EXTBUS D14
P1[5]/SCS1[1]/
PMAT3[5]/A5
102[1] GPIO 1, pin 5 SPI1 SCS1 PWM3 MAT5 EXTBUS A5
P1[4]/SCS2[2]/
PMAT3[4]/A4
103[1] GPIO 1, pin 4 SPI2 SCS2 PWM3 MAT4 EXTBUS A4
TRST 104[1] IEEE 1149.1 test reset NOT; active LOW; pulled up internally
RST 105[1] asynchronous device reset; active LOW; pulled up internally
VSS(OSC) 106 ground for oscillator
XOUT_OSC 107[3] crystal out for oscillator
XIN_OSC 108[3] crystal in for oscillator
VDD(OSC_PLL) 109 1.8 V supply for oscillator and PLL
VSS(PLL) 110 ground for PLL
P2[7]/MAT1[3]/
EI3/D15
111[1] GPIO 2, pin 7 TIMER1 MAT3 EXTINT3 EXTBUS D15
P3[14]/SDI1/
EI6/TXDC0
112[1] GPIO 3, pin 14 SPI1 SDI EXTINT6 CAN0 TXD
P3[15]/SCK1/
EI7/RXDC0
113[1] GPIO 3, pin 15 SPI1 SCK EXTINT7 CAN0 RXD
VDD(IO) 114 3.3 V power supply for I/O
P2[8]/CLK_OUT/
PMAT0[0]/SCS0[2]
115[1] GPIO 2, pin 8 CLK_OUT PWM0 MAT0 SPI0 SCS2
P2[9]/
USB_UP_LED1/
PMAT0[1]/SCS0[1]
116[1] GPIO 2, pin 9 USB_UP_LED1 PWM0 MAT1 SPI0 SCS1
P1[3]/SCS2[1]/
PMAT3[3]/A3
117[1] GPIO 1, pin 3 SPI2 SCS1 PWM3 MAT3 EXTBUS A3
P1[2]/SCS2[3]/
PMAT3[2]/A2
118[1] GPIO 1, pin 2 SPI2 SCS3 PWM3 MAT2 EXTBUS A2
P1[1]/EI1/PMAT3[1]/
119[1] GPIO 1, pin 1 EXTINT1 PWM3 MAT1 EXTBUS A1
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

VSS(CORE) 120 ground for digital core
VDD(CORE) 121 1.8 V power supply for digital core
P1[0]/EI0/
PMAT3[0]/A0
122[1] GPIO 1, pin 0 EXTINT0 PWM3 MAT0 EXTBUS A0
P2[10]/USB_INT1/
PMAT0[2]/SCS0[0]
123[1] GPIO 2, pin 10 USB_INT1 PWM0 MAT2 SPI0 SCS0
P2[11]/USB_RST1/
PMAT0[3]/SCK0
124[1] GPIO 2, pin 11 USB_RST1 PWM0 MAT3 SPI0 SCK
P0[0]/PHB0/
TXDC0/D24
125[1] GPIO 0, pin 0 QEI0 PHB CAN0 TXD EXTBUS D24
VSS(IO) 126 ground for I/O
P4[13]/BLS1 127[1] GPIO 4, pin 13 EXTBUS BLS1 --
P0[1]/PHA0/
RXDC0/D25
128[1] GPIO 0, pin 1 QEI 0 PHA CAN0 RXD EXTBUS D25
P5[13]/D25 129[1] GPIO 5, pin 13 EXTBUS D25 - -
P0[2]/CLK_OUT/
PMAT0[0]/D26
130[1] GPIO 0, pin 2 CLK_OUT PWM0 MAT0 EXTBUS D26
P4[2]/A10 131[1] GPIO 4, pin 2 EXTBUS A10 - -
VDD(IO) 132 3.3 V power supply for I/O
P5[2]/D10 133[1] GPIO 5, pin 2 EXTBUS D10 - -
P0[3]/
USB_UP_LED1/
PMAT0[1]/D27
134[1] GPIO 0, pin 3 USB_UP_LED1 PWM0 MAT1 EXTBUS D27
P4[18]/
USB_UP_LED2
135[1] GPIO 4, pin 18 USB_UP_LED2 --
P3[0]/IN0[6]/
PMAT2[0]/CS6
136[1] GPIO 3, pin 0 ADC0 IN6 PWM2 MAT0 EXTBUS CS6
P4[10]/OE/CTS1 137[1] GPIO 4, pin 10 EXTBUS OE UART1 CTS -
P3[1]/IN0[7/
PMAT2[1]/CS7
138[1] GPIO 3, pin 1 ADC0 IN7 PWM2 MAT1 EXTBUS CS7
P5[10]/D22/DSR0 139[1] GPIO 5, pin 10 EXTBUS D22 UART0 DSR -
P2[12]/IN0[4]
PMAT0[4]/SDI0
140[1] GPIO 2, pin 12 ADC0 IN4 PWM0 MAT4 SPI0 SDI
VDD(CORE) 141 1.8 V power supply for digital core
VSS(CORE) 142 ground for digital core
P4[22]/
USB_PPWR2
143[1] GPIO 4, pin 22 USB_PPWR2 --
VSS(IO) 144 ground for I/O
P2[13]/IN0[5]/
PMAT0[5]/SDO0
145[1] GPIO 2, pin 13 ADC0 IN5 PWM0 MAT5 SPI0 SDO
P4[6]/A20/RI1 146[1] GPIO 4, pin 6 EXTBUS A20 UART1 RI -
P0[4]/IN0[0]/
PMAT0[2]/D28
147[1] GPIO 0, pin 4 ADC0 IN0 PWM0 MAT2 EXTBUS D28
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

P5[6]/D18/RI0 148[1] GPIO 5, pin 6 EXTBUS D18 UART0 RI -
P4[14]/BLS2 149[1] GPIO 4, pin 14 EXTBUS BLS2 --
P0[5]/IN0[1]/
PMAT0[3]/D29
150[1] GPIO 0, pin 5 ADC0 IN1 PWM0 MAT3 EXTBUS D29
P5[14]/
USB_SSPND1/RTS0
151[1] GPIO 5, pin 14 USB_SSPND1 UART0 RTS -
VDD(IO) 152 3.3 V power supply for I/O
P0[6]/IN0[2]/
PMAT0[4]/D30
153[1] GPIO 0, pin 6 ADC0 IN2 PWM0 MAT4 EXTBUS D30
P0[7]/IN0[3]/
PMAT0[5]/D31
154[1] GPIO 0, pin 7 ADC0 IN3 PWM0 MAT5 EXTBUS D31
VDDA(ADC3V3) 155 3.3 V power supply for ADC
JTAGSEL 156[1] TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan; pulled up internally
VDDA(ADC5V0) 157 5 V supply voltage for ADC0 and 5 V reference for ADC0
VREFP 158[3] HIGH reference for ADC
VREFN 159[3] LOW reference for ADC
P0[8]/IN1[0]/TXDL0/
A20
160[4] GPIO 0, pin 8 ADC1 IN0 LIN0 TXD/ UART TXD EXTBUS A20
P0[9]/IN1[1]/
RXDL0/A21
161[4] GPIO 0, pin 9 ADC1 IN1 LIN0 RXD/ UART TXD EXTBUS A21
P0[10]/IN1[2]/
PMAT1[0]/A8
162[4] GPIO 0, pin 10 ADC1 IN2 PWM1 MAT0 EXTBUS A8
P0[11]/IN1[3]/
PMAT1[1]/A9
163[4] GPIO 0, pin 11 ADC1 IN3 PWM1 MAT1 EXTBUS A9
P2[14]/SDA1/
PCAP0[0]/BLS0
164[1] GPIO 2, pin 14 I2 C1 SDA PWM0 CAP0 EXTBUS BLS0
P2[15]/SCL1/
PCAP0[1]/BLS1
165[1] GPIO 2, pin 15 I2 C1 SCL PWM0 CAP1 EXTBUS BLS1
P3[2]/MAT3[0]/
PMAT2[2]/
USB_SDA1
166[1] GPIO 3, pin 2 TIMER3 MAT0 PWM2 MAT2 USB_SDA1
VDD(CORE) 167 1.8 V power supply for digital core
VSS(CORE) 168 ground for digital core
VSS(IO) 169 ground for I/O
P4[3]/A11 170[1] GPIO 4, pin 3 EXTBUS A11 - -
P3[3]/MAT3[1]/
PMAT2[3]/
USB_SCL1
171[1] GPIO 3, pin 3 TIMER3 MAT1 PWM2 MAT3 USB_SCL1
P5[3]/D11 172[1] GPIO 5, pin 3 EXTBUS D11 - -
P0[12]/IN1[4]/
PMAT1[2]/A10
173[4] GPIO 0, pin 12 ADC1 IN4 PWM1 MAT2 EXTBUS A10
P4[19]/
USB_CONNECT2
174[1] GPIO 4, pin 19 USB_CONNECT2 --
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

P0[13]/IN1[5]/
PMAT1[3]/A11
175[4] GPIO 0, pin 13 ADC1 IN5 PWM1 MAT3 EXTBUS A11
VDD(IO) 176 3.3 V power supply for I/O
P4[11]/WE/CTS0 177[1] GPIO 4, pin 11 EXTBUS WE UART0 CTS -
P0[14]/IN1[6]/
PMAT1[4]/A12
178[4] GPIO 0, pin 14 ADC1 IN6 PWM1 MAT4 EXTBUS A12
P5[11]/D23/DCD0 179[1] GPIO 5, pin 11 EXTBUS D23 UART0 DCD -
P0[15]/IN1[7]/
PMAT1[5]/A13
180[4] GPIO 0, pin 15 ADC1 IN7 PWM1 MAT5 EXTBUS A13
P4[23]/
USB_PWRD2
181[1] GPIO 4, pin 23 USB_PWRD2 --
P0[16]IN2[0]/
TXD0/A22
182[4] GPIO 0, pin 16 ADC2 IN0 UART0 TXD EXTBUS A22
P4[7]/A21/DTR1 183[1] GPIO 4, pin 7 EXTBUS A21 UART1 DTR -
VSS(IO) 184 ground for I/O
P5[7]/D19/
U0OUT1
185[1] GPIO 5, pin 7 EXTBUS D19 UART0 OUT1 -
P0[17]/IN2[1]/
RXD0/A23
186[4] GPIO 0, pin 17 ADC2 IN1 UART0 RXD EXTBUS A23
P4[15]/BLS3 187[1] GPIO 4, pin 15 EXTBUS BLS3 --
P5[15]/
USB_UP_LED1/
RTS1
188[1] GPIO 5, pin 15 USB_UP_LED1 UART1 RTS -
VDD(CORE) 189 1.8 V power supply for digital core
VSS(CORE) 190 ground for digital core
P2[16]/TXD1/
PCAP0[2]/BLS2
191[1] GPIO 2, pin 16 UART1 TXD PWM0 CAP2 EXTBUS BLS2
P2[17]/RXD1/
PCAP1[0]/BLS3
192[1] GPIO 2, pin 17 UART1 RXD PWM1 CAP0 EXTBUS BLS3
VDD(IO) 193 3.3 V power supply for I/O
P0[18]/IN2[2]/
PMAT2[0]/A14
194[4] GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14
P0[19]/IN2[3]/
PMAT2[1]/A15
195[4] GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15
P3[4]/MAT3[2]/
PMAT2[4]/
TXDC1
196[1] GPIO 3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TXD
P3[5]/MAT3[3]/
PMAT2[5]/
RXDC1
197[1] GPIO 3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RXD
P2[18]/SCS2[1]/
PCAP1[1]/D16
198[1] GPIO 2, pin 18 SPI2 SCS1 PWM1 CAP1 EXTBUS D16
P2[19]/SCS2[0]/
PCAP1[2]/D17
199[1] GPIO 2, pin 19 SPI2 SCS0 PWM1 CAP2 EXTBUS D17
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

[1] Bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5 V tolerant; TTL with hysteresis; programmable pull-up /
pull-down / repeater.
[2] USB pad.
[3] Analog pad; Analog I/O.
[4] Analog I/O pad.
P0[20]/IN2[4]/
PMAT2[2]/A16
200[4] GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16
P0[21]/IN2[5]/
PMAT2[3]/A17
201[4] GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17
P0[22]/IN2[6]/
PMAT2[4]/A18
202[4] GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18
VSS(IO) 203 ground for I/O
P0[23]/IN2[7]/
PMAT2[5]/A19
204[4] GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19
P2[20]/
PCAP2[0]/D18
205[1] GPIO 2, pin 20 SPI2 SDO PWM2 CAP0 EXTBUS D18
VDD(CORE) 206 1.8 V power supply for digital core
VSS(CORE) 207 ground for digital core
TDI 208[1] IEEE 1149.1 data in, pulled up internally
Table 3. LQFP208 pin assignment …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6. Functional description
6.1 Architectural overview

The LPC2939 consists of: An ARM968E-S processor with real-time emulation support An AMBA multilayer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control SubSystem (PCRSS) Three ARM Peripheral Buses (APB - a compatible super set of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems One ARM Peripheral Bus for event router and system control
The LPC2939 configures the ARM968E-S processor in little-endian byte order. All
peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB-to-APB bridge used in the subsystems contains a write-ahead
buffer one transaction deep. This implies that when the ARM968E-S issues a buffered
write action to a register located on the APB side of the bridge, it continues even though
the actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
6.2 ARM968E-S processor

The ARM968E-S is a general purpose 32-bit RISC processor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective controller
core.
Amongst the most compelling features of the ARM968E-S are: Separate directly connected instruction and data Tightly Coupled Memory (TCM)
interfaces Write buffers for the AHB and TCM buses Enhanced 16  32 multiplier capable of single-cycle MAC operations and 16-bit fixed-
point DSP instructions to accelerate signal-processing algorithms and applications
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline
architecture. Typically, in a three-stage pipeline architecture, while one instruction is being
executed its successor is being decoded and a third instruction is being fetched from
memory. In the five-stage pipeline additional stages are added for memory access and
write-back cycles.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

The ARM968E-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions or to applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM968E-S processor has two instruction sets: Standard 32-bit ARMv5TE set 16-bit THUMB set
The THUMB set's 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM's performance advantage over a
traditional 16-bit controller using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM controller connected to a 16-bit memory system.
The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref.2.
6.3 On-chip flash memory system

The LPC2939 includes a 768 kB flash memory system. This memory can be used for both
code and data storage. Programming of the flash memory can be accomplished via the
flash memory controller or the JTAG.
The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated
on the LPC2939.
6.4 On-chip static RAM

In addition to the two 32 kB TCMs the LPC2939 includes two static RAM memories: one
of 32 kB and one of 16 kB. Both may be used for code and/or data storage.
In addition, 8 kB SRAM for the ETB can be used as static memory for code and data
storage. However, DMA access to this memory region is not supported.
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NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
emory map
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.6 Reset, debug, test, and power description
6.6.1 Reset and power-up behavior

The LPC2939 contains external reset input and internal power-up reset circuits. This
ensures that a reset is extended internally until the oscillators and flash have reached a
stable state. See Section 8 for trip levels of the internal power-up reset circuit1 . See
Section 9 for characteristics of the several start-up and initialization times. Table 4 shows
the reset pin.
At activation of the RST pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2939 is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
6.6.2 Reset strategy

The LPC2939 contains a central module, the Reset Generator Unit (RGU) in the Power,
Clock and Reset Subsystem (PCRSS), which controls all internal reset signals towards
the peripheral modules. The RGU provides individual reset control as well as the
monitoring functions needed for tracing a reset back to source.
6.6.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)

The LPC2939 contains boundary-scan test logic according to IEEE 1149.1, also referred
to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can
be used to connect a debugger probe for the embedded ARM processor. Pin JTAGSEL
selects between boundary-scan mode and debug mode. Table 5 shows the boundary-
scan test pins. Only for 1.8 V power sources
Table 4. Reset pin

RST IN external reset input, active LOW; pulled up internally
Table 5. IEEE 1149.1 boundary-scan test and debug interface

JTAGSEL TAP controller select input. LOW level selects ARM debug mode and HIGH level selects boundary scan and flash programming; pulled up internally
TRST test reset input; pulled up internally (active LOW)
TMS test mode select input; pulled up internally
TDI test data input, pulled up internally
TDO test data output
TCK test clock input
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.6.3.1 ETM/ETB

The ETM provides real-time trace capability for deeply embedded processor cores. It
outputs information about processor execution to a trace buffer. A software debugger
allows configuration of the ETM using a JTAG interface and displays the trace information
that has been captured in a format that a user can easily understand. The ETB stores
trace data produced by the ETM.
The ETM/ETB module has the following features: Closely tracks the instructions that the ARM core is executing On-chip trace data storage (ETB) All registers are programmed through JTAG interface Does not consume power when trace is not being used THUMB/Java instruction set support
6.6.4 Power supply pins

Table 6 shows the power supply pins.
6.7 Clocking strategy
6.7.1 Clock architecture

The LPC2939 contains several different internal clock areas. Peripherals like Timers, SPI,
UART, CAN and LIN have their own individual clock sources called base clocks. All base
clocks are generated by the Clock Generator Unit (CGU0). They may be unrelated in
frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Bus infrastructure has its own base clock. This
means most peripherals are clocked independently from the system clock. See Figure4
for an overview of the clock areas within the device.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. See Section 6.16 for
more details of clock and power control within the device.
Table 6. Power supply pins

VDD(CORE) digital core supply 1.8V
VSS(CORE) digital core ground (digital core, ADC0/1/2)
VDD(IO) I/O pins supply 3.3V
VSS(IO) I/O pins ground
VDD(OSC_PLL) oscillator and PLL supply
VSS(OSC) oscillator ground
VSS(PLL) PLL ground
VDDA(ADC3V3) ADC1 and ADC2 3.3 V supply
VDDA(ADC5V0) ADC0 5.0 V supply
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

Two of the base clocks generated by the CGU0 are used as input into a second,
dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate
two base clocks for the USB controller and one base clock for an independent clock
output.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.7.2 Base clock and branch clock relationship

Table 7 contains an overview of all the base blocks in the LPC2939 and their derived
branch clocks. A short description is given of the hardware parts that are clocked with the
individual branch clocks. In relevant cases more detailed information can be found in the
specific subsystem description. Some branch clocks have special protection since they
clock vital system parts of the device and should not be switched off. See Section 6.16.5
for more details of how to control the individual branch clocks. Table 7. CGU0 base clock and branch clock overview
BASE_SAFE_CLK CLK_SAFE watchdog timer [1]
BASE_SYS_CLK CLK_SYS_CPU ARM968E-S and TCMs
CLK_SYS_SYS AHB bus infrastructure
CLK_SYS_PCRSS AHB side of bridge in PCRSS
CLK_SYS_FMC flash memory controller
CLK_SYS_RAM0 embedded SRAM controller 0 (32 kB)
CLK_SYS_RAM1 embedded SRAM controller 1 (16 kB)
CLK_SYS_SMC external Static Memory Controller
(SMC)
CLK_SYS_GESS General SubSystem (GESS)
CLK_SYS_VIC Vectored Interrupt Controller (VIC)
CLK_SYS_PESS Peripheral SubSystem (PESS) [2][4]
CLK_SYS_GPIO0 GPIO bank 0
CLK_SYS_GPIO1 GPIO bank 1
CLK_SYS_GPIO2 GPIO bank 2
CLK_SYS_GPIO3 GPIO bank 3
CLK_SYS_GPIO4 GPIO bank 4
CLK_SYS_GPIO5 GPIO bank 5
CLK_SYS_IVNSS_A AHB side of bridge of IVNSS
CLK_SYS_MSCSS_A AHB side of bridge of MSCSS
CLK_SYS_DMA GPDMA
CLK_SYS_USB USB registers
BASE_PCR_CLK CLK_PCR_SLOW PCRSS, CGU, RGU and PMU logic
clock
[1][3]
BASE_IVNSS_CLK CLK_IVNSS_APB APB side of the IVNSS
CLK_IVNSS_CANCA CAN controller Acceptance Filter
CLK_IVNSS_CANC0 CAN channel 0
CLK_IVNSS_CANC1 CAN channel 1
CLK_IVNSS_I2C0 I2C0
CLK_IVNSS_I2C1 I2C1
CLK_IVNSS_LIN0 LIN channel 0
CLK_IVNSS_LIN1 LIN channel 1
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

[1] This clock is always on (cannot be switched off for system safety reasons).
[2] In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock
source. See Section 6.13 for details.
[3] In the Power Clock and Reset Control subsystem parts of the CGU, RGU, and PMU have their own clock
source. See Section 6.16 for details.
[4] The clock should remain activated when system wake-up on timer or UART is required.
BASE_MSCSS_CLK CLK_MSCSS_APB APB side of the MSCSS
CLK_MSCSS_MTMR0 timer 0 in the MSCSS
CLK_MSCSS_MTMR1 timer 1 in the MSCSS
CLK_MSCSS_PWM0 PWM 0
CLK_MSCSS_PWM1 PWM 1
CLK_MSCSS_PWM2 PWM 2
CLK_MSCSS_PWM3 PWM 3
CLK_MSCSS_ADC0_APB APB side of ADC 0
CLK_MSCSS_ADC1_APB APB side of ADC 1
CLK_MSCSS_ADC2_APB APB side of ADC 2
CLK_MSCSS_QEI Quadrature Encoder Interface (QEI)
BASE_UART_CLK CLK_UART0 UART 0 interface clock
CLK_UART1 UART 1 interface clock
BASE_ICLK0_CLK - CGU1 input clock
BASE_SPI_CLK CLK_SPI0 SPI 0 interface clock
CLK_SPI1 SPI 1 interface clock
CLK_SPI2 SPI 2 interface clock
BASE_TMR_CLK CLK_TMR0 timer 0 clock for counter part
CLK_TMR1 timer 1 clock for counter part
CLK_TMR2 timer 2 clock for counter part
CLK_TMR3 timer 3 clock for counter part
BASE_ADC_CLK CLK_ADC0 control of ADC 0, capture sample
result
CLK_ADC1 control of ADC 1, capture sample
result
CLK_ADC2 control of ADC 2, capture sample
result reserved -
BASE_ICLK1_CLK - CGU1 input clock
Table 8. CGU1 base clock and branch clock overview

BASE_OUT_CLK CLK_OUT_CLK pin CLK_OUT
BASE_USB_CLK CLK_USB_CLK USB clock
BASE_USB_I2C_CLK CLK_USB_I2C_CLK USB OTG I2 C clock
Table 7. CGU0 base clock and branch clock overview …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.8 Flash memory controller

The flash memory has a 128-bit wide data interface and the flash controller offers two
128-bit buffer lines to improve system performance. The flash has to be programmed
initially via JTAG. In-system programming must be supported by the bootloader. Flash
memory contents can be protected by disabling JTAG access. Suspension of burning or
erasing is not supported.
The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two
tasks: Memory data transfer Memory configuration via triggering, programming, and erasing
The key features are: Programming by CPU via AHB Programming by external programmer via JTAG JTAG access protection Burn-finished and erase-finished interrupt
6.8.1 Functional description

After reset flash initialization is started. During this initialization, flash access is not
possible and AHB transfers to flash are stalled, blocking the AHB bus.
During flash initialization, the index sector is read to identify the status of the JTAG access
protection and sector security. If JTAG access protection is active, the flash is not
accessible via JTAG. In this case, ARM debug facilities are disabled and flash-memory
contents cannot be read. If sector security is active, only the unsecured sections can be
read.
Flash can be read synchronously or asynchronously to the system clock. In synchronous
operation, the flash goes into standby after returning the read data. Started reads cannot
be stopped, and speculative reading and dual buffering are therefore not supported.
With asynchronous reading, transfer of the address to the flash and of read data from the
flash is done asynchronously, giving the fastest possible response time. Started reads can
be stopped, so speculative reading and dual buffering are supported.
Buffering is offered because the flash has a 128-bit wide data interface while the AHB
interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash
word, from which four words can be read. Without buffering every AHB data port read
starts a flash read. A flash read is a slow process compared to the minimum AHB cycle
time, so with buffering the average read time is reduced improving system performance.
With single buffering, the most recently read flash word remains available until the next
flash read. When an AHB data-port read transfer requires data from the same flash word
as the previous read transfer, no new flash read is done and the read data is given without
wait cycles.
When an AHB data port read transfer requires data from a different flash word to that
involved in the previous read transfer, a new flash read is done and wait states are given
until the new read data is available.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

With dual buffering, a secondary buffer line is used, the output of the flash being
considered as the primary buffer. On a primary buffer, hit data can be copied to the
secondary buffer line, which allows the flash to start a speculative read of the next flash
word.
Both buffer lines are invalidated after: Initialization Configuration-register access Data-latch reading Index-sector reading
The modes of operation are listed in Table9.
6.8.2 Flash layout

The ARM processor can program the flash for ISP (In-System Programming) through the
flash memory controller. Note that the flash always has to be programmed by ‘flash words’
of 128 bits (four 32-bit AHB bus words, hence 16 bytes).
The flash memory is organized into eight ‘small’ sectors of 8 kB each and up to 11 ‘large’
sectors of 64 kB each. The number of large sectors depends on the device type. A sector
must be erased before data can be written to it. The flash memory also has sector-wise
protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small
sector contains 16 pages; a large sector contains 128 pages.
Table 10 gives an overview of the flash-sector base addresses.
Table 9. Flash read modes
Synchronous timing

No buffer line for single (non-linear) reads; one flash-word read per word read
Single buffer line default mode of operation; most recently read flash word is kept until
another flash word is required
Asynchronous timing

No buffer line one flash-word read per word read
Single buffer line most recently read flash word is kept until another flash word is
required
Dual buffer line, single
speculative
on a buffer miss a flash read is done, followed by at most one
speculative read; optimized for execution of code with small loops
(less than eight words) from flash
Dual buffer line, always
speculative
most recently used flash word is copied into second buffer line; next
flash-word read is started; highest performance for linear reads
Table 10. Flash sector overview
8 0x2000 0000 8 0x2000 2000 8 0x2000 4000 8 0x2000 6000 8 0x2000 8000
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

The index sector is a special sector in which the JTAG access protection and sector
security are located. The address space becomes visible by setting the FS_ISS bit and
overlaps the regular flash sector’s address space.
Note that the index sector, once programmed, cannot be erased. Any flash operation must
be executed out of SRAM (internal or external).
6.8.3 Flash bridge wait-states

To eliminate the delay associated with synchronizing flash-read data, a predefined
number of wait-states must be programmed. These depend on flash-memory response
time and system clock period. The minimum wait-states value can be calculated with the
following formulas:
Synchronous reading:
(1)
Asynchronous reading:
(2)
Remark: If the programmed number of wait-states (WST) is more than three, flash-data

reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if
speculative reading is active.
6.8.4 Pin description

The flash memory controller has no external pins. However, the flash can be programmed
via the JTAG pins, see Section 6.6.3. 8 0x2000 A000 8 0x2000 C000 8 0x2000 E000 64 0x2001 0000 64 0x2002 0000 64 0x2003 0000 64 0x2004 0000 64 0x2005 0000 64 0x2006 0000 64 0x2007 0000 64 0x2008 0000 64 0x2009 0000 64 0x200A 0000 64 0x200B 0000
Table 10. Flash sector overview …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.8.5 Clock description

The flash memory controller is clocked by CLK_SYS_FMC, see Section 6.7.2.
6.8.6 EEPROM

EEPROM is a non-volatile memory mostly used for storing relatively small amounts of
data, for example for storing settings. It contains one 16 kB memory block and is
byte-programmable and byte-erasable.
The EEPROM can be accessed only through the flash controller.
6.9 External Static Memory Controller (SMC)

The LPC2939 contains an external Static Memory Controller (SMC) which provides an
interface for external (off-chip) memory devices.
Key features are: Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices Asynchronous page-mode read operation in non-clocked memory subsystems Asynchronous burst-mode read access to burst-mode ROM devices Independent configuration for up to eight banks, each up to 16 MB Programmable bus-turnaround (idle) cycles (one to 16) Programmable read and write wait states (up to 32), for static RAM devices Programmable initial and subsequent burst-read wait state for burst-ROM devices Programmable write protection Programmable burst-mode operation Programmable external data width: 8 bit, 16 bit, or 32 bit Programmable read-byte lane enable control
6.9.1 Description

The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting
SRAM, ROM, burst-ROM memory, or external I/O devices.
A separate chip select output is available for each bank. The chip select lines are
configurable to be active HIGH or LOW. Memory bank selection is controlled by memory
addressing. Table 11 shows how the 32-bit system address is mapped to the external bus
memory base addresses, chip selects, and bank internal addresses.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

6.9.2 Pin description

The external static-memory controller module in the LPC2939 has the following pins,
which are combined with other functions on the port pins of the LPC2939. Table 13 shows
the external memory controller pins.
6.9.3 Clock description

The external Static Memory Controller is clocked by CLK_SYS_SMC, see Section 6.7.2.
6.9.4 External memory timing diagrams

A timing diagram for reading from external memory is shown in Figure 5. The relationship
between the wait state settings is indicated with arrows.
Table 11. External memory bank address bit description

31 to 29 BA[2:0] external static memory base address (three most significant bits);
the base address can be found in the memory map; see Ref. 1. This
field contains ‘010’ when addressing an external memory bank.
28 to 26 CS[2:0] chip select address space for eight memory banks; see Ref.1
25 and 24 - always ‘00’; other values are ‘mirrors’ of the 16 MB bank address
23 to 0 A[23:0] 16 MB memory banks address space
Table 12. External static memory controller banks

000 bank0
001 bank1
010 bank2
011 bank3
100 bank4
101 bank5
110 bank6
111 bank7
Table 13. External memory controller pins

EXTBUS CSx CSx OUT memory bank x select, x runs from 0 to 7
EXTBUS BLSyBLSy OUT byte lane select input y, y runs from 0 to 3
EXTBUS WE WE OUT write enable (active LOW)
EXTBUS OE OE OUT output enable (active LOW)
EXTBUS A[23:0] A[23:0] OUT address bus
EXTBUS D[31:0] D[31:0] IN/OUT data bus
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

A timing diagram for writing to external memory is shown In Figure 6. The relationship
between wait state settings is indicated with arrows.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

Usage of the idle/turn-around time (IDCY) is demonstrated In Figure 7. Extra wait states
are added between a read and a write cycle in the same external memory device.
Address pins on the device are shared with other functions. When connecting external
memories, check that the I/O pin is programmed for the correct function. Control of these
settings is handled by the SCU.
6.10 General Purpose DMA (GPDMA) controller

The GPDMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the same AHB master or one area by each master.
The GPDMA controls eight DMA channels with hardware prioritization. The DMA
controller interfaces to the system via two AHB bus masters, each with a full 32-bit data
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.10.2 Clock description

The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see
Section 6.7.2.
6.11 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic
configuration of the devices. All transactions are initiated by the Host controller.
The LPC2939 USB interface includes a device and OTG controller with on-chip PHY for
device. The OTG switching protocol is supported through the use of an external controller.
Details on typical USB interfacing solutions can be found in Section 10.2.
6.11.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the on-chip
SRAM.
The USB device controller has the following features: Fully compliant with USB 2.0 specification (full speed) Supports 32 physical (16 logical) endpoints with a 2 kB endpoint buffer RAM Supports Control, Bulk, Interrupt and Isochronous endpoints Scalable realization of endpoints at run time Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time Supports SoftConnect and GoodLink features While USB is in the Suspend mode, the LPC2939 can enter the Power-down mode
and wake up on USB activity Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints Allows dynamic switching between CPU-controlled slave and DMA modes Double buffer implementation for Bulk and Isochronous endpoints
6.11.2 USB OTG controller

USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals.
The OTG Controller integrates the device controller, and a master-only I2 C interface to
implement OTG dual-role device functionality. The dedicated I2 C interface controls an
external OTG transceiver.
The USB OTG controller has the following features:
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a Hardware support for Host Negotiation Protocol (HNP) Includes a programmable timer required for HNP and Session Request Protocol
(SRP) Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0
6.11.3 USB host controller

The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the OHCI specification.
6.11.3.1 Features
OHCI compliant Two downstream ports Supports per-port power switching
6.11.4 Pin description
Table 14. USB OTG port pins
Port 1

USB_VBUS1 I VBUS status input. When this function is not enabled
via its corresponding PINSEL register, it is driven
HIGH internally.
USB_D+1 I/O positive differential data -
USB_D1 I/O negative differential data -
USB_CONNECT1 O SoftConnect control signal -
USB_UP_LED1 O GoodLink LED control signal -
USB_SCL1 I/O I 2C serial clock external OTG transceiver
USB_SDA1 I/O I 2C serial data external OTG transceiver
USB_LS1 O low-speed status (applies to host functionality only) external OTG transceiver
USB_RST1 O USB reset status external OTG transceiver
USB_INT1 O USB transceiver interrupt external OTG transceiver
USB_SSPND1 O bus suspend status external OTG transceiver
USB_PWRD1 I port power status USB host
USB_PPWR1 O port power enable USB host
USB_OVRCR1 I over-current status USB host
Port 2

USB_VBUS2 I VBUS status input. When this function is not enabled via its corresponding PINSEL register, it is driven
HIGH internally.
USB_D+2 I/O positive differential data -
USB_D2 I/O negative differential data -
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.11.5 Clock description

Access to the USB registers is clocked by the CLK_SYS_USB, derived from
BASE_SYS_CLK, see Section 6.7.2. The CGU1 provides two independent base clocks to
the USB block, BASE_USB_CLK and BASE_USB_I2C_CLK (see Section 6.16.3).
6.12 General subsystem
6.12.1 General subsystem clock description

The general subsystem is clocked by CLK_SYS_GESS, see Section 6.7.2.
6.12.2 Chip and feature identification

The Chip/Feature ID (CFID) module contains registers which show and control the
functionality of the chip. It contains an ID to identify the silicon and also registers
containing information about the features enabled or disabled on the chip.
The key features are: Identification of product Identification of features enabled
The CFID has no external pins.
6.12.3 System Control Unit (SCU)

The system control unit contains system related functions.The key feature is configuration
of the I/O port pins multiplexer. It defines the function of each I/O pin of the LPC2939. The
I/O pin configuration should be consistent with peripheral function usage.
The SCU has no external pins.
6.12.4 Event router

The event router provides bus-controlled routing of input events to the vectored interrupt
controller for use as interrupt or wake-up signals.
Key features: Up to 22 level-sensitive external interrupt pins, including the receive pins of SPI, CAN,
LIN, USB, and UART, as well as the I2 C-bus SCL pins plus three internal event
sources Input events can be used as interrupt source either directly or latched (edge-detected) Direct events disappear when the event becomes inactive Latched events remain active until they are explicitly cleared
USB_CONNECT2 O SoftConnect control signal -
USB_UP_LED2 O GoodLink LED control signal -
USB_PWRD2 I port power status USB host
USB_PPWR2 O port power enable USB host
USB_OVRCR2 I over-current status USB host
Table 14. USB OTG port pins …continued
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Programmable input level and edge polarity Event detection maskable Event detection is fully asynchronous, so no clock is required
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
The vectored interrupt controller inputs are active HIGH.
6.12.4.1 Pin description

The event router module in the LPC2939 is connected to the pins listed below. The pins
are combined with other functions on the port pins of the LPC2939. Table 15 shows the
pins connected to the event router and three additional internal signals.
6.13 Peripheral subsystem
6.13.1 Peripheral subsystem clock description

The peripheral subsystem is clocked by a number of different clocks: CLK_SYS_PESS CLK_UART0/1 CLK_SPI0/1/2 CLK_TMR0/1/2/3 CLK_SAFE (see Section 6.7.2)
Table 15. Event-router pin connections

EXTINT[7:0] I external interrupt inputs 7 to 0 1
CAN0 RXD I CAN0 receive data input wake-up 0
CAN1 RXD I CAN1 receive data input wake-up 02 C0 SCL I I2 C0 SCL clock input 02 C1 SCL I I2 C1 SCL clock input 0
LIN0 RXD I LIN0 receive data input wake-up 0
LIN1 RXD I LIN1 receive data input wake-up 0
SPI0 SDI I SPI0 receive data input 0
SPI1 SDI I SPI1 receive data input 0
SPI2 SDI I SPI2 receive data input 0
UART0 RXD I UART0 receive data input 0
UART1 RXD I UART1 receive data input 0
USB_SCL1 I USB I2 C serial clock 0 n/a CAN interrupt (internal) 1 n/a VIC FIQ (internal) 1 n/a VIC IRQ (internal) 1
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.13.2 Watchdog timer

The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features: Internal chip reset if not periodically triggered Timer counter register runs on always-on safe clock Optional interrupt generation on watchdog time-out Debug mode with disabling of reset Watchdog control register change protected with key Programmable 32-bit watchdog timer period with programmable 32-bit prescaler
6.13.2.1 Functional description

The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out, it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog overflow interrupt can be cleared by writing to
the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the watchdog timer control register is set.
The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains
a reset source register to identify the reset source when the device has gone through a
reset. See Section 6.16.4.
6.13.2.2 Clock description

The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE,
see Section 6.7.2. The register interface towards the system bus is clocked by
CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is
always on.
6.13.3 Timer

The LPC2939 contains six identical timers: four in the peripheral subsystem and two in the
Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral
base addresses. This section describes the four timers in the peripheral subsystem. Each
timer has four capture inputs and/or match outputs. Connection to device pins depends on
the configuration programmed into the port function-select registers. The two timers
located in the MSCSS have no external capture or match pins, but the memory map is
identical, see Section 6.15.6. One of these timers has an external input for a pause
function.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

The key features are: 32-bit timer/counter with programmable 32-bit prescaler Up to four 32-bit capture channels per timer. These take a snapshot of the timer value
when an external signal connected to the TIMERx CAPn input changes state. A
capture event may also optionally generate an interrupt. Four 32-bit match registers per timer that allow: Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs per timer corresponding to match registers, with the
following capabilities: Set LOW on match Set HIGH on match Toggle on match Do nothing on match Pause input pin (MSCSS timers only)
The timers are designed to count cycles of the clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers. They also
include capture inputs to trap the timer value when an input signal changes state,
optionally generating an interrupt. The core function of the timers consists of a 32 bit
prescale counter triggering the 32 bit timer counter. Both counters run on clock
CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this
clock. Note that each timer has its individual clock source within the Peripheral
SubSystem. In the Modulation and Sampling SubSystem each timer also has its own
individual clock source. See Section 6.16.5 for information on generation of these clocks.
6.13.3.1 Pin description

The four timers in the peripheral subsystem of the LPC2939 have the pins described
below. The two timers in the modulation and sampling subsystem have no external pins
except for the pause pin on MSCSS timer 1. See Section 6.15.6 for a description of these
timers and their associated pins. The timer pins are combined with other functions on the
port pins of the LPC2939, see Section 6.12.3. Table 16 shows the timer pins (x runs from
0 to 3). Table 16. Timer pins
TIMERx CAP[0] CAPx[0] IN TIMER x capture input0
TIMERx CAP[1] CAPx[1] IN TIMER x capture input1
TIMERx CAP[2] CAPx[2] IN TIMER x capture input2
TIMERx CAP[3] CAPx[3] IN TIMER x capture input3
TIMERx MAT[0] MATx[0] OUT TIMER x match output0
TIMERx MAT[1] MATx[1] OUT TIMER x match output1
TIMERx MAT[2] MATx[2] OUT TIMER x match output2
TIMERx MAT[3] MATx[3] OUT TIMER x match output3
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.13.3.2 Clock description

The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx
(x = 0 to 3), see Section 6.7.2. Note that each timer has its own CLK_TMRx branch clock
for power management. The frequency of all these clocks is identical as they are derived
from the same base clock BASE_CLK_TMR. The register interface towards the system
bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by
CLK_TMRx.
6.13.4 UARTs

The LPC2939 contains two identical UARTs located at different peripheral base
addresses. The key features are: 16-byte receive and transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes Built-in baud rate generator Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode Both UARTs equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS)
The UART is commonly used to implement a serial interface such as RS232. The
LPC2939 contains two industry-standard 550 UARTs with 16-byte transmit and receive
FIFOs, but they can also be put into 450 mode without FIFOs.
Remark: The LIN controller can be configured to provide two additional standard UART

interfaces (see Section 6.14.2).
6.13.4.1 Pin description

The UART pins are combined with other functions on the port pins of the LPC2939.
Table 17 shows the UART pins (x runs from 0 to 1). Table 17. UART pins
UARTx TXD TXDx OUT UART channel x transmit data output
UARTx RXD RXDx IN UART channel x receive data input
UARTx CTS CTSx IN UART channel x Clear To Send (modem)
UARTx DCD DCDx IN UART channel x Data Carrier Detect (modem)
UARTx DSR DSRx IN UART channel x Data Set Ready (modem)
UARTx DTR DTRx OUT UART channel x Data Terminal Ready
(modem)
UARTx RI RIx IN UART Ring Indicator (modem)
UARTx RTS RTSx OUT UART Request To Send (modem)
UARTx OUT1 UxOUT1 OUT UART channel x user designated output 1
UARTx OUT2 UxOUT2 OUT UART channel x user designated output 2
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.13.4.2 Clock description

The UART modules are clocked by two different clocks; CLK_SYS_PESS and
CLK_UARTx (x = 0 to 1), see Section 6.7.2. Note that each UART has its own
CLK_UARTx branch clock for power management. The frequency of all CLK_UARTx
clocks is identical since they are derived from the same base clock BASE_CLK_UART.
The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud
generator is clocked by the CLK_UARTx.
6.13.5 Serial peripheral interface (SPI)

The LPC2939 contains three Serial Peripheral Interface modules (SPIs) to allow
synchronous serial communication with slave or master peripherals.
The key features are: Master or slave operation Each SPI supports up to four slaves in sequential multi-slave operation Supports timer-triggered operation Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep Programmable choice of interface operation: Motorola SPI or Texas Instruments
Synchronous Serial Interfaces Programmable data-frame size from 4 to 16 bits Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts Serial clock-rate master mode: fserial_clk  fclk(SPI) / 2 Serial clock-rate slave mode: fserial_clk = fclk(SPI) / 4 Internal loopback test mode
The SPI module can operate in: Master mode: Normal transmission mode Sequential slave mode Slave mode
6.13.5.1 Functional description

The SPI module is a master or slave interface for synchronous serial communication with
peripheral devices that have either Motorola SPI or Texas Instruments Synchronous
Serial Interfaces.
The SPI module performs serial-to-parallel conversion on data received from a peripheral
device. The transmit and receive paths are buffered with FIFO memories (16 bits wide 
32 words deep). Serial data is transmitted on pins SDOx and received on pins SDIx.
The SPI module includes a programmable bit-rate clock divider and prescaler to generate
the SPI serial clock from the input clock CLK_SPIx.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

The SPI module’s operating mode, frame format, and word size are programmed through
the SLVn_SETTINGS registers.
A single combined interrupt request SPI_INTREQ output is asserted if any of the
interrupts are asserted and unmasked.
Depending on the operating mode selected, the SPI SCS outputs operate as an
active-HIGH frame synchronization output for Texas Instruments synchronous serial
frame format or an active-LOW chip select for SPI.
Each data frame is between four and 16 bits long, depending on the size of words
programmed, and is transmitted starting with the MSB.
6.13.5.2 Pin description

The SPI pins are combined with other functions on the port pins of the LPC2939, see
Section 6.12.3. Table 18 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3).
[1] Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in
master mode, input in slave mode.
[2] In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in
slave mode.
6.13.5.3 Clock description

The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx = 0, 1, 2), see Section 6.7.2. Note that each SPI has its own CLK_SPIx branch clock for
power management. The frequency of all clocks CLK_SPIx is identical as they are derived
from the same base clock BASE_CLK_SPI. The register interface towards the system bus
is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.
The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock
frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the
interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on
the interface.
6.13.6 General-Purpose I/O (GPIO)

The LPC2939 contains six general-purpose I/O ports located at different peripheral base
addresses. In the 208-pin package all six ports are available. All I/O pins are bidirectional,
and the direction can be programmed individually. The I/O pad behavior depends on the
configuration programmed in the port function-select registers.
The key features are: General-purpose parallel inputs and outputs Direction control of individual bits Synchronized input sampling for stable input data values
Table 18. SPI pins

SPIx SCSy SCSx[y] IN/OUT SPIx chip select[1][2]
SPIx SCK SCKx IN/OUT SPIx clock[1]
SPIx SDI SDIx IN SPIx data input
SPIx SDO SDOx OUT SPIx data output
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
All I/O pins default to input at reset to avoid any possible bus conflicts
6.13.6.1 Functional description

The general-purpose I/O provides individual control over each bidirectional port pin. There
are two registers to control I/O direction and output level. The inputs are synchronized to
achieve stable read levels.
To generate an open-drain output, set the bit in the output register to the desired value.
Use the direction register to control the signal. When set to output, the output driver
actively drives the value on the output; when set to input the signal floats and can be
pulled up internally or externally.
6.13.6.2 Pin description

The six GPIO ports in the LPC2939 have the pins listed below. The GPIO pins are
combined with other functions on the port pins of the LPC2939. Table 19 shows the GPIO
pins.
6.13.6.3 Clock description

The GPIO modules are clocked by several clocks, all of which are derived from
BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0, 1, 2, 3, 4, 5), see
Section 6.7.2. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for
power management. The frequency of all clocks CLK_SYS_GPIOx is identical to
CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.
6.14 Networking subsystem
6.14.1 CAN gateway

Controller Area Network (CAN) is the definition of a high-performance communication
protocol for serial data communication. The two CAN controllers in the LPC2939 provide a
full implementation of the CAN protocol according to the CAN specification version 2.0B.
The gateway concept is fully scalable with the number of CAN controllers, and always
operates together with a separate powerful and flexible hardware acceptance filter.
The key features are: Supports 11-bit as well as 29-bit identifiers Double receive buffer and triple transmit buffer Programmable error-warning limit and error counters with read/write access Arbitration-lost capture and error-code capture with detailed bit position Single-shot transmission (i.e. no re-transmission)
Table 19. GPIO pins

GPIO0 pin[31:0] P0[31:0] IN/OUT GPIO port x pins 31 to 0
GPIO1 pin[31:0] P1[31:0] IN/OUT GPIO port x pins 31 to 0
GPIO2 pin[27:0] P2[27:0] IN/OUT GPIO port x pins 27 to 0
GPIO3 pin[15:0] P3[15:0] IN/OUT GPIO port x pins 15 to 0
GPIO4 pin[23:0] P4[23:0] IN/OUT GPIO port x pins 23 to 0
GPIO5 pin[19:0] P5[19:0] IN/OUT GPIO port x pins 19 to 0
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Listen-only mode (no acknowledge; no active error flags) Reception of ‘own’ messages (self-reception request) Full CAN mode for message reception
6.14.1.1 Global acceptance filter

The global acceptance filter provides look-up of received identifiers - called acceptance
filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table
memory, in which software maintains one to five sections of identifiers. The CAN ID
look-up table memory is 2 kB large (512 words, each of 32 bits). It can contain up to 1024
standard frame identifiers or 512 extended frame identifiers or a mixture of both types. It is
also possible to define identifier groups for standard and extended message formats.
6.14.1.2 Pin description

The two CAN controllers in the LPC2939 have the pins listed below. The CAN pins are
combined with other functions on the port pins of the LPC2939. Table 20 shows the CAN
pins (x runs from 0 to 1).
6.14.2 LIN

The LPC2939 contain two LIN 2.0 master controllers. These can be used as dedicated
LIN 2.0 master controllers with additional support for sync break generation and with
hardware implementation of the LIN protocol according to spec 2.0.
Remark: Both LIN channels can be also configured as UART channels.

The key features are: Complete LIN 2.0 message handling and transfer One interrupt per LIN message Slave response time-out detection Programmable sync-break length Automatic sync-field and sync-break generation Programmable inter-byte space Hardware or software parity generation Automatic checksum generation Fault confinement Fractional baud rate generator
6.14.2.1 Pin description

The two LIN 2.0 master controllers in the LPC2939 have the pins listed below. The LIN
pins are combined with other functions on the port pins of the LPC2939. Table 21 shows
the LIN pins. For more information see Ref. 1 subsection 3.43, LIN master controller.
Table 20. CAN pins

CANx TXD TXDC0/1 OUT CAN channel x transmit data output
CANx RXD RXDC0/1 IN CAN channel x receive data input
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

6.14.3I2 C-bus serial I/O controllers

The LPC2939 each contain two I2 C-bus controllers.
The I2 C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or as a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2 C is a multi-master bus, and it can be
controlled by more than one bus master connected to it.
The main features if the I2 C-bus interfaces are:I2 C0 and I2 C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2 C-bus)
and do not support powering off of individual devices connected to the same bus lines Easy to configure as master, slave, or master/slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer The I2 C-bus can be used for test and diagnostic purposes All I2 C-bus controllers support multiple address recognition and a bus monitor mode
6.14.3.1 Pin description

[1] Note that the pins are not I2 C-bus compliant open-drain pins.
6.15 Modulation and Sampling Control SubSystem (MSCSS)

The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2939 includes four
Pulse-Width Modulators (PWMs), three 10-bit successive approximation Analog-to-Digital
Converters (ADCs) and two timers.
The key features of the MSCSS are:
Table 21. LIN controller pins

LIN0/1 TXD TXDL0/1 OUT LIN channel 0/1 transmit data output
LIN0/1 RXD RXDL0/1 IN LIN channel 0/1 receive data input
Table 22. I2C-bus pins[1]

I2C SCL0/1 SCL0/1 I/O I2C clock input/output
I2C SDA0/1 SDA0/1 I/O I2C data input/output
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various trigger-
start options One 10-bit, 400 ksamples/s, 8-channel ADC with 5 V inputs (5 V measurement range)
and various trigger-start options Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality Two dedicated timers to schedule and synchronize the PWMs and ADCs Quadrature encoder interface
6.15.1 Functional description

The MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters
(ADCs) and timers.
Figure 8 provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of
communication with the AHB system bus. Two internal timers are dedicated to this
subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the
first PWM. The second timer (MSCSS timer 1) is used to generate ‘carrier’ signals for the
PWMs. These carrier patterns can be used, for example, in applications requiring current
control. Several other trigger possibilities are provided for the ADCs (external, cascaded
or following a PWM). The capture inputs of both timers can also be used to capture the
start pulse of the ADCs.
The PWMs can be used to generate waveforms in which the frequency, duty cycle and
rising and falling edges can be controlled very precisely. Capture inputs are provided to
measure event phases compared to the main counter. Depending on the applications,
these inputs can be connected to digital sensor motor outputs or digital external signals.
Interrupt signals are generated on several events to closely interact with the CPU.
The ADCs can be used for any application needing accurate digitized data from analog
sources. To support applications like motor control, a mechanism to synchronize several
PWMs and ADCs is available (sync_in and sync_out).
Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see
Section 6.16.2.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.15.2 Pin description

The pins of the LPC2939 MSCSS associated with the three ADC modules are described
in Section 6.15.4.2. Pins connected to the four PWM modules are described in
Section 6.15.5.4, pins directly connected to the MSCSS timer 1 module are described in
Section 6.15.6.1, and pins connected to the quadrature encoder interface are described in
Section 6.15.7.1.
6.15.3 Clock description

The MSCSS is clocked from a number of different sources: CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge CLK_MSCSS_APB clocks the subsystem APB bus CLK_MSCSS_MTMR0/1 clocks the timers CLK_MSCSS_PWM0:3 clocks the PWMs
Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB (x = 0,
1, or 2) and a control part for the analog section clocked by CLK_ADCx = 0, 1, or 2), see
Section 6.7.2.
All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A
which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived
from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding
clocks can be switched off.
6.15.4 Analog-to-digital converter

The MSCSS in the LPC2939 includes three 10-bit successive-approximation
analog-to-digital converters.
The key features of the ADC interface module are: ADC0: Eight analog inputs; time-multiplexed; measurement range up to 5.0V ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to
3.3V External reference-level inputs 400 ksamples/s at 10-bit resolution up to 1500 ksamples/s at 2-bit resolution Programmable resolution from 2-bit to10-bit Single analog-to-digital conversion scan mode and continuous analog-to-digital
conversion scan mode Optional conversion on transition on external start input, timer capture/match signal,
PWM_sync or ‘previous’ ADC Converted digital values are stored in a register for each channel Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’
compare-value indication for each channel Power-down mode
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.15.4.1 Functional description

The ADC block diagram, Figure 9, shows the basic architecture of each ADC. The ADC
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.
The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower
than or equal to the system clock frequency. To meet this constraint or to select the
desired lower sampling frequency, the clock generation unit provides a programmable
fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined
by the ADC clock frequency divided by the number of resolution bits plus one. Accessing
ADC registers requires an enabled ADC clock, which is controllable via the clock
generation unit, see Section 6.16.2.
Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system
clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs
are connected at MSCSS level, see Section 6.15 for details.
6.15.4.2 Pin description

The three ADC modules in the MSCSS have the pins described below. The ADCx input
pins are combined with other functions on the port pins of the LPC2939. The VREFN and
VREFP pins are common to all ADCs. Table 23 shows the ADC pins.
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[1] VREFP, VREFN, VDDA(ADC3V3) must be connected for the 5 V ADC0 to operate properly.
[2] The analog inputs of ADC0 are internally multiplied by a factor of 3.3/ 5. If VDDA(ADC5V0) is connected to
3.3 V, the maximum digital result is 10243.3/5.
[3] VDDA(ADC5V0) and VDDA(ADC3V3) must be set as follows: VDDA(ADC5V0) = VDDA(ADC3V3)  1.5.
Remark: The following formula only applies to ADC0:

Voltage variations on VREFP (i.e. those that deviate from voltage variations on the
VDDA(ADC5V5) pin) are visible as variations in the measurement result. Equation 3 shows
the formula used to determine the conversion result of an input voltage VIN on ADC0:
(3)
Remark: Note that the ADC1 and ADC2 accept an input voltage up to of 3.6 V (see

Table 34) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant. The
ADC0 pins are 5 V tolerant.
6.15.4.3 Clock description

The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_APB and
CLK_ADCx (x = 0, 1, or 2), see Section 6.7.2. Note that each ADC has its own
CLK_ADCx and CLK_MSCSS_ADCx_APB branch clocks for power management. If an
ADC is unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off.
The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to
CLK_MSCSS_APB since they are derived from the same base clock
BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical
since they are derived from the same base clock BASE_ADC_CLK.
The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB.
Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also
Figure9.
6.15.5 Pulse Width Modulator (PWM)

The MSCSS in the LPC2939 includes four PWM modules with the following features.
Table 23. Analog to digital converter pins

ADC0 IN[7:0] IN0[7:0] IN analog input for 5.0 V ADC0, channel 7 to
channel 0
ADC1/2 IN[7:0] IN1/2[7:0] IN analog input for 3.3 V ADC1/2, channel 7 to
channel 0
ADCn_EXTSTART CAP1[n] IN ADC external start-trigger input (n is 0, 1, or 2)
VREFN VREFN IN ADC LOW reference level
VREFP VREFP IN ADC HIGH reference level
VDDA(ADC5V0) VDDA(ADC5V0)[1] IN 5 V high-power supply and HIGH reference for
ADC0. Connect to clean 5 V as HIGH reference.
May also be connected to 3.3 V if 3.3 V
measurement range for ADC0 is needed. [2][3]
VDDA(ADC3V3) VDDA(ADC3V3) IN ADC1 and ADC2 3.3 V supply (also used for
ADC0).[3]
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ARM9 microcontroller with CAN, LIN, and USB
Six pulse-width modulated output signals Double edge features (rising and falling edges programmed individually) Optional interrupt generation on match (each edge) Different operation modes: continuous or run-once 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods A protective mode (TRAP) holding the output in a software-controllable state and with
optional interrupt generation on a trap event Three capture registers and capture trigger pins with optional interrupt generation on
a capture event Interrupt generation on match event, capture event, PWM counter overflow or trap
event A burst mode mixing the external carrier signal with internally generated PWM Programmable sync-delay output to trigger other PWM modules (master/slave
behavior)
6.15.5.1 Functional description

The ability to provide flexible waveforms allows PWM blocks to be used in multiple
applications; e.g. dimmer/lamp control and fan control. Pulse-width modulation is the
preferred method for regulating power since no additional heat is generated, and it is
energy-efficient when compared with linear-regulating voltage control networks.
The PWM delivers the waveforms/pulses of the desired duty cycles and cycle periods. A
very basic application of these pulses can be in controlling the amount of power
transferred to a load. Since the duty cycle of the pulses can be controlled, the desired
amount of power can be transferred for a controlled duration. Two examples of such
applications are: Dimmer controller: The flexibility of providing waves of a desired duty cycle and cycle
period allows the PWM to control the amount of power to be transferred to the load.
The PWM functions as a dimmer controller in this application. Motor controller: The PWM provides multi-phase outputs, and these outputs can be
controlled to have a certain pattern sequence. In this way the force/torque of the
motor can be adjusted as desired. This makes the PWM function as a motor drive.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB

The PWM block diagram in Figure 10 shows the basic architecture of each PWM. PWM
functionality is split into two major parts, a APB domain and a PWM domain, both of which
run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects
behavior from a system-level perspective. The actual PWM and prescale counters are
located in the PWM domain but system control takes place in the APB domain.
The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM
counter. The position of the rising and falling edges of the PWM outputs can be
programmed individually. The prescale counter allows high system bus frequencies to be
scaled down to lower PWM periods. Registers are available to capture the PWM counter
values on external events.
Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock
source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer
counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references
are related to the period of this clock. See Section 6.16 for information on generation of
these clocks.
6.15.5.2 Synchronizing the PWM counters

A mechanism is included to synchronize the PWM period to other PWMs by providing a
sync input and a sync output with programmable delay. Several PWMs can be
synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.
See Figure 8 for details of the connections of the PWM modules within the MSCSS in the
LPC2939. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc.
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.15.5.3 Master and slave mode

A PWM module can provide synchronization signals to other modules (also called Master
mode). The signal sync_out is a pulse of one clock cycle generated when the internal
PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out,
generated if a transfer from system registers to PWM shadow registers occurred when the
PWM counter restarted. A delay may be inserted between the counter start and
generation of trans_enable_out and sync_out.
A PWM module can use input signals trans_enable_in and sync_in to synchronize its
internal PWM counter and the transfer of shadow registers (Slave mode).
6.15.5.4 Pin description

Each of the four PWM modules in the MSCSS has the following pins. These are combined
with other functions on the port pins of the LPC2939. Table 24 shows the PWM0 to PWM3
pins.
6.15.5.5 Clock description

The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0 to 3), see Section 6.7.2.
Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power
management. The frequency of all these clocks is identical to CLK_MSCSS_APB since
they are derived from the same base clock BASE_MSCSS_CLK.
Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer
counter registers of the PWM modules run at the same clock as the APB system interface
CLK_MSCSS_APB. This clock is independent of the AHB system clock.
If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off.
6.15.6 Timers in the MSCSS

The two timers in the MSCSS are functionally identical to the timers in the peripheral
subsystem, see Section 6.13.3. The features of the timers in the MSCSS are the same as
the timers in the peripheral subsystem, but the capture inputs and match outputs are not
available on the device pins. These signals are instead connected to the ADC and PWM
modules as outlined in the description of the MSCSS, see Section 6.15.1.
See Section 6.13.3 for a functional description of the timers.
Table 24. PWM pins

PWMn CAP[0] PCAPn[0] IN PWM n capture input0
PWMn CAP[1] PCAPn[1] IN PWM n capture input1
PWMn CAP[2] PCAPn[2] IN PWM n capture input2
PWMn MAT[0] PMATn[0] OUT PWM n match output0
PWMn MAT[1] PMATn[1] OUT PWM n match output1
PWMn MAT[2] PMATn[2] OUT PWM n match output2
PWMn MAT[3] PMATn[3] OUT PWM n match output3
PWMn MAT[4] PMATn[4] OUT PWM n match output4
PWMn MAT[5] PMATn[5] OUT PWM n match output5
PWMn TRAP TRAPn IN PWM n trap input
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ARM9 microcontroller with CAN, LIN, and USB
6.15.6.1 Pin description

MSCSS timer 0 has no external pins.
MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined
with other functions on the port pins of the LPC2939. Table 25 shows the MSCSS timer1
external pin.
6.15.6.2 Clock description

The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx (x = 0 to 1), see
Section 6.7.2. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for
power management. The frequency of all these clocks is identical to CLK_MSCSS_APB
since they are derived from the same base clock BASE_MSCSS_CLK.
Note that, unlike the timer modules in the Peripheral SubSystem, the actual timer counter
registers run at the same clock as the APB system interface CLK_MSCSS_APB. This
clock is independent of the AHB system clock.
If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off.
6.15.7 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
The QEI has the following features: Tracks encoder position Increments/ decrements depending on direction Programmable for 2 or 4 position counting Velocity capture using built-in timer Velocity compare function with less than interrupt Uses 32-bit registers for position and velocity Three position compare registers with interrupts Index counter for revolution counting Index compare register with interrupts Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement Digital filter with programmable delays for encoder input signals Can accept decoded signal inputs (clk and direction) Connected to APB
Table 25. MSCSS timer 1 pin

MSCSS PAUSE IN pause pin for MSCSS timer1
NXP Semiconductors LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.15.7.1 Pin description

The QEI module in the MSCSS has the following pins. These are combined with other
functions on the port pins of the LPC2939. Table 26 shows the QEI pins.
6.15.7.2 Clock description

The QEI module is clocked by CLK_MSCSS_QEI, see Section 6.7.2. The frequency of
this clock is identical to CLK_MSCSS_APB since they are derived from the same base
clock BASE_MSCSS_CLK.
If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off.
6.16 Power, Clock and Reset control SubSystem (PCRSS)

The Power, Clock and Reset Control Subsystem in the LPC2939 includes a Clock
Generator Unit (CGU), a Reset Generator Unit (RGU), and a Power Management Unit
(PMU).
Figure 11 provides an overview of the PCRSS. An AHB-to-DTL bridge controls the
communication with the AHB system bus.
Table 26. QEI pins

QEI0 IDX IDX0 IN Index signal. Can be used to reset the position.
QEI0 PHA PHA0 IN Sensor signal. Corresponds to PHA in
quadrature mode and to direction in
clock/direction mode.
QEI0 PHB PHB0 IN Sensor signal. Corresponds to PHB in
quadrature mode and to clock signal in
clock/direction mode.
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