LPC2458FET180 ,Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interfaceGeneral descriptionNXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit A ..
LPC2460FBD208 ,Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interfaceFeatures and benefits ARM7TDMI-S processor, running at up to 72 MHz. 82/98 kB on-chip SRAM includ ..
LPC2460FET208 ,Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interfacefeatures.LPC2420_60 All information provided in this document is subject to legal disclaimers. NXP ..
LPC2468FBD208 ,Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interfaceFeatures and benefits ARM7TDMI-S processor, running at up to 72 MHz. 512 kB on-chip flash program ..
LPC2468FET208 ,Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interfaceGeneral descriptionNXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit A ..
LPC2470FBD208 ,Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interfaceFeatures and benefits ARM7TDMI-S processor, running at up to 72 MHz. 98 kB on-chip SRAM includes: ..
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LPC2458FET180
Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
1. General descriptionNXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This
flash memory includes a special 128-bit wide memory interface and accelerator
architecture that enables the CPU to execute sequential instructions from flash memory at
the maximum 72 MHz system clock rate. This feature is available only on the LPC2000
ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and
16-bit Thumb instructions. Support for the two instruction sets means engineers can
choose to optimize their application for either performance or code size at the sub-routine
level. When the core executes instructions in Thumb state it can reduce code size by
more than 30 % with only a small loss in performance while executing instructions in ARM
state maximizes core performance.
The LPC2458 microcontroller is ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C
interfaces, and an I2 S interface. Supporting this collection of serial communications
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered interrupts. All of these features make the LPC2458
particularly suitable for industrial control and medical systems.
2. Features and benefits ARM7TDMI-S processor, running at up to 72 MHz. 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access. 98 kB on-chip SRAM includes:64 kB of SRAM on the ARM local bus for high performance CPU access.16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
LPC2458
Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN,
ISP/IAP , USB 2.0 device/host/OTG, external memory interface
Rev. 4.1 — 15 October 2013 Product data sheet
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro16 kB SRAM for general purpose DMA use also accessible by the USB.2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain. Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, USB DMA, and program execution from on-chip flash with no contention. EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as Single Data Rate SDRAM. Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts. General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP, 2 S, and SD/MM interface as well as for memory-to-memory transfers. Serial Interfaces: Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB. USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and
associated DMA controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO. CAN controller with two channels. SPI controller. Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller. Three I2 C-bus interfaces (one with open-drain and two with standard port pins).I2 S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA. Other peripherals: SD/MMC memory card interface. 136 General purpose I/O pins with configurable pull-up/down resistors. 10-bit ADC with input multiplexing among 8 pins. 10-bit DAC. Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input. Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs. RTC with separate power domain, clock source can be the RTC oscillator or the
APB clock.2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock. Standard ARM test/debug interface for compatibility with existing tools. Emulation trace module supports real-time trace. Single 3.3 V power supply (3.0 V to 3.6 V). Four reduced power modes: idle, sleep, power-down, and deep power-down. Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources. Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro Two independent power domains allow fine tuning of power consumption based on
needed features. Each peripheral has its own clock divider for further power saving. These dividers help
reduce active power by 20 % to 30%. Brownout detect with separate thresholds for interrupt and forced reset. On-chip power-on reset. On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator. Boundary scan for simplified board testing. Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
3. Applications Industrial control Medical systems Protocol converter Communications
4. Ordering information
4.1 Ordering options
Table 1. Ordering informationLPC2458FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-3
Table 2. Ordering optionsLPC2458FET180 512 64 16 162 98 16-bit MII/RMII yes 2 yes yes 8 1 40 C to +85C
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
5. Block diagramNXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
6. Pinning information
6.1 Pinning
Table 3. Pin allocation table
Row A
Row B
Row C
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
Row D
Row E
Row F
Row G
Row H
Row J
Table 3. Pin allocation table …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
Row K
Row L
Row M
Row N
Row P
Table 3. Pin allocation table …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
6.2 Pin descriptionTable 4. Pin descriptionP0[0] to P0[31] I/O
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin
Connect block.
P0[0]/RD1/
TXD3/SDA1
M10[1] I/O
P0[0] — General purpose digital input/output pin. RD1 — CAN1 receiver input. TXD3 — Transmitter output for UART3.I/O
SDA1 — I2 C1 data input/output (this is not an open-drain pin).
P0[1]/TD1/RXD3/
SCL1
N11[1] I/O
P0[1] — General purpose digital input/output pin. TD1 — CAN1 transmitter output. RXD3 — Receiver input for UART3.I/O
SCL1 — I2 C1 clock input/output (this is not an open-drain pin).
P0[2]/TXD0 D5[1] I/O
P0[2] — General purpose digital input/output pin. TXD0 — Transmitter output for UART0.P0[3]/RXD0 A3[1] I/O
P0[3] — General purpose digital input/output pin. RXD0 — Receiver input for UART0.P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
A11[1] I/O
P0[4] — General purpose digital input/output pin.I/O
I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2 S-bus specification.
RD2 — CAN2 receiver input. CAP2[0] — Capture input for Timer 2, channel 0.
P0[5]/
I2SRX_WS/
TD2/CAP2[1]
B11[1] I/O
P0[5] — General purpose digital input/output pin.I/O
I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2 S-bus specification.
TD2 — CAN2 transmitter output. CAP2[1] — Capture input for Timer 2, channel 1.
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
D11[1] I/O
P0[6] — General purpose digital input/output pin.I/O
I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2 S-bus specification.
I/O
SSEL1 — Slave Select for SSP1. MAT2[0] — Match output for Timer 2, channel 0.
P0[7]/
I2STX_CLK/
SCK1/MAT2[1]
B12[1] I/O
P0[7] — General purpose digital input/output pin.I/O
I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2 S-bus specification.
I/O
SCK1 — Serial Clock for SSP1. MAT2[1] — Match output for Timer 2, channel 1.
P0[8]/
I2STX_WS/
MISO1/MAT2[2]
C12[1] I/O
P0[8] — General purpose digital input/output pin.I/O
I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2 S-bus specification.
I/O
MISO1 — Master In Slave Out for SSP1. MAT2[2] — Match output for Timer 2, channel 2.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP0[9]/
I2STX_SDA/
MOSI1/MAT2[3]
A13[1] I/O
P0[9] — General purpose digital input/output pin.I/O
I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2 S-bus specification.
I/O
MOSI1 — Master Out Slave In for SSP1. MAT2[3] — Match output for Timer 2, channel 3.
P0[10]/TXD2/
SDA2/MAT3[0]
L10[1] I/O
P0[10] — General purpose digital input/output pin. TXD2 — Transmitter output for UART2.I/O
SDA2 — I2 C2 data input/output (this is not an open-drain pin).
MAT3[0] — Match output for Timer 3, channel 0.
P0[11]/RXD2/
SCL2/MAT3[1]
P12[1] I/O
P0[11] — General purpose digital input/output pin. RXD2 — Receiver input for UART2.I/O
SCL2 — I2 C2 clock input/output (this is not an open-drain pin).
MAT3[1] — Match output for Timer 3, channel 1.
P0[12]/
USB_PPWR2/
MISO1/AD0[6][2] I/O
P0[12] — General purpose digital input/output pin. USB_PPWR2 — Port Power enable signal for USB port 2.I/O
MISO1 — Master In Slave Out for SSP1. AD0[6] — A/D converter 0, input 6.P0[13]/
USB_UP_LED2/
MOSI1/AD0[7][2] I/O
P0[13] — General purpose digital input/output pin. USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled), or when host is enabled and has
detected a device on the bus. It is HIGH when the device is not configured, or
when host is enabled and has not detected a device on the bus, or during global
suspend. It transitions between LOW and HIGH (flashes) when host is enabled
and detects activity on the bus.
I/O
MOSI1 — Master Out Slave In for SSP1. AD0[7] — A/D converter 0, input 7.P0[14]/
USB_HSTEN2/
USB_CONNECT2/
SSEL1[1] I/O
P0[14] — General purpose digital input/output pin. USB_HSTEN2 — Host Enabled status for USB port 2. USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect
USB feature.
I/O
SSEL1 — Slave Select for SSP1.P0[15]/TXD1/
SCK0/SCK
H13[1] I/O
P0[15] — General purpose digital input/output pin. TXD1 — Transmitter output for UART1.I/O
SCK0 — Serial clock for SSP0.I/O
SCK — Serial clock for SPI.P0[16]/RXD1/
SSEL0/SSEL
H14[1] I/O
P0[16] — General purpose digital input/output pin. RXD1 — Receiver input for UART1.I/O
SSEL0 — Slave Select for SSP0.I/O
SSEL — Slave Select for SPI.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP0[17]/CTS1/
MISO0/MISO
J12[1] I/O
P0[17] — General purpose digital input/output pin. CTS1 — Clear to Send input for UART1.I/O
MISO0 — Master In Slave Out for SSP0.I/O
MISO — Master In Slave Out for SPI.P0[18]/DCD1/
MOSI0/MOSI
J13[1] I/O
P0[18] — General purpose digital input/output pin. DCD1 — Data Carrier Detect input for UART1.I/O
MOSI0 — Master Out Slave In for SSP0.I/O
MOSI — Master Out Slave In for SPI.P0[19]/DSR1/
MCICLK/SDA1
J10[1] I/O
P0[19] — General purpose digital input/output pin. DSR1 — Data Set Ready input for UART1. MCICLK — Clock output line for SD/MMC interface.I/O
SDA1 — I2 C1 data input/output (this is not an open-drain pin).
P0[20]/DTR1/
MCICMD/SCL1
K14[1] I/O
P0[20] — General purpose digital input/output pin. DTR1 — Data Terminal Ready output for UART1.I/O
MCICMD — Command line for SD/MMC interface.I/O
SCL1 — I2 C1 clock input/output (this is not an open-drain pin).
P0[21]/RI1/
MCIPWR/RD1
K11[1] I/O
P0[21] — General purpose digital input/output pin. RI1 — Ring Indicator input for UART1. MCIPWR — Power Supply Enable for external SD/MMC power supply. RD1 — CAN1 receiver input.P0[22]/RTS1/
MCIDAT0/TD1
L14[1] I/O
P0[22] — General purpose digital input/output pin. RTS1 — Request to Send output for UART1.I/O
MCIDAT0 — Data line 0 for SD/MMC interface. TD1 — CAN1 transmitter output.P0[23]/AD0[0]/
I2SRX_CLK/
CAP3[0][2] I/O
P0[23] — General purpose digital input/output pin. AD0[0] — A/D converter 0, input 0.I/O
I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2 S-bus specification.
CAP3[0] — Capture input for Timer 3, channel 0.
P0[24]/AD0[1]/
I2SRX_WS/
CAP3[1][2] I/O
P0[24] — General purpose digital input/output pin. AD0[1] — A/D converter 0, input 1.I/O
I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2 S-bus specification.
CAP3[1] — Capture input for Timer 3, channel 1.
P0[25]/AD0[2]/
I2SRX_SDA/
TXD3[2] I/O
P0[25] — General purpose digital input/output pin. AD0[2] — A/D converter 0, input 2.I/O
I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2 S-bus specification.
TXD3 — Transmitter output for UART3.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP0[26]/AD0[3]/
AOUT/RXD3 [2][3] I/O
P0[26] — General purpose digital input/output pin. AD0[3] — A/D converter 0, input 3. AOUT — D/A converter output. RXD3 — Receiver input for UART3.P0[27]/SDA0 L3[4] I/O
P0[27] — General purpose digital input/output pin. Output is open-drain.I/O
SDA0 — I2 C0 data input/output. Open-drain output (for I2 C-bus compliance).
P0[28]/SCL0 M1[4] I/O
P0[28] — General purpose digital input/output pin. Output is open-drain.I/O
SCL0 — I2 C0 clock input/output. Open-drain output (for I2 C-bus compliance).
P0[29]/USB_D+1 K5[5] I/O
P0[29] — General purpose digital input/output pin. I/O
USB_D+1 — USB port 1 bidirectional D+ line.P0[30]/USB_D1N4[5] I/O
P0[30] — General purpose digital input/output pin.I/O
USB_D1 — USB port 1 bidirectional D line.P0[31]/USB_D+2 N1[5] I/O
P0[31] — General purpose digital input/output pin.I/O
USB_D+2 — USB port 2 bidirectional D+ line.P1[0] to P1[31] I/O
Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 1 pins depends upon the pin function selected via the Pin
Connect block.
P1[0]/
ENET_TXD0[1] I/O
P1[0] — General purpose digital input/output pin. ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).P1[1]/
ENET_TXD1[1] I/O
P1[1] — General purpose digital input/output pin. ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).P1[2]/
ENET_TXD2/
MCICLK/
PWM0[1][1] I/O
P1[2] — General purpose digital input/output pin. ENET_TXD2 — Ethernet transmit data 2 (MII interface). MCICLK — Clock output line for SD/MMC interface. PWM0[1] — Pulse Width Modulator 0, output 1.P1[3]/
ENET_TXD3/
MCICMD/
PWM0[2][1] I/O
P1[3] — General purpose digital input/output pin. ENET_TXD3 — Ethernet transmit data 3 (MII interface).I/O
MCICMD — Command line for SD/MMC interface. PWM0[2] — Pulse Width Modulator 0, output 2.P1[4]/
ENET_TX_EN[1] I/O
P1[4] — General purpose digital input/output pin. ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface).P1[5]/
ENET_TX_ER/
MCIPWR/
PWM0[3]
B13[1] I/O
P1[5] — General purpose digital input/output pin. ENET_TX_ER — Ethernet Transmit Error (MII interface). MCIPWR — Power Supply Enable for external SD/MMC power supply. PWM0[3] — Pulse Width Modulator 0, output 3.P1[6]/
ENET_TX_CLK/
MCIDAT0/
PWM0[4]
B10[1] I/O
P1[6] — General purpose digital input/output pin. ENET_TX_CLK — Ethernet Transmit Clock (MII interface).I/O
MCIDAT0 — Data line 0 for SD/MMC interface. PWM0[4] — Pulse Width Modulator 0, output 4.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP1[7]/
ENET_COL/
MCIDAT1/
PWM0[5]
C13[1] I/O
P1[7] — General purpose digital input/output pin. ENET_COL — Ethernet Collision detect (MII interface).I/O
MCIDAT1 — Data line 1 for SD/MMC interface. PWM0[5] — Pulse Width Modulator 0, output 5.P1[8]/
ENET_CRS_DV/
ENET_CRS[1] I/O
P1[8] — General purpose digital input/output pin. ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid (RMII interface)/ Ethernet Carrier Sense (MII interface).
P1[9]/
ENET_RXD0[1] I/O
P1[9] — General purpose digital input/output pin. ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).P1[10]/
ENET_RXD1[1] I/O
P1[10] — General purpose digital input/output pin. ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).P1[11]/
ENET_RXD2/
MCIDAT2/
PWM0[6]
A12[1] I/O
P1[11] — General purpose digital input/output pin. ENET_RXD2 — Ethernet Receive Data 2 (MII interface).I/O
MCIDAT2 — Data line 2 for SD/MMC interface. PWM0[6] — Pulse Width Modulator 0, output 6.P1[12]/
ENET_RXD3/
MCIDAT3/
PCAP0[0]
A14[1] I/O
P1[12] — General purpose digital input/output pin. ENET_RXD3 — Ethernet Receive Data (MII interface).I/O
MCIDAT3 — Data line 3 for SD/MMC interface. PCAP0[0] — Capture input for PWM0, channel 0.P1[13]/
ENET_RX_DV
D14[1] I/O
P1[13] — General purpose digital input/output pin. ENET_RX_DV — Ethernet Receive Data Valid (MII interface).P1[14]/
ENET_RX_ER[1] I/O
P1[14] — General purpose digital input/output pin. ENET_RX_ER — Ethernet receive error (RMII/MII interface).P1[15]/
ENET_REF_CLK/
ENET_RX_CLK[1] I/O
P1[15] — General purpose digital input/output pin. ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII interface)/ Ethernet Receive Clock (MII interface).
P1[16]/
ENET_MDC[1] I/O
P1[16] — General purpose digital input/output pin. ENET_MDC — Ethernet MIIM clock.P1[17]/
ENET_MDIO[1] I/O
P1[17] — General purpose digital input/output pin.I/O
ENET_MDIO — Ethernet MI data input and output.P1[18]/
USB_UP_LED1/
PWM1[1]/
CAP1[0][1] I/O
P1[18] — General purpose digital input/output pin. USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled), or when host is enabled and has
detected a device on the bus. It is HIGH when the device is not configured, or
when host is enabled and has not detected a device on the bus, or during global
suspend. It transitions between LOW and HIGH (flashes) when host is enabled
and detects activity on the bus.
PWM1[1] — Pulse Width Modulator 1, channel 1 output. CAP1[0] — Capture input for Timer 1, channel 0.
P1[19]/
USB_TX_E1/
USB_PPWR1/
CAP1[1][1] I/O
P1[19] — General purpose digital input/output pin. USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver). USB_PPWR1 — Port Power enable signal for USB port 1. CAP1[1] — Capture input for Timer 1, channel 1.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP1[20]/
USB_TX_DP1/
PWM1[2]/SCK0[1] I/O
P1[20] — General purpose digital input/output pin. USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver). PWM1[2] — Pulse Width Modulator 1, channel 2 output.I/O
SCK0 — Serial clock for SSP0.P1[21]/
USB_TX_DM1/
PWM1[3]/SSEL0[1] I/O
P1[21] — General purpose digital input/output pin. USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver). PWM1[3] — Pulse Width Modulator 1, channel 3 output.I/O
SSEL0 — Slave Select for SSP0.P1[22]/
USB_RCV1/
USB_PWRD1/
MAT1[0][1] I/O
P1[22] — General purpose digital input/output pin. USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver). USB_PWRD1 — Power Status for USB port 1 (host power switch). MAT1[0] — Match output for Timer 1, channel 0.
P1[23]/
USB_RX_DP1/
PWM1[4]/MISO0[1] I/O
P1[23] — General purpose digital input/output pin. USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver). PWM1[4] — Pulse Width Modulator 1, channel 4 output.I/O
MISO0 — Master In Slave Out for SSP0.P1[24]/
USB_RX_DM1/
PWM1[5]/MOSI0[1] I/O
P1[24] — General purpose digital input/output pin. USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver). PWM1[5] — Pulse Width Modulator 1, channel 5 output.I/O
MOSI0 — Master Out Slave in for SSP0.P1[25]/
USB_LS1/
USB_HSTEN1/
MAT1[1][1] I/O
P1[25] — General purpose digital input/output pin. USB_LS1 — Low-speed status for USB port 1 (OTG transceiver). USB_HSTEN1 — Host Enabled status for USB port 1. MAT1[1] — Match output for Timer 1, channel 1.
P1[26]/
USB_SSPND1/
PWM1[6]/
CAP0[0][1] I/O
P1[26] — General purpose digital input/output pin. USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver). PWM1[6] — Pulse Width Modulator 1, channel 6 output. CAP0[0] — Capture input for Timer 0, channel 0.
P1[27]/
USB_INT1/
USB_OVRCR1/
CAP0[1][1] I/O
P1[27] — General purpose digital input/output pin. USB_INT1 — USB port 1 OTG transceiver interrupt. USB_OVRCR1 — USB port 1 Over-Current status. CAP0[1] — Capture input for Timer 0, channel 1.
P1[28]/
USB_SCL1/
PCAP1[0]/
MAT0[0]
P10[1] I/O
P1[28] — General purpose digital input/output pin.I/O
USB_SCL1 — USB port 1 I2 C serial clock (OTG transceiver).
PCAP1[0] — Capture input for PWM1, channel 0. MAT0[0] — Match output for Timer 0, channel 0.
P1[29]/
USB_SDA1/
PCAP1[1]/
MAT0[1]
N10[1] I/O
P1[29] — General purpose digital input/output pin.I/O
USB_SDA1 — USB port 1 I2 C serial data (OTG transceiver).
PCAP1[1] — Capture input for PWM1, channel 1. MAT0[1] — Match output for Timer 0, channel 0.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP1[30]/
USB_PWRD2/
VBUS/AD0[4][2] I/O
P1[30] — General purpose digital input/output pin. USB_PWRD2 — Power Status for USB port 2. VBUS — Monitors the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur. AD0[4] — A/D converter 0, input 4.P1[31]/
USB_OVRCR2/
SCK1/AD0[5][2] I/O
P1[31] — General purpose digital input/output pin. USB_OVRCR2 — Over-Current status for USB port 2.I/O
SCK1 — Serial Clock for SSP1. AD0[5] — A/D converter 0, input 5.P2[0] to P2[31] I/O
Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin
Connect block.
Pins P2[14:15], P2[22:23], P[26:27] and P2[30:31] are not available.
P2[0]/PWM1[1]/
TXD1/
TRACECLK
D12[1] I/O
P2[0] — General purpose digital input/output pin. PWM1[1] — Pulse Width Modulator 1, channel 1 output. TXD1 — Transmitter output for UART1. TRACECLK — Trace Clock.P2[1]/PWM1[2]/
RXD1/
PIPESTAT0
C14[1] I/O
P2[1] — General purpose digital input/output pin. PWM1[2] — Pulse Width Modulator 1, channel 2 output. RXD1 — Receiver input for UART1. PIPESTAT0 — Pipeline Status, bit 0.P2[2]/PWM1[3]/
CTS1/
PIPESTAT1
E11[1] I/O
P2[2] — General purpose digital input/output pin. PWM1[3] — Pulse Width Modulator 1, channel 3 output. CTS1 — Clear to Send input for UART1. PIPESTAT1 — Pipeline Status, bit 1.P2[3]/PWM1[4]/
DCD1/
PIPESTAT2
E13[1] I/O
P2[3] — General purpose digital input/output pin. PWM1[4] — Pulse Width Modulator 1, channel 4 output. DCD1 — Data Carrier Detect input for UART1. PIPESTAT2 — Pipeline Status, bit 2.P2[4]/PWM1[5]/
DSR1/
TRACESYNC
E14[1] I/O
P2[4] — General purpose digital input/output pin. PWM1[5] — Pulse Width Modulator 1, channel 5 output. DSR1 — Data Set Ready input for UART1. TRACESYNC — Trace Synchronization.P2[5]/PWM1[6]/
DTR1/
TRACEPKT0
F12[1] I/O
P2[5] — General purpose digital input/output pin. PWM1[6] — Pulse Width Modulator 1, channel 6 output. DTR1 — Data Terminal Ready output for UART1. TRACEPKT0 — Trace Packet, bit 0.P2[6]/PCAP1[0]/RI1/
TRACEPKT1
F13[1] I/O
P2[6] — General purpose digital input/output pin. PCAP1[0] — Capture input for PWM1, channel 0. RI1 — Ring Indicator input for UART1. TRACEPKT1 — Trace Packet, bit 1.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP2[7]/RD2/
RTS1/
TRACEPKT2
G11[1] I/O
P2[7] — General purpose digital input/output pin. RD2 — CAN2 receiver input. RTS1 — Request to Send output for UART1. TRACEPKT2 — Trace Packet, bit 2.P2[8]/TD2/
TXD2/
TRACEPKT3
G14[1] I/O
P2[8] — General purpose digital input/output pin. TD2 — CAN2 transmitter output. TXD2 — Transmitter output for UART2. TRACEPKT3 — Trace Packet, bit 3.P2[9]/
USB_CONNECT1/
RXD2/
EXTIN0
H11[1] I/O
P2[9] — General purpose digital input/output pin. USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an external 1.5 k resistor under the software control. Used with the SoftConnect
USB feature.
RXD2 — Receiver input for UART2. EXTIN0 — External Trigger Input.P2[10]/EINT0 M13[6] I/O
P2[10] — General purpose digital input/output pin.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset.
EINT0 — External interrupt 0 input.P2[11]/EINT1/
MCIDAT1/
I2STX_CLK
M12[6] I/O
P2[11] — General purpose digital input/output pin. EINT1 — External interrupt 1 input.I/O
MCIDAT1 — Data line 1 for SD/MMC interface.I/O
I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2 S-bus specification.
P2[12]/EINT2/
MCIDAT2/
I2STX_WS
N14[6] I/O
P2[12] — General purpose digital input/output pin. EINT2 — External interrupt 2 input.I/O
MCIDAT2 — Data line 2 for SD/MMC interface.I/O
I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2 S-bus specification.
P2[13]/EINT3/
MCIDAT3/
I2STX_SDA
M11[6] I/O
P2[13] — General purpose digital input/output pin. EINT3 — External interrupt 3 input.I/O
MCIDAT3 — Data line 3 for SD/MMC interface.I/O
I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2 S-bus specification.
P2[16]/CAS P9[1] I/O
P2[16] — General purpose digital input/output pin. CAS — LOW active SDRAM Column Address Strobe.P2[17]/RAS P11[1] I/O
P2[17] — General purpose digital input/output pin. RAS — LOW active SDRAM Row Address Strobe.P2[18]/
CLKOUT0[1] I/O
P2[18] — General purpose digital input/output pin. CLKOUT0 — SDRAM clock 0.P2[19]/
CLKOUT1[1] I/O
P2[19] — General purpose digital input/output pin. CLKOUT1 — SDRAM clock 1.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP2[20]/DYCS0 P6[1] I/O
P2[20] — General purpose digital input/output pin. DYCS0 — SDRAM chip select 0.P2[21]/DYCS1 N8[1] I/O
P2[21] — General purpose digital input/output pin. DYCS1 — SDRAM chip select 1.P2[24]/
CKEOUT0[1] I/O
P2[24] — General purpose digital input/output pin. CKEOUT0 — SDRAM clock enable 0.P2[25]/
CKEOUT1[1] I/O
P2[25] — General purpose digital input/output pin. CKEOUT1 — SDRAM clock enable 1.P2[28]/
DQMOUT0[1] I/O
P2[28] — General purpose digital input/output pin. DQMOUT0 — Data mask 0 used with SDRAM and static devices.P2[29]/
DQMOUT1[1] I/O
P2[29] — General purpose digital input/output pin. DQMOUT1 — Data mask 1 used with SDRAM and static devices.P3[0] to P3[31] I/O
Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the Pin
Connect block.
Pins P3[16:22] and P3[27:31] are not available.
P3[0]/D0 D6[1] I/O
P3[0] — General purpose digital input/output pin.I/O
D0 — External memory data line 0.P3[1]/D1 E6[1] I/O
P3[1] — General purpose digital input/output pin.I/O
D1 — External memory data line 1.P3[2]/D2 A2[1] I/O
P3[2] — General purpose digital input/output pin.I/O
D2 — External memory data line 2.P3[3]/D3 G5[1] I/O
P3[3] — General purpose digital input/output pin.I/O
D3 — External memory data line 3.P3[4]/D4 D3[1] I/O
P3[4] — General purpose digital input/output pin.I/O
D4 — External memory data line 4.P3[5]/D5 E3[1] I/O
P3[5] — General purpose digital input/output pin.I/O
D5 — External memory data line 5.P3[6]/D6 F4[1] I/O
P3[6] — General purpose digital input/output pin.I/O
D6 — External memory data line 6.P3[7]/D7 G3[1] I/O
P3[7] — General purpose digital input/output pin.I/O
D7 — External memory data line 7.P3[8]/D8 A6[1] I/O
P3[8] — General purpose digital input/output pin.I/O
D8 — External memory data line 8.P3[9]/D9 A4[1] I/O
P3[9] — General purpose digital input/output pin.I/O
D9 — External memory data line 9.P3[10]/D10 B3[1] I/O
P3[10] — General purpose digital input/output pin.I/O
D10 — External memory data line 10.P3[11]/D11 B2[1] I/O
P3[11] — General purpose digital input/output pin.I/O
D11 — External memory data line 11.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP3[12]/D12 A1[1] I/O
P3[12] — General purpose digital input/output pin.I/O
D12 — External memory data line 12.P3[13]/D13 C1[1] I/O
P3[13] — General purpose digital input/output pin.I/O
D13 — External memory data line 13.P3[14]/D14 F1[1] I/O
P3[14] — General purpose digital input/output pin.I/O
D14 — External memory data line 14.P3[15]/D15 G4[1] I/O
P3[15] — General purpose digital input/output pin.I/O
D15 — External memory data line 15.P3[23]/CAP0[0]/
PCAP1[0][1] I/O
P3[23] — General purpose digital input/output pin. CAP0[0] — Capture input for Timer 0, channel 0.
PCAP1[0] — Capture input for PWM1, channel 0.P3[24]/CAP0[1]/
PWM1[1][1] I/O
P3[24] — General purpose digital input/output pin. CAP0[1] — Capture input for Timer 0, channel 1.
PWM1[1] — Pulse Width Modulator 1, output 1.P3[25]/MAT0[0]/
PWM1[2][1] I/O
P3[25] — General purpose digital input/output pin. MAT0[0] — Match output for Timer 0, channel 0.
PWM1[2] — Pulse Width Modulator 1, output 2.P3[26]/MAT0[1]/
PWM1[3][1] I/O
P3[26] — General purpose digital input/output pin. MAT0[1] — Match output for Timer 0, channel 1.
PWM1[3] — Pulse Width Modulator 1, output 3.P4[0] to P4[31] I/O
Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the Pin
Connect block.
Pins P4[20:23] are not available.
P4[0]/A0 L6[1] I/O
P4[0] — General purpose digital input/output pin.I/O
A0 — External memory address line 0.P4[1]/A1 M7[1] I/O
P4[1] — General purpose digital input/output pin.I/O
A1 — External memory address line 1.P4[2]/A2 M8[1] I/O
P4[2] — General purpose digital input/output pin.I/O
A2 — External memory address line 2.P4[3]/A3 K9[1] I/O
P4[3] — General purpose digital input/output pin.I/O
A3 — External memory address line 3.P4[4]/A4 P13[1] I/O
P4[4] — General purpose digital input/output pin.I/O
A4 — External memory address line 4.P4[5]/A5 H10[1] I/O
P4[5] — General purpose digital input/output pin.I/O
A5 — External memory address line 5.P4[6]/A6 K10[1] I/O
P4[6] — General purpose digital input/output pin.I/O
A6 — External memory address line 6.P4[7]/A7 K12[1] I/O
P4[7] — General purpose digital input/output pin.I/O
A7 — External memory address line 7.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP4[8]/A8 J11[1] I/O
P4[8] — General purpose digital input/output pin.I/O
A8 — External memory address line 8.P4[9]/A9 H12[1] I/O
P4[9] — General purpose digital input/output pin.I/O
A9 — External memory address line 9.P4[10]/A10 G12[1] I/O
P4[10] — General purpose digital input/output pin.I/O
A10 — External memory address line 10.P4[11]/A11 F11[1] I/O
P4[11] — General purpose digital input/output pin.I/O
A11 — External memory address line 11.P4[12]/A12 F10[1] I/O
P4[12] — General purpose digital input/output pin.I/O
A12 — External memory address line 12.P4[13]/A13 B14[1] I/O
P4[13] — General purpose digital input/output pin.I/O
A13 — External memory address line 13.P4[14]/A14 E8[1] I/O
P4[14] — General purpose digital input/output pin.I/O
A14 — External memory address line 14.P4[15]/A15 C10[1] I/O
P4[15] — General purpose digital input/output pin.I/O
A15 — External memory address line 15.P4[16]/A16 N12[1] I/O
P4[16] — General purpose digital input/output pin.I/O
A16 — External memory address line 16.P4[17]/A17 N13[1] I/O
P4[17] — General purpose digital input/output pin.I/O
A17 — External memory address line 17.P4[18]/A18 P14[1] I/O
P4[18] — General purpose digital input/output pin.I/O
A18 — External memory address line 18.P4[19]/A19 M14[1] I/O
P4[19] — General purpose digital input/output pin.I/O
A19 — External memory address line 19.P4[24]/OE C8[1] I/O
P4[24] — General purpose digital input/output pin. OE — LOW active Output Enable signal.P4[25]/WE D9[1] I/O
P4[25] — General purpose digital input/output pin. WE — LOW active Write Enable signal.P4[26]/BLS0 K13[1] I/O
P4[26] — General purpose digital input/output pin. BLS0 — LOW active Byte Lane select signal 0.P4[27]/BLS1 F14[1] I/O
P4[27] — General purpose digital input/output pin. BLS1 — LOW active Byte Lane select signal 1.P4[28]/MAT2[0]/
TXD3
D10[1] I/O
P4[28] — General purpose digital input/output pin. MAT2[0] — Match output for Timer 2, channel 0.
TXD3 — Transmitter output for UART3.P4[29]/MAT2[1]/
RXD3[1] I/O
P4[29] — General purpose digital input/output pin. MAT2[1] — Match output for Timer 2, channel 1.
RXD3 — Receiver input for UART3.P4[30]/CS0 C7[1] I/O
P4[30] — General purpose digital input/output pin. CS0 — LOW active Chip Select 0 signal.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microP4[31]/CS1 E7[1] I/O
P4[31] — General purpose digital input/output pin. CS1 — LOW active Chip Select 1 signal.ALARM H5[7] O
ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC
alarm is generated.
USB_D2N2 I/O
USB_D2 — USB port 2 bidirectional D line.DBGEN E5 [1][8] I
DBGEN — JTAG interface control signal. Also used for boundary scan.TDO B1 [1][9] O
TDO — Test Data Out for JTAG interface.TDI C3 [1][8] I
TDI — Test Data In for JTAG interface.TMS C2 [1][8] I
TMS — Test Mode Select for JTAG interface.TRST D4 [1][8] I
TRST — Test Reset for JTAG interface.TCK D2 [1][9] I
TCK — Test Clock for JTAG interface. This clock must be slower than 1 ⁄6 of the
CPU clock (CCLK) for the JTAG interface to operate.
RTCK C4 [1][8] I/O
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset.
RSTOUT H2 O
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2458 being in Reset state.
RESET J1[10] I
external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 L2 [7][11] I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 K4 [7][11] O Output from the oscillator amplifier.
RTCX1 J2 [7][12] I Input to the RTC oscillator circuit.
RTCX2 J3 [7][12] O Output from the RTC oscillator circuit.
VSSIO H4, P4,
L9, L13,
G13,
D13,
C11, [13]
ground: 0 V reference for the digital IO pins.
VSSCORE H3, L8,
A10[13] I
ground: 0 V reference for the core.
VSSA F3[14] I
analog ground: 0 V reference. This should nominally be the same voltage as
VSSIO/VSSCORE, but should be isolated to minimize noise and error.
VDD(3V3) E2, L4,
K8, L11,
J14, E12,
E10, [15]
3.3 V supply voltage: This is the power supply voltage for the I/O ports.n.c. H1, L12,
G10[16] I
not connected pins: These pins must be left unconnected (floating).VDD(DCDC)(3V3) G1, N9, [17] I
3.3 V DC-to-DC converter supply voltage: This is the power supply for the on-chip DC-to-DC converter.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
[3]5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7] Pad provides special analog functionality.
[8] This pin has a built-in pull-up resistor.
[9] This pin has no built-in pull-up and no built-in pull-down resistor.
[10] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
[12] If the RTC is not used, these pins can be left floating.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
[15] Pad provides special analog functionality.
[16] Pad provides special analog functionality.
[17] Pad provides special analog functionality.
[18] Pad provides special analog functionality.
7. Functional description
7.1 Architectural overviewThe LPC2458 microcontroller consists of an ARM7TDMI-S CPU with emulation support,
the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip
memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external
memory, and the AMBA APB for connection to other on-chip peripheral functions. The
microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte
order.
The LPC2458 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the VIC, GPDMA controller, and EMC.
VDDA F2[18] I
analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used
to power the ADC and DAC.
VREF G2[18] I
ADC reference: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. The level on this pin is used as a
reference for ADC and DAC.
VBAT K1[18] I
RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
Table 4. Pin description …continued
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microThe second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,
and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2
are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB. The
AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is
allocated a 16 kB address space within the APB address space.
The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers
high performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed complex
instruction set computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
the standard 32-bit ARM set
a 16-bit Thumb set
The Thumb set’s 16-bit instruction length allows it to approach higher density compared to
standard ARM code while retaining most of the ARM’s performance.
7.2 On-chip flash programming memoryThe LPC2458 incorporates 512 kB flash memory system. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port (UART0). The
application program may also erase and/or program the flash while the application is
running, allowing a great degree of flexibility for data storage field and firmware upgrades.
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at speeds of 72 MHz.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.3 On-chip SRAMThe LPC2458 includes a SRAM memory of 64 kB reserved for the ARM processor
exclusive use. This RAM may be used for code and/or data storage and may be accessed
as 8 bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM
associated with the second AHB can be used both for data and code storage. The 2 kB
RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and
retains the content in the absence of the main power supply.
7.4 Memory mapThe LPC2458 memory map incorporates several distinct regions as shown in Table 5 and
Figure3.
In addition, the CPU interrupt vectors may be remapped to allow them to reside in either
flash memory (default), boot ROM, or SRAM (see Section 7.26.6).
Table 5. LPC2458 memory usage and details0x0000 0000 to
0x3FFF FFFF
on-chip
non-volatile memory and fast
I/O
0x0000 0000 to 0x0007 FFFF flash memory (512 kB)
0x3FFF C000 to 0x3FFF FFFF fast GPIO registers
0x4000 0000 to
0x7FFF FFFF
on-chip RAM 0x4000 0000 to 0x4000 FFFF RAM (64 kB)
0x7FE0 0000 to 0x7FE0 3FFF Ethernet RAM (16 kB)
0x7FD0 0000 to 0x7FD0 3FFF USB RAM (16 kB)
0x8000 0000 to
0xBFFF FFFF
off-chip memory two static memory banks, 1 MB each
0x8000 0000 to 0x800F FFFF static memory bank 0
0x8100 0000 to 0x810F FFFF static memory bank 1
two dynamic memory banks, 256 MB each
0xA000 0000 to 0xAFFF FFFF dynamic memory bank 0
0xB000 0000 to 0xBFFF FFFF dynamic memory bank 1
0xE000 0000 to
0xEFFF FFFF
APB peripherals 36 peripheral blocks, 16 kB each
0xF000 0000 to
0xFFFF FFFF
AHB peripherals
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.5 Interrupt controllerThe ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast
Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be
programmed as FIQ or vectored IRQ types. The programmable assignment scheme
means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.
FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs
the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ
latency is achieved when only one request is classified as FIQ, because then the FIQ
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microservice routine can simply start dealing with that device. But if more than one request is
assigned to the FIQ class, the FIQ service routine can read a word from the VIC that
identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a
programmable interrupt priority. When more than one interrupt is assigned the same
priority and occur simultaneously, the one connected to the lowest numbered VIC channel
will be serviced first.
The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the
ARM processor. The IRQ service routine can start by reading a register from the VIC and
jumping to the address supplied by that register.
7.5.1 Interrupt sourcesEach peripheral device has one interrupt line connected to the VIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both. Such
interrupt request coming from port 0 and/or port 2 will be combined with the EINT3
interrupt requests.
7.6 Pin connect blockThe pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.7 External memory controllerThe LPC2458 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering
support for asynchronous static memory devices such as RAM, ROM, and flash. In
addition, it can be used as an interface with off-chip memory-mapped devices and
peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
peripheral.
7.7.1 Features Dynamic memory interface support including single data rate SDRAM.
Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
Low transaction latency.
Read and write buffers to reduce latency and to improve performance.
8/16 data and 20 address lines wide static memory support.
16 bit wide chip select SDRAM memory support.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro Static memory features include:
Asynchronous page mode read
Programmable Wait States
Bus turnaround delay
Output enable and write enable delays
Extended wait
Two chip selects for synchronous memory and two chip selects for static memory
devices.
Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
Dynamic memory self-refresh mode controlled by software.
Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, and 16 data bits per device.
Separate reset domains allow auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
7.8 General purpose DMA controllerThe GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2458
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
7.8.1 Features Two DMA channels. Each channel can support a unidirectional transfer.
The GPDMA can transfer data between the 16 kB SRAM, external memory, and
peripherals such as the SD/MMC, two SSPs, and the I2 S interface.
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time, the channel with the
highest priority is serviced first.
AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro One AHB master for transferring data. This interface transfers data when a DMA
request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
Internal four-word FIFO per channel.
Supports 8-bit, 16-bit, and 32-bit wide transactions.
An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
Interrupt masking. The DMA error and DMA terminal count interrupt requests can be
masked.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.9 Fast general purpose parallel I/ODevice pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC2458 use accelerated GPIO functions:
GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved.
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All GPIO registers are byte and half-word addressable.
Entire port value can be written in one instruction.
Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an
analog input/output can be programmed to generate an interrupt on a rising edge, a falling
edge, or both. The edge detection is asynchronous, so it may operate when clocks are not
present such as during Power-down mode. Each enabled interrupt can be used to wake
the chip up from Power-down mode.
7.9.1 Features Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Backward compatibility with other earlier devices is maintained with legacy port 0 and
port 1 registers appearing at the original addresses on the APB.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.10 EthernetThe Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access
the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic
in the LPC2458 takes place on a different AHB subsystem, effectively separating Ethernet
activity from the rest of the system. The Ethernet DMA can also access off-chip memory
via the EMC, as well as the SRAM located on another AHB. However, using memory
other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to
memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
7.10.1 Features Ethernet standards support:
Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
Fully compliant with IEEE standard 802.3.
Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
Flexible transmit and receive frame options.
Virtual Local Area Network (VLAN) frame support.
Memory management:
Independent transmit and receive buffers memory mapped to shared SRAM.
DMA managers with scatter/gather DMA and arrays of frame descriptors.
Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
Receive filtering.
Multicast and broadcast frame support for both transmit and receive.
Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
Selectable automatic transmit frame padding.
Over-length frame support for both transmit and receive allows any length frames.
Promiscuous receive mode.
Automatic collision back-off and frame retransmission.
Includes power management by clock switching.
Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro Physical interface:
Attachment of external PHY chip through standard MII or RMII interface.
PHY register access is available via the MIIM interface.
7.11 USB interfaceThe Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The Host Controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
Host Controller.
The LPC2458 USB interface includes a device, Host, and OTG Controller. Details on
typical USB interfacing solutions can be found in Section 14.1 “Suggested USB interface
solutions” on page 65
7.11.1 USB device controllerThe device controller enables 12 Mbit/s data exchange with a USB Host Controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.11.1.1 Features Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, LPC2458 can enter one of the reduced power
modes and wake up on USB activity.
Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
7.11.2 USB Host ControllerThe Host Controller enables full- and low-speed data exchange with USB devices
attached to the bus. It consists of a register interface, a serial interface engine and a DMA
controller. The register interface complies with the OHCI specification.
7.11.2.1 Features OHCI compliant.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro Two downstream ports.
Supports per-port power switching.
7.11.3 USB OTG ControllerUSB OTG is a supplement to the USB 2.0 specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the Host Controller, device controller, and a master-only 2 C interface to implement OTG dual-role device functionality. The dedicated I2 C interface
controls an external OTG transceiver.
7.11.3.1 Features Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.12 CAN controller and acceptance filtersThe Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router between two of CAN buses in industrial
or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.12.1 Features Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with CAN specification 2.0B, ISO 11898-1.
Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
FullCAN messages can generate interrupts.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.13 10-bit ADCThe LPC2458 contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.13.1 Features 10-bit successive approximation ADC
Input multiplexing among 8 pins
Power-down mode
Measurement range 0 V to Vi(VREF)
10-bit conversion time 2.44s
Burst conversion mode for single or multiple inputs
Optional conversion on transition of input pin or Timer Match signal
Individual result registers for each ADC channel to reduce interrupt overhead
7.14 10-bit DACThe DAC allows the LPC2458 to generate a variable analog output. The maximum output
value of the DAC is Vi(VREF).
7.14.1 Features 10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
7.15 UARTsThe LPC2458 contains four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface.
The UART s include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.15.1 Features 16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro UART3 includes an IrDA mode to support infrared communication.
7.16 SPI serial I/O controllerThe LPC2458 contains one SPI controller. SPI is a full duplex serial interface designed to
handle multiple masters and slaves connected to a given bus. Only a single master and a
single slave can communicate on the interface during a given data transfer. During a data
transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave
always sends 8 bits to 16 bits of data to the master.
7.16.1 Features Compliant with SPI specification
Synchronous, Serial, Full Duplex Communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
7.17 SSP serial I/O controllerThe LPC2458 contains two SSP controllers. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the
bus. Only a single master and a single slave can communicate on the bus during a given
data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of
data flowing from the master to the slave and from the slave to the master. In practice,
often only one of these data flows carries meaningful data.
7.17.1 Features Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave
mode) of the input clock rate
DMA transfers supported by GPDMA
7.18 SD/MMC card interfaceThe Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11.
7.18.1 Features The MCI interface provides all functions specific to the SD/MMC memory card. These
include the clock generation unit, power management control, and command and data
transfer.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro Conforms to Multimedia Card Specification v2.11.
Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
DMA supported through the GPDMA controller.
7.19I2 C-bus serial I/O controllerThe LPC2458 contains three I2 C-bus controllers.
The I2 C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2 C-bus is a multi-master bus and can
be controlled by more than one bus master connected to it.
The I2 C-bus implemented in LPC2458 supports bit rates up to 400 kbit/s (Fast I2 C-bus).
7.19.1 FeaturesI2 C0 is a standard I2 C compliant bus interface with open-drain pins.
I2 C1 and I2 C2 use standard I/O pins and do not support powering off of individual
devices connected to the same bus lines.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2 C-bus can be used for test and diagnostic purposes.
7.20I2 S-bus serial I/O controllersThe I2 S-bus provides a standard communication interface for digital audio applications.
The I2 S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2 S connection has one master, which is always the
master, and one slave. The I2 S interface on the LPC2458 provides a separate transmit
and receive channel, each of which can operate as either a master or a slave.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.20.1 Features The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
Configurable word select period in master mode (separately for I2 S input and output).
Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop and mute options separately for I2 S input and I2 S output.
7.21 General purpose 32-bit timers/external event countersThe LPC2458 includes four 32-bit Timer/Counters. The Timer/Counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. The Timer/Counter also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
7.21.1 Features A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Counter or Timer operation.
Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.22 Pulse width modulatorThe PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2458. The Timer is designed to count
cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. A
dedicated match register controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, a dedicated match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
7.22.1 Features LPC2458 has two PWMs with the same operational features. These may be operated
in a synchronized fashion by setting them both up to run at the same rate, then
enabling both simultaneously. PWM0 acts as the master and PWM1 as the slave for
this use.
Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
7.23 Watchdog timer (WDT)The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
7.23.1 Features Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK)232 4) in
multiples of Tcy(WDCLK)4.
The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the
Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of
potential timing choices of Watchdog operation under different power reduction
conditions. It also provides the ability to run the WDT from an entirely internal source
that is not dependent on an external crystal and its associated components and
wiring, for increased reliability.
7.24 RTC and battery RAMThe RTC is a set of counters for measuring time when system power is on, and optionally
when power is off. It uses little power in Power-down and Deep power-down modes. On
the LPC2458, the RTC can be clocked by a separate 32.768 kHz oscillator or by a
programmable prescale divider based on the APB clock. The RTC is powered by its own
power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply
used by the rest of the device.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microThe VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power is removed, the RTC
can supply an alarm output that can be used by external hardware to restore chip power
and resume operation.
7.24.1 Features Measures the passage of time to maintain a calendar and clock.
Ultra low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
Dedicated 32 kHz oscillator or programmable prescaler from APB clock.
Dedicated power supply pin can be connected to a battery or to the main 3.3V.
An alarm output pin is included to assist in waking up when the chip has had power
removed to all functions except the RTC and Battery RAM.
Periodic interrupts can be generated from increments of any field of the time registers,
and selected fractional second values. This enhancement enables the RTC to be
used as a System Timer.
2 kB data SRAM powered by VBAT.
RTC and Battery RAM power supply is isolated from the rest of the chip.
7.25 Clocking and power control
7.25.1 Crystal oscillatorsThe LPC2458 includes three independent oscillators. These are the Main Oscillator, the
Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than
one purpose as required in a particular application. Any of the three clock sources can be
chosen by software to drive the PLL and ultimately the CPU.
Following reset, the LPC2458 will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
7.25.1.1 Internal RC oscillatorThe IRC may be used as the clock source for the WDT , and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is
trimmed to 1 % accuracy.
Upon power-up or any chip reset, the LPC2458 uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.25.1.2 Main oscillatorThe main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can
be boosted to a higher frequency, up to the maximum CPU operating frequency, by the
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microPLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to Section 7.25.2 for additional information.
7.25.1.3 RTC oscillatorThe RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the
RTC oscillator can be used to drive the PLL and the CPU.
7.25.2 PLLThe PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value
‘N’, which may be in the range of 1 to 256. This input division provides a wide range of
output frequencies from the same input frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only. The program must configure and activate the PLL,
wait for the PLL to lock, then connect to the PLL as a clock source.
7.25.3 Wake-up timerThe LPC2458 begins operation at power-up and when awakened from Power-down and
Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This
allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down and Deep power-down
modes, any wake-up of the processor from Power-down modes makes use of the
Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some event caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
sufficient amplitude to drive the clock logic. The amount of time depends on many factors,
including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry
(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.25.4 Power controlThe LPC2458 supports a variety of power control features. There are four special modes
of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, Peripheral power control allows shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Each of the peripherals
has its own clock divider which provides even better power control.
The LPC2458 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the RTC and a small SRAM,
referred to as the Battery RAM.
7.25.4.1 Idle modeIn Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.25.4.2 Sleep modeIn Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The kHz RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
The Sleep mode can be terminated and normal operation resumed by either a Reset or
certain specific interrupts that are able to function without clocks. Since all dynamic
operation of the chip is suspended, Sleep mode reduces chip power consumption to a
very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.
On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the
code execution and peripherals activities will resume after 4 cycles expire. If the main
external oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
7.25.4.3 Power-down modePower-down mode does everything that Sleep mode does, but also turns off the IRC
oscillator and the flash memory. This saves more power, but requires waiting for
resumption of flash operation before execution of code or data access in the flash memory
can be accomplished.
On the wake-up from Power-down mode, if the IRC was used before entering
Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire
before the code execution can then be resumed if the code was running from SRAM. In
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit microthe meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the
100 s flash start-up time. When it times out, access to the flash will be allowed. The
customers need to reconfigure the PLL and clock dividers accordingly.
7.25.4.4 Deep power-down modeDeep power-down mode is similar to the Power-down mode, but now the on-chip
regulator that supplies power to the internal logic is also shut off. This produces the lowest
possible power consumption without removing power from the entire chip. Since the Deep
power-down mode shuts down the on-chip logic power supply, there is no register or
memory retention, and resumption of operation involves the same activities as a full chip
reset.
If power is supplied to the LPC2458 during Deep power-down mode, wake-up can be
caused by the RTC Alarm interrupt or by external Reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2458 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the Battery RAM, as long as the external power
to the VBAT pin is maintained.
7.25.4.5 Power domainsThe LPC2458 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the RTC and the Battery RAM.
On the LPC2458, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the
VDD(DCDC)(3V3) pins power the on-chip DC-to-DC converter which in turn provides power to
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and
a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-DC
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.26 System control
7.26.1 ResetReset has four sources on the LPC2458: the RESET pin, the Watchdog reset, power-on
reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable
level, starts the Wake-up timer (see description in Section 7.25.3 “Wake-up timer”),
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the flash controller has completed its
initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.26.2 Brownout detectionThe LPC2458 includes 2-stage monitoring of the voltage on the VDD(DCDC)(3V3) pins. If this
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
The second stage of low-voltage detection asserts Reset to inactivate the LPC2458 when
the voltage on the VDD(DCDC)(3V3) pins falls below 2.65 V. This Reset prevents alteration of
the flash as operation of the various elements of the chip would otherwise become
unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at
which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
7.26.3 Code security (Code Read Protection - CRP)This feature of the LPC2458 allows user to enable different levels of security in the system
so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When
needed, CRP is invoked by programming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
NXP Semiconductors LPC2458
Single-chip 16-bit/32-bit micro
7.26.4 AHB The LPC2458 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB
SRAM.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters
with access to AHB2 are the ARM7 and the Ethernet block.
7.26.5 External interrupt inputsThe LPC2458 includes up to 68 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
7.26.6 Memory mapping controlThe memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM, the SRAM, or external memory. This allows code running in different memory
spaces to have control of the interrupts.
7.27 Emulation and debuggingThe LPC2458 support emulation and debugging via a JTAG serial port. A trace port allows
tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface
peripherals residing on other pins are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
7.27.1 EmbeddedICEThe EmbeddedICE logic provides on-chip debug support. The debugging of the target
system requires a host computer running the debugger software and an EmbeddedICE
protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug
Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present
on the target system.
The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC
allows a program running on the target to communicate with the host debugger or another
separate host without stopping the program flow or even entering the debug state. The
