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LMH1982SQE/NOPB
Multi-Rate Video Clock Generator with Genlock
GENLOCKED
3G-SDI OUT
FPGA
with SerDes
TRIPLE-RATE SDI
LMH1982OUT
LPF
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LMH1982SNLS289D –APRIL 2008–REVISED SEPTEMBER 2015
LMH1982 Multi-Rate Video Clock Generator With Genlock Features 3 DescriptionThe LMH1982 deviceisa multi-rate video clock Two Simultaneous LVDS Output Clocks with generator ideal for useina wide rangeof 3-GbpsSelectable Frequencies and Hi-Z Capability: (3G), high-definition (HD), and standard-definition– SD Clock:27 MHzor 67.5 MHz (SD) video applications, such as video HD Clock: 74.25 MHz, 74.25/1.001 MHz, synchronization, serial digital interface (SDI) serializer
and deserializer (SerDes), video conversion, video148.5 MHzor 148.5/1.001 MHz editing, and other broadcast and professional video• Low-Jitter Output Clocks May Be Directly systems.Connectedtoan FPGA Serializerto Meet SMPTE
The LMH1982 can generate two simultaneous SDSDI Jitter Specifications
and HD clocks anda Topof Frame (TOF) pulse.In• Topof Frame (TOF) Pulse with Programmable genlock mode, the device's phase locked loopsOutput Format Timing and Hi-Z Capability (PLLs) can synchronize the output signalstoH sync• Two reference ports(A andB) WithH andV Sync andV sync input signals appliedto either of the
Inputs reference ports. The input reference can have analog
timing from Texas Instrument's LMH1981 multi-format• Supports Cross-Lockingof Input and Output video sync separatoror digital timing from an SDITiming deserializer and should conformto the major SD and• External Loop Filter Allows Controlof Loop HD standards. Whena lossof reference occurs, theBandwidth, Jitter Transfer, and Lock Time device can defaultto free run operation where theCharacteristics output timing accuracy will be determined by the
external bias on the free run control voltage input.• Free Runor Holdover Operationon Lossof
Reference The LMH1982 can replace discrete PLLs and field-• User-Defined Free Run Control Voltage Input programmable gate array (FPGA) PLLs with multiple
voltage controlled crystal oscillators (VCXOs). Only•I2C Interface and Control Registers one 27.0000 MHz VCXO and loop filter are externally• 3.3-V and 2.5-V Supplies required for genlock mode. The external loop filteras
well as programmable PLL parameters can provide
2 Applications narrow loop bandwidthsto minimize jitter transfer. HD
clock output jitter as low as 40 ps peak-to-peak can• Video Genlock and Synchronization
help designers using FPGA SerDes meet stringent• FPGA SDI SerDes Recovered Clock Generation SDI output jitter specifications.• Triple Rate 3G/HD/SD-SDI SerDes
The LMH1982is offeredina space-saving5 mmx5• Video Capture, Conversion, Editing and mm 32-pin WQFN package and provides low totalDistribution power consumptionof about 250 mW (typical).• Video Displays and Projectors
Device Information(1)• Broadcast and Professional Video Equipment
(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Application Typical Loop Filter Topology
