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LMH0031VSNSN/a160avaiDigital Video Deserializer/Descrambler w/ Video & Ancillary Data FIFOs 64-TQFP 0 to 70


LMH0031VS ,Digital Video Deserializer/Descrambler w/ Video & Ancillary Data FIFOs 64-TQFP 0 to 70FEATURES APPLICATIONS2• SDTV/HDTV Serial Digital Video Standard • SDTV/HDTV Serial-to-Parallel Digi ..
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LMH0031VS
Digital Video Deserializer/Descrambler w/ Video & Ancillary Data FIFOs
LMH0031
www.ti.com
SNLS218A –JANUARY 2006–REVISED APRIL 2013
LMH0031 SMPTE 292M/259M Digital Video Deserializer/ Descrambler with Video
and Ancillary Data FIFOs
Checkfor Samples: LMH0031
1FEATURES APPLICATIONS SDTV/HDTV Serial Digital Video Standard • SDTV/HDTV Serial-to-Parallel Digital Video
Compliant Interfaces for: Supports 270 Mbps, 360 Mbps, 540 Mbps, – Video Editing Equipment
1.483 Gbps and 1.485 Gbps Serial Video Data – VTRs
Rates with Auto-Detection – Standards Converters LSB De-Dithering Option – Digital Video Routers and Switchers• Uses Low-Cost 27MHz Crystalor Clock – Digital Video Processing and EditingOscillator Reference Equipment Fast VCO Lock Time:< 500µsat 1.485 Gbps – Video Test Pattern Generators and Digital• Built-in Self-Test (BIST) and Video Test Pattern Video Test EquipmentGenerator (TPG) – Video Signal Generators

(1) Patent Applications Madeor Pending
DESCRIPTION• Automatic EDH/CRC Word and Flag
Processing
The LMH0031 SMPTE 292M/ 259M Digital Video
Deserializer/Descrambler with Video and Ancillary• Ancillary Data FIFO with Extensive Packet Data FIFOsisa monolithic integrated circuit thatHandling Options deserializes and decodes SMPTE 292M, 1.485Gbps• Adjustable, 4-Deep Parallel Output Video Data (or 1.483Gbps) serial component video data,to 20-bitFIFO parallel data witha synchronized parallel word-rate
clock.It also deserializes and decodes SMPTE 259M,• Flexible Control and Configuration I/O Port
270Mbps, 360Mbps and SMPTE 344M (proposed)• LVCMOS Compatible Control Inputs and Clock 540Mbps serial component video data, to 10-bitand Data Outputs parallel data. Functions performed by the LMH0031• LVDS and ECL-Compatible, Differential, Serial include: clock/data recovery from the serial data,
Inputs
serial-to-parallel data conversion, SMPTE standard
data decoding, NRZI-to-NRZ conversion, parallel data• 3.3V I/O Power Supply and 2.5V Logic Power clock generation, word framing, CRC and EDH dataSupply Operation checking and handling, Ancillary Data extraction and 850mW automatic video format determination. The parallel video output featuresa variable-depth FIFO which
can be adjustedto delay the output data upto4 Range 0°Cto +70°C Ancillary Data may be from the parallel data through
the use of masking and control bits in the
configuration and and storedin the
on-chip FIFO. dithering
implemented.
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