LMC669CCN ,+/-8 V to +/-20 V, 3 mA, auto-zeroElectrical Characteristics The following specifications apply for V+ = + 15V, and V‘ = - 15V unless ..
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LQG18HN2N7S00D , Chip Coils for High Frequency Monolithic Type
LQG18HN2N7S00D , Chip Coils for High Frequency Monolithic Type
LQG18HN33NJ00D , Chip Coils for High Frequency Monolithic Type
LQG18HN33NJ00D , Chip Coils for High Frequency Monolithic Type
LQG18HN3N3S00D , Chip Coils for High Frequency Monolithic Type
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LMC669CCN
+/-8 V to +/-20 V, 3 mA, auto-zero
LMC669
I National
T Semiconductor
LMC669 Auto-Zero
General Description
The LMC669 uses sampled-data techniques to reduce the
input offset voltage Nos) of an amplifier or system to ap-
proximately 5 wit. A four-stage comparator samples the
summing node of an inverting-amplifier and generates a cor-
rection voltage that is applied to the amplitier's non-invert-
ing input. The offset correction is independent of time, tem-
perature. and supply voltage, and requires no initial or peri-
odic user offset adjustments.
The user may also adjust clock frequency, sample rate, and
the correction voltage's step size and magnitude.
The Auto-Zero operates on supply voltages of iBV to
A20V with a quiescent current of 3 mA.
The use of the LM0669 does not limit the performance of
the ampliMr it is used with. Full use of the gain-bandwidth
product, slew rate, and DC gain is retained.
The LMC669 can be used as a precision comparator with a
latched, open drain output, or as a Iow-oftset inverting oper-
ational amplifier for low-speed applications.
Featu res
u 5 microvolts typical offset voltage
I: Temperature independent offset correction
" Internal or external clocking
n Automatic and continuous offset voltage correction
I: High voltage CMOS-up to i20V supplies
Typical Application
20 (16)
m 2 LMCSSS
_ IN REF
w (6) ll
OUTPUT
OUT REF 6(5)
TL/H/8661-1
Numbers In I ) are for t6-pln packages
Absolute Maximum Ratings (Notes1&2)
If MIIItary/Aorospaco specified devices are requlred.
please contact tho National Sqttnittonthttttttr Sales
OffitttVDftttrlttttttmt for availability and spoclflcatlons.
Positive Supply Voltage (V +) + 22V
Negative Supply Voltage (V -) - 22V
Voltage of Logic Pins
T1, T2, W. CLK -0.2V to (V+ + 0.2V)
Voltage at Inputs -0.2Y to N + + 0.2V)
Input Current (Note 3)
INREF, IN1 and 1N2 20 mA
Power Dissipation (Note 4)
Storage Temperature
Lead Temp. (soldering, 10 seconds)
500 mW
- 65''C to + 150°C
Operating Ranges (Notes1 & 2)
Temperature Range TMINS TA s TMAX
LM06690 -40t s; TA g +85''C
Positive Supply Voltage + 8V to + 20V
Negative Supply Voltage - 8V to - 20V
INREF, IN1 and IN2 Voltage (Note 5)
-200 mV to +2V
ESD Susceptability (Note 10) 600V
Electrical Characteristics The following specifications apply for V+ = +15V, and V‘ = - 15V unless
otherwise specified. Boldface llmltn apply for Tram to Tm: all other limits TA = Tu = 25°C.
T lcal Tasted Dealgn
Symbol Parameter Conditions (Nyolze 6) Limit Limit Unlts
(Note n (Note B)
vos Maximum Input LMC669BIN, BIM Signal applied to both * 5 * "
OffsetVoltago LMC669BGN, BCM IN1 & ml2, TCLK = K25
Note 9 50 " VINHEF =
( ) LMC669tyN, CIM OV, 0.5V i 10 i so pil/
LMC669CCN, COM 1 50
LMC669OD i 5 i "
Vos Maximum Input LMC669BIN, BIM Signal applied only to * 10 k 50
OffsetVoltage LMC669BCN, BCM IN1 or IN2, TCLK = 150
(Note 9) LMC669CIN, CIM 50 M, VINREF = ov i 20 * 100 WV
LMC669CGN, COM d: 100
LMC669CD i 10 i BO
lb Maximum Input IN2 Clock Off 1 100 pA
Bias Current 400 p A
IN1 or IN1 a IN2 5 100 pA
40 " nA
h os Average Input Offset Drift th1 pNPt1
V|N1, VIN2 IN1 & IN2 InputVoltage min -200 0 mV
Range (Note 5) max +2.0 +0.5 v
VIN REF IN REF Input Voltage min - 200 0 mV
Range (Note 5) max +2.0 +0.5 v
VOUT REF OUT REF Input Voltage min - 100 mV
Range max +100 mV
PSRR Power Supply Rejection Ratio 120 dB
VOUT Integrator Output Voltage Range * 14 i 12 * 1 1 V
Vco Comparator Open-Drain Low (max) Sink Current = 1.0 mA 0.25 0.4 V
Output Voltage Range High (min) 25 20 , .
15+ Maximum Positive Supply Current AMET Low, 3.2 6.0 m A
TCLK = 50 H3 10.0
6990W'1
LMC669
Electrical Characteristics The following specifications apply for v+ = +15V, and v- = - 15V unless
otherwise specified. Boldface Ilmltu apply for Tum to Tu“; all other llmits TA = Tu = 25'C. (Continued)
Typlcal Tested Deslgn
Symbol Parameter Condltlons (Note 6) Llmlt lelt Unlts
(Note n (Note 8)
kr- Maximum Negative RESET Low, 2.0 5.0
Supply Current TCLK = 50 us T.0
ts Maximum Sample Rate RE§ET Low, Internal Clock 100 66.6 " kHz
fCLK Clock Frequency Flange min 100 1 00 Hz
max 1 00 1 oo kHz
TR Minimum At-mE I Pulse Width 80 150 1 " ns
VTH Digital Input T1, T2, High (min) 2.9 3.5 V
Threshold RE ET Low (max) 2.9 1.5 V
Voltage
CLK High (min) 3.5 4.0 V
Low (max) 1.5 1.0 V
In IN T1, T2, RE§ET, & CLK High 1.0 pA
Maximum Digital 1 At " A
Input Current
Low 1.0 pA
1.0 pA
Note I.. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and Ac electrical speCifTttations do not appty when operating
the device beyond its trpaeified operating conditions.
Note 2: All voltages are with respect to AGND.
Note 3: This input outrent will exist only when an Input Is driven to a voltage greater than (V+ + 0.2V) or less than -O.2V. It is due to internal diode clamps at the
inputs turning on. It the current is limited to 20 mA, the overdrive will not be harmful to the LMCSSB.
Note 4: The typical lunetion-to-amtyent thermal resistance (94A) of the 16 pin J package is 80’C/W.
Note 5: If input currents are limited, input voltages may be wiven beyond these limits and the device will still be functional. The comparator output will be correct as
long as the voltage on either the INREF pin or the two input IN1 A IN2 pins is between -200 mV and +2V.
Note tk Typicals are at 25'C and represent most likely parametric norm.
Note 7: Guaranteed and 100% tested.
Note 8: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note th The LMCBGBCD exhibits a warm-up drift of approximately 3 [N to 5 pl] in the negative direction. There are two factors that work together to cause this.
Firstty, as the die becomes warm, a temperature gradient forms between pin 2 and pins 1 and 16. Secondly, a thermocouple is created between the metal of the
Ieadframe and the metal of the wire (usually copper) used to connect the KI to a circuit It takes about ft minutes for the drift to stabil'ae. The N and M packages do
not exhibit this din because their Ieadframes are 90% copper.
Note Ith. Human body model, 100 pF discharged through 1.5 kn.
Typical Performance Characteristics
Posltlve Supply Current
CURRDleA)
B S S S
5:120V
VS=215V
Vs= 210V
-35 ~15 5 a 45 as as
mpzumnwc)
Vcoup OUT vs Temperature
vomcuv)
8 8 E g 8
-35 -15 s 5 45 lit) 5
TDPERATURSPC)
Integrator Summing Node
Leakage Current
'5 -15 5
25 45 as as
rmpmnmvc)
CLOCK FREQUENCY (KHZ) CURRENT (mA)
CLOCK FREQUENCY (KHI)
OUTPUT CURRENT(mA)
Negative Supply Current
41> y -:Iov
Vs=t15Vs-
V5: 22W
45 -1s ' a 45 as as
rwawunwc)
Clock Frequency "
Temperature
ct m.3c
s=210V
Vs=815V
Vs: l 2tW
-5 -15 5 25 45 85 as
mrmmnwc)
Clock Frequency vs
Temperature
=IDO pF
C1 F1th3C
VS=SWV
Vs=tISV
hr--""
-35 -15 s 25 45 as as
mmwch)
Output Current Limit
" Output Voltage
'strar= t 1 "
Ts=2se
SNKING CURRENT
-IS -10 -5 0 5 1O 15
OUTPUTVOLTAGHV)
CLOCK mmummmz) VOLTAGHV)
8’ 8 S g
CLOCK FREQUENCY (H1)
TLfH/85iM-3
T1, T2 & RESET thresholds "
sssiov
VS: ' 20Y
-35 -15 5 25 45 65 as
rtuvmmnwc)
Clock Frequency vs
Temperature
= 1000 pF
no. 30
V5=“°V
es=ttw
vsanov
-5 -ns 5 a 45 55 as
mmmmoc)
Clock Frequency vs
Temperature
=.l prF
Vs=t IOV
Vs=215V
Vs: 220V
-35 -15 5 a 6 65 85
TEMPmTURE(°C)
TL/H/8681-2
6990b“
LMCGGQ
Connection Diagram
16-Pin Dual-ln-Llne Package
m1: 1 V 13 31142
iNREFI: 2 15 :IAGND
AONDC 3 14 :leND
COMPOUTE 4 13 Cw'
0mm: 5 12 STI
CAPE 6 11 CIT2
00TPOTt2 7 IO 2fitzr
v‘: 8 9 Clout
TL/Hf856t-4
Top View
Order Number LM0669D
See NS Package Number D160
Pin Description LMC669 Numbers in ()are for 16-pin package
IN1, we
(1,16)
Description
These are the inputs to the Auto Zero's
comparator. They should be tied together
and connected to the summing node of the
host operational amplifier (op amp). One set
of inputs, either IN1 and IN2 or INREF, must
be between + 2 volts and ground while the
other can go to V+ (also refer to notes 3
and 5).
20-Pln Dualoln-Llne (N) Package
20-Pln Small-Outllne (M) Package
Mtt2 1 20 21 "
INREFI: 2 19 :AGND
AGNDI: 3 18 306140
ti.t.N2 4 17 :W
ctMtourt2 s 16 Cart
OUTREFC 6 IS ca T2
CAP: , 14 Cl AGND'
OUI’PUTC 8 13 :RESET
9 12 C3 CLK
IE TOGETHER‘
IO 11 cw-
TL/H/ase1-17
Top Vlew
‘These pins must be connected " shown to
ensure compatbility with future parts.
Description
This is the input for the tromparator's
reference voltage. Correction of Vos is
accomplished by connecting this pin to a
good clean system ground of its own. One
set of inputs, either IN1 and Mt? or INREF,
must be between + 2 volts and ground while
the other can go to V + (also refer to notes 3
and 5).
Pin Description 16-pin LM0669 (Continued)
(3,15)
COM POUT
OUTREF
OUTPUT
Description
These act to shield the INI, IN2, and
INFIEF connections from stray
capacitance and leakage which could
degrade the part's performance. They
should be connected to a high quality
ground.
Provides a separate ground for the
internal digital circuitry to prevent noise
from corrupting the comparator inputs.
It should have its own ground
connection.
This is the latched output from the
internal comparator. It is an open drain
which can be left unconnected if not
needed. Its response time is equal to
the sample rate's period. The rise time,
from 10% to 90%, is nominally 500 ns
with a 10 kfl pulI-up resistor. The output
is typically capable of swinging from
+ 0.25 (at 1 mA) to + 25 volts.
Output reference; for proper integrator
operation this input should be
connected to a good system ground,
such as the ground to which INREF is
connected.
This is the LM0669's integrator output.
it can swing from - 1 2 to + 12 volts in
0.2 volt steps with a 210 m load and
no external integrating capacitor.
When a capacitor is used to decrease
the correction voltage's step size, it is
connected between CAP and OUTPUT.
It parallels an internal 10 pF capacitor.
External clock input/internal adjust.
The frequency of the internal clock
(nominally 100 kHz) may be reduced
with an external capacitor or an
external clock connected to the CLK
input. The logic thresholds for this input
are 4 volts tor a logic high and 1 volt tor
logic low. The internal clock can be
stopped by applying a logic high,
through a diode, to the CLK input.
When a logic low is applied to the
diode, the internal clock runs freely.
(See Figure 3)
Comparator reset. At power-up. or
when FEET is pulled low during
normal operation, the Auto Zero will run
at its fastest sample rate. This allows
for the quickest Vos nulling.
Leave this pin unconnected.
Connect these pins together.
Connect to analog ground.
Pin Description
These pins select one of five clock
divider ratios. The ratio, hence the
sample rate can be changed by
applying V+ or ground to T1 and T2.
The ratio chosen by these inputs is
valid after the comparator's output
changes state; Le., a zero-crossing
between the offset and correction
voltage has taken piace. These inputs
can also be changed at any time to
modify the LMC669'e sample rate. Use
the table below to determine the
reduction in the clock’s frequency for
each combination of T1 and T2.
T1IT2 rt-E-s-ser} =.
(12,11)
1 1024
Positive and negative power supply
inputs. Typical supply voltages are * 15
volts, but operation will take place from
i 8 to i 20 volts. Power supply current
is typically 3 mA. Bypass capacitors
(0.01 - 0.1 pF) should be connected
to the power supply pins.
OO-‘AX
OAO-‘X
(13,8)
Application Hints
1.0 INTRODUCTION
in its standard application shown in Figure t, the LMC669
continuously samples the summing node of an inverting am-
plifier and generates a correction voltage for the amplifier's
non-inverting input, nulling the arnplifittr's input offset volt-
age (Vos) to 5 p.V. The offset correction is independent of
time. temperature, and supply voltage. The LMC669 elimi-
nates the need for initial or periodic offset adjustments.
compensates for Vos drift due to temperature changes, al-
lows the use of greater DC gain, and increases immunity to
changes in power supply voltages.
At the input of the LMC669 is a sampled-data differential
comparator with very low offset voltage. When the compar-
ator samples the summing node voltage and determines
that it is not at ground, the LM0669's output generates a
small voltage step in the opposite direction of the error. The
size of the step and the sample rate are user-selectable.
The correction voltage continues to step up or down until
the summing node is within the vos of the LMCtm--typi-
cally 5 pv. At this point the Auto Zero continues to monitor
the summing node and perform any needed corrections. An
internal divider generates five different sampling rates for
any given clock frequency.
The only external parts needed for Vos correction of most
amplifiers are two resistors and one capacitor. Since the
capacitor is in the feedback loop of an integrator, it should
be a low leakage type (polycarbonate, polypropylene, poly-
styrene, mylar, etc.). The tolerance of the resistors and ca-
pacitor is not critical (10% components are satisfactory).
6990W'I
LM0669
Application Hints (Continued)
-15VDC +15VDC
N.C. I TI
14 L, 13(10) 17(13)14
1 - --.-.
IO) IN: y RESET V+ COMPOUT
ll 2 CAP
( ) INREF LMC669 ourpur
1905) AGND 0mm
‘GND TI CLOCK T? DGND
Rin Rib
16 12 12 9 15 ll
9H") ( )NL () 1%,
TL/H/8561-5
FIGURE 1. Typical Application
1.1 CIRCUIT OPERATION
At the heart of the LMC669 is a four-stage precision sam-
pled-data comparator, shown in Figure 2 The circuit oper-
ates by successively zeroing the offset of each stage, re-
sulting in a very high gain amplifier with extremely low input
offset voltage.
After a comparator decision is made, the latch is enabled
and holds the eomparator's output state. At the same time
this state appears at COMPOUT. The latch also generates a
11V signal that charges capacitor th to , 1V. th's charge
is then transferred to the integrator's feedback capacitor Ca.
Since Cg is thm times larger than Co tt 200 mV step will
appear at the integrator's output. Further reduction of the
step size is possible with an external capacitor connected in
parallel with tk (between OUTPUT and CAP). The integra-
tor output is then attenuated by a resistive divider network
betore being applied to the external op amp's non-inverting
input, completing the offset correction loop.
1 .2 CLOCKS
In order to control the events that take place in the LMC669,
an internal Schmitt trigger oscillator generates a 100 kHz
clock. This oscillators frequency can be lowered by con-
necting a capacitor between the CLK input and ground as in
Figure 3c. It can also be overridden by applying an external
clock source (s 100 kHz) to the CLK input (Figure ao. Fur-
ther, the clock can be halted with a diode connected as
shown in Figure 3(b).
The clock signal drives the input of the divider (See Figure
a. Depending on the logic levels at inputs T1, T2, and
WE'S‘ET, the clock can be divided by five different ratios (1,
4, 16, 128, and 1024). The output of the divider triggers the
sequencer which controls the auto-zero function.
When the LMC669 is powered-up or reset the internal divid-
er automatically divides by one. This allows the Auto-Zero to
operate at maximum sampling rate so that large initial oft-
sets can be rapidly corrected. When the comparator toggles
for the first time, this indicates that input null has been
achieved and that maximum sample rate is no longer re-
quired. The latch then switches the dividertrom + 1 to the
ratio programmed via T1 and T2. By employing this "two
speed" approach the device can move quickly to handle
turn-on transients and then shift to the optimum "gear" for
long term offset correction. It is also possible to return to the
maximum sample rate via the REEF input so that non-
power-up transients can be dealt with as well.
1.3 INPUT RANGE
The lN1, IN2, and INREF inputs can accept signal levels
between 0 and +2 V. However, as long as both lN1 and
IN2, or INREF, is kept between 0 and 2V the other input (or
inputs) can be taken to V+ and, it input current limiting
(s; 20 mA) is provided, to W-. In most auto-zero applications
lN1 and ma will be able to go to these extended limits since
INREF will normally be grounded.
Application Hints (Continued)
SAMPLE!)
CEI-- COMPARATOR
MATRIX
‘I oumzr
INTERNAL " H -
EEF-r cum " iWllEtt ,
scoumcm
TL/H/8561-6
FIGURE 2. Block Diagram
CLOCK CLOCK CLOCK
12(9) 12(9)
12(9)!
J'LFLF'
100 " TO 100 Kht
ON J- Orr cT(pF)=CLOCK PERIOD (us)
l.o., 100 pF -lthbts
(b) (e)
TLlH/8561-B
FIGURE a Clock Input. External clock (a), controlling Internal clock (b), roduclng Internal clock frequency (0).
6990W'I
LM6669
Application Hints (Continued)
2.0 APPLICATION CIRCUITS
The most general application of the Auto-Zero is offset cor-
rection of an inverting op amp as shown in Figure t. The
example below shows how the integration capacitor and the
resistor divider are chosen.
Determine the maximum expected offset voltage from the
op amp characteristics and the requirements of the overall
system. The correction voltage swing capability should be
greater than or equal to this value. Also select the minimum
system resolution and the time that can be allowed to null
the initial offset. These will determine the correction voltage
step size. The magnitude of the correction voltage (Vcon)
and the step size (dv) are defined according to equations 1
and 2:
Correction voltage = Voorr = Vout-ii-Ari-i,- + R
Vo is typically 1121/ tor I15V supplies.
R, Vcon
(V0 - Vcorr)
- 10K Vcorr
- (12 - Voorr)
Ra = (la)
for R, = 10 kn (For proper operation R1 + Fig should
be greater than 10 kn.)
' - - s,,?,-:-,) (_R2_)
step Size dv 1.0V (t + C R, + R2 (2)
- C1R2 _
tivift, + Fig) C2 (2a)
with c, = 2 pF, tht = 10 pF, R, and R; from Eq. 1a.
c, and C2 are internal.
A further consideration regarding the selection of step size
is resolution: the magnitude of the smallest significant sig-
nal. In the case of nulling the Vos of an op amp used with a
digital-to-analog converter (DAG) the smallest signal is the
voltage produced by the least-significant bit (LSB). There-
fore, the correction voitage's step size would need to be
much smaller than the magnitude of the DAC's LSB in order
to retain the DAC's desired resolution.
Finally, for proper operation, the sampling period should be
longer than the amplitier's settling time. 10 p.s or more
should be adequate for most contemporary amplifiers.
DESIGN EXAMPLE
As an example. assume that the offset of the op amp in
Figure t is expected to be no more than " mV and the
system can tolerate a 1 PV square wave at a rate equal to
the internal clock. Begin by using R1 and Rato set the maxi-
mum correction voltage to 15 mV. The LMCGGB's output
can swing to A12 volts with a 10 Kn load and a i 15 volt
power supply. R, and R2 should be chosen to reduce this to
R, VCOIY
Vo - Veorr
= (10K)(0.015)
(12 - 0.015)
= 12.5tt 1Tf, 130
for i15V supplies and R1 = 10K.
Now choose C. the integrator's external feedback capacitor,
to set the final step size to 1 PW. Using equation (tta):
- c, R2
-itvtrjirhT)
with R1 = 10 kn, R2 = 130. th = 2pF,
and Ce = 10 pF, yields
C a 2500 pF
The null time for this example, with an amplifier offset of 15
mV, step size of 1 pV, and initial sample rate of 100 kHz, is
.___&_ (3)
(dv)(sample rate)
= 150 msec
it this is too slow, the step size can be increased.
OP AMP INPUT BIAS CURRENT
Input bias current should be considered when selecting an
op amp that is nulled by the LMC669. if this current Is too
high, the result is a significant voltage drop across the teed-
back components and consequent output offset. The Auto
Zero will not correct this error since it does not appear as a
voltage at the summing node. Therefore, use low resistance
teedback networks. or op amps with low input bias current
such as the LF156, LF400, and LF411.
Through tareful selection of the sample rate and step size a
compromise can be made between noise and null time. Low
sample rates achieve low noise but take a long time to null
an offset or correct it when a sudden change occurs. High
sample rates can quickly null or correct changes in Vos but
do so with an increase in noise. Step size directly affects the
null time and the amount of noise introduced: small step
sizes (< 100 nV) contribute almost no noise, but result in
long null times.
Low noise LMC669 applications are beneficial to instrumen-
tation and audio electronics. An LM833 low noise operation-
al amplifier (4.5 W lt/H_z) with the LM0669 is shown in
Figure 4. In this circuit the Auto Zero adds only 1 W / WE
referred to the amplifier’s input. To achieve this the step
size is set to 100 W. The sample rate, with the internal
clock free-running, is set to 98 Hz (clock frequency +
1024). and input and output filters are added to the
LMC669. The input filter prevents switching transients from
reaching the amplifier input and the output filter attenuates
AC components of the steps at the Auto Zero's output. The
filter at the op amp's input also introduces a pole at
F = _1,_.,
P 277mm + Rt)Ct
Null time ==
and a zero at
1 amp,
The maximum Vos that can be corrected by the circuit in
Figure 4 is 12 mV. More offset correction am be obtained
while retaining good noise performance by increasing the
size of R2 and C the same percentage. Increasing C com-
pensates for the reduced attenuation caused by increasing
R2. This allows the step size to remain the same but in-
creases the amount of correction voltage applied to the op
Application Hints (Continued)
-15VDC
+15VDC
N.c. 'l TI,
l, 11(a) 13(10) 17(13) 14
1mm 1 Y" RESET v‘ COMPOUT
2Mm)m2 thp
.1ur tk 2( )INREF Lucssa outpu1
T ci-Sl, AGND cums
"? T1 CLOCK 12 t)tmo
15(11)
16(12) |12(9)
l8 14) l,
5.1 kn
5.1 kn I .1 pr
FIGURE 4. Low Noise Application
1500 HSVDC
It(8) 1300)
17051}
1(1) IN!
19(15)
It" RESET
LMCGSS
TI CLOCK
V‘ couPour
OUTPUT
OUTREF
15(12) |12(9) l15(11)
N.C. +I5VDC
TL/H/8561-0
FIGURE ti. Zeroing LM1875 Power Op-Amp
TUH/8561-10
6993W'I
LMCGSQ
Application Hints (Continued)
POWER AMPLIFIERS
For applications such as motor control, automated servo
systems, and power amplification the LMC669 can also be
used with amplifiers other than standard small signal op
amps. Figure 5 shows how the Auto Zero can allow an
LM1875 audio power amplifier to operate with very low off-
set. While the sample rate for this configuration is not crit-
ical, the LMC669's output step size should be set for less
than 1 wi/ to ensure low system noise.
NON-INVERTING AMPLIFIERS AND SYSTEMS
A variation of the above circuit appears in Figure 6 with the
LMC669 operating as a DC-servo integrating feedback loop.
This configuration is applicable when the Auto Zero is used
with non-inverting op amps amplifying AC-only signals. The
output error of the amplifier is reduced to the Vos of the Auto
Zero, typically 5 pV. A filter at the input of the LMC669 limits
current and ensures that only DC and very low frequencies
-15VDC
N.C. i [
l4 L, 1300) tr0s) R;
(< 0.6 Hz) are sampled. In this application the output of the
op amp is sampled and compared with a reference ground.
The correction output from the Auto Zero now replaces the
ground reference for the feedback resistor connected to the
inverting input.
Systems can also benefit from the Auto Zero. Figure 7
shows how the Vos of an MF6 Butterworth low-pass
switched capacitor filter is nulled by the LMC669. The Auto
Zero's IN1 and IN2 inputs are connected to the MF6's out-
put while INFtEF is connected to its input. The correction
signal is applied to the MF6's Vos ADJ input. RC low-pass
filters (rm, ct, and Re, tha) are used to reduce AC signals
at the LMC669's inputs and provide current limiting. It is
important to set each passive RC filter's cutoff as low as
possible, at most 0.1 of the MF6's to.
This correction makes the MF6 useful in applications calling
for good DC accuracy. The MF6's typical 250 mV offset is
decreased to 5 p.V with a step size of 1 p.V.
+15VDC
f COMPOUT Ji-(A.c.
CAP (6) |CZOOp
ourpur 8(7)
OUTREF 6(5)
mo 1804)
m 1 If" RESET
INREF Lucsss
“m n CLOCK
1602) |12(9) Iism)
N.C. 915VDC
It, 10m
R2 won
TL/H/856t-11
FIGURE 6. DC Servo Loop
Application Hints (Continued)
~15voc +15voc
N.C. i
l‘ L, 13(10) 17(13) Fl;
LMCGSS
V” COMPOUT _ - N.C.
7 c .068 r
CAP C-l'." JI
OUTPUT
OUTREF
T2 DGND
16(12) |12(9) 1501)
m l +15voc
R, 10 m
2l ul -5voc
VOUTZ INY2 10
V- J3 sson
r 6 OUT y
M - 12
L.SH out
vos AN tmo
vow: mv1 CLKR
" 13 I n l m LEVEL
TL/H/8561-12
FIGURE r. Auto zeroing a system. In this case the 250 mV offset
ot a swltched-capacltor low-pese filter is corrected by the LMC669.
MAINTAINING DAC LINEARITY
The LMC669 is particularly useful for zeroing the offset of
an op amp used with a CMOS digital-to-analog converter
(DAC). For good linearity the DAC's two outputs (lout and
750 must be connected to identical ground potentials. The
presence ot op amp Vos (and its drift due to temperature)
will degrade the DAC's linearity. Even though the effects of
Vos can be corrected by trimming. a static trim will not be
very helptul if the Vos changes with respect to temperature.
Figure 8 shows the DAC1208 with a 10V reference driving
an LF357. The linearity of this DAC will degrade by 0.01 %
for each millivolt of op amp Vos. Therefore, the LF357's
typical offset of 5 mV will turn the 12-bit DAC1208's 0.012%
linearity error into 0.062%. What was a 12 bit linear device
now has only 9 bits linearity. The original linearity specifics
tion can be retained by connecting en LM0669 to the inputs
of the LF357, rendering the non-Iinearity due to Vos and
temperature drift negligible. The DAC is now able to operate
at its published linearity specifications independent of Vos
and temperature.
Figure g shows the schematic of a unipolar power DAC.
One use of the power DAC is as a digitally controlled power
supply having the ability to sink current. in the case of induc-
tive loads, as well as source current. The linearity of the
DAC is preserved by the nulling action ot the LMC669 con-
nected to the inputs of the LM1875 power amplifier. The
amplifier can generate an output voltage from 0 to 25 volts
and a maximum current of 3 amperes. The actual output is
determined by
--Vret (D)
CD" is tho value of the digital code, base 10). The magni-
tude of each step is
Vout =
lvretl
Stable operation of the LM1875 is ensured by the RC com-
bination connected to the inverting input.
LM0669 AS A COMPARATOR
The LMC669's operation as a comparator is shown in Fig-
um tll Its input impedance is 5 kit with 160 pF to ground.
For proper operation as a comparator lN1 and ma. or IN-
REF, should be kept between 0 and 2V while the other input
(or inputs) can be taken to V+. If input current limiting
(s20 mA) is provided, the inputs can also go to V‘. (In
addition, please refer to notes 3 and 5 under "Electrical
Characteristics".)
The open collector output can be pulled-up to typically 25
volts. When the sink current is 1 mA the output can pull-
down to 0.25V. Outputs closer to ground are possible with a
larger pullup resistor.
6990!“
LMC669
Application Hlnts (Continued)
-1svoc +15voc
N.C. _ !
I; 11(8) 13(10) 17(13) 14
1 tlt -
( ) MI g'" RESET V’ COMPOUT
m 2 CAP
tuner LMCGGS OUTPUT
AGND oumzr
limo TI CLOCK T2 OGNO
" '10 16(12) |12(9) 15(11)
N.C. +15VDC
I FS. ADJUST 5011
It I 2°93.
-2ov TO +201! "T"
O vers RFB IOUT - L351 Von!
:iiiiirsii) memos |___‘ .
sun sun our
TL/H/Moo-"
FIGURE 8. Reducing V°.-lnduced llnearlty errors In a 12-bit DAC by 0.01% lmv omot.
1????[77
mm T1 T2 RESET v’v’ DGND
INREF Lucsss
IN 1 W
IN 2 COMPOUT cuxht
-20V T0 OZOV
o-- VREF Rn, bur --o--
comm. 0AC1208 - -r"'-
GND GND
FIGURE 9. Power DAG with t 20Vrr, and 3A output capabilities.
TL/HlBSB1-14
Application Hints (Continued) “me
LOW-FREQUENCY, HIGH-GAIN AMPLIFIER
For applications that require precision high-gain DC and
~15VDC
Iow-frequency performance. the LMC669 can be connected ' tP
as an amplifier as shown in Figure tt. For a closed-Ioop . L m 1 f RESET y" coupom Your
galn of - 1000 the useful frequency range Is typically v
Hz m- R, - m 2 w -
Fmax - ao-rr-_-- o-MN- mas? M889 tMNT -
mV of step size
AGND OUTREF
Mt10 T1 CLOCK T2 noun sl,
I I l T
TUH/BSM -10
"R - 10K. For Inputs greats: man 2 volts.
FIGURE 10. Low-Spood Proclolon Comparator
J11 1 "
AGND LMCSSS
FIGURE 11. Low Offset, High Gain,
Low Frequency Op Amp.
Bandwidth " 2oaraarpTiip “M tattt - too ue.
TL/H/8561-15
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
LMC669CCM - product/lm0669ccm?HQS=T|-nu|I-nuIl-dscataIog-df-pf-null-wwe
LMC669BIN - product/lm0669bin?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nulI-wwe
LMC669D - product/Imc669d?HQS=TI-nulI-nulI-dscatalog-df—pf—nuII-wwe
LMC669CIN - product/Imc669cin?HQS=T|—nuII-nu|I-dscatalog-df-pf-nulI-wwe
LMC669CIM - product/Im06690im?HQS=Tl-null-nulI-dscatalog-df-pf-nuII-wwe
LMC669CD - product/lm06690d?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
LMC669CCN - product/ImcGGQccn?HQS=T|—nu||-nu|I-dscatalog-df-pf-null-wwe
LMC669BCM - product/Imc669bcm?HQS=TI-nu|I-nu|I-dscatalog-df-pf-nulI-wwe
LMC669BIM - product/Im0669bim?HQS=Tl-nu|I-nulI-dscatalog-df-pf-null-wwe
LMC669BCN - product/ImcG69bcn?HQS=T|-nu|I-nulI-dscatalog-df-pf-nulI-wwe
