LM604ACN ,4 CHANNEL MUX-AMPElectrical Characteristics vs”...LY = * 15V (Note 3)
LM604AC
LM604AM LM604I LM604C
Parameter C ..
LM604CM ,4 CHANNEL MUX-AMPBlock Diagram
A CHANNEL SELECTION
B AND BI-STATE
DIGITAL GROUND OUTPUT CONTROL
FOUR
SEPARA ..
LM604CN ,4 CHANNEL MUX-AMPElectrical Characteristics vSUPPLY = i15V (Note 3)
LM604AC
LM604AM LM604I LM 6 0 4 C
Parameter ..
LM60BIM3 ,2.7V, SOT-23 Temperature SensorElectrical CharacteristicsUnless otherwise noted, these specifications apply for +V = +3.0 V and I ..
LM60BIM3X ,2.7V, SOT-23 Temperature SensorGeneral DescriptionThe LM60 is a precision integrated-circuit temperature sen-
LM60CIM3 ,2.7V, SOT-23 Temperature SensorFeaturesn Nonlinearity: ±0.8˚C (max)n Calibrated linear scale factor of +6.25 mV/˚Cn Output Impedan ..
LP3470IM5X-4.63 ,Tiny Power On Reset CircuitFeaturesvoltage (V ) options: 2.63V, 2.93V, 3.08V, 3.65V, 4.00V,RTH4.38V, and 4.63V. If other volta ..
LP3470IM5X-4.63 ,Tiny Power On Reset CircuitElectrical CharacteristicsLimits in standard typeface are for T = 25˚C, and limits in boldface type ..
LP3470IM5X-4.63 ,Tiny Power On Reset CircuitElectrical CharacteristicsLimits in standard typeface are for T = 25˚C, and limits in boldface type ..
LP3470IM5X-4.63 ,Tiny Power On Reset CircuitElectrical CharacteristicsLimits in standard typeface are for T = 25˚C, and limits in boldface type ..
LP3470IM5X-4.63 ,Tiny Power On Reset CircuitLP3470 Tiny Power On Reset CircuitSeptember 2000LP3470Tiny Power On Reset Circuitn Custom Reset Thr ..
LP3470M5-2.63 ,Tiny Power On Reset CircuitFeaturesvoltage (V ) options: 2.63V, 2.93V, 3.08V, 3.65V, 4.00V,RTH4.38V, and 4.63V. If other volta ..
LM604ACN-LM604CM-LM604CN
4 CHANNEL MUX-AMP
National
Semiconductor
LM604 4 Channel Mux-Amp
General Description
The LM604 Mux-Amp is an op-amp with four selectable dif-
ferential inputs, combining the functions of a multiplexer
with an op-amp. The LM604 can select, buffer, and amplify
one of four different input signals, providing a complete sys-
tem for multiplexing analog signals. It also has the unique
Bi-State output which allows two or more Mux-Amps to be
connected together at their outputs to increase the number
of multiplexed channels. Channel selection and the Bi-State
output are controlled by internal logic that interfaces directly
to a microprocessor. Besides these unique features, the
LM604 has excellent AC and DC op-amp specifications and
is internally compensated.
Applications include signal multiplexing and linear circuits
that are controlled by digital signals (i.e., programmable gain
blocks, filters, and other op-amp circuits).
Features
a Multiplexes four differential input channels to a single
op-amp
n Easy to interface to microprocessor, or operates "stand
alone"
" Bi-State output: Operates in two states, Active and Dis-
abled. When disabled, it becomes a high impedance.
n Wide operating voltage range
single supply 4V to 32V
split supply i2V to i16V
a Wide input common mode range V' to V+ - 1V
ll Fast channel to channel switching time 5 11.8
n Output will drive a 6000 load
Block Diagram
A CHANNEL SELECTION
8 AND BI-STATE
DIGITAL GROUND OUTPUT CONTROL
SEPARATE
DIFFERENTIAL
CHANNELS
SECOND STAGE AND
Bl-STATE OUTPUT
Channel Selection
- A B R c-s Channel
TR 0 0 0 0 1
- 0 1 0 0 2
cs 1 o o o 3
1 1 0 0 4
X X X 1 Unchanged
X X 1 X Unchanged
Bi-State Output Control
voor ttN w-rt Tsg Output State
0 0 0 Enabled
1 0 0 Disabled, High Z
X X 1 Unchanged
X 1 X Unchanged
TL/H/9131-10
Order Number LM604AMJ, LM604IJ, LM604IN, LM604ACN, LM604CN, LM604ACM, or LM604CM
See NS Package Number J18A, MBA or M208
VOQW'I
Absolute Maximum Ratings
If Mllltary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrlbutors for avallabillty and specifications.
Supply Voltage 36V or i 18V
Differential Input Voltage i Supply Voltage
Input Voltage Range i Supply Voltage
Output Short Circuit to Gnd Continuous (Note 1)
ESD Tolerance (CZAp = 120 pF,
RZAP = 15000) 2,000V
Lead Temperature (Soldering, 5 sec.) 300'C
Storage Temperature Range -65''C to 150°C
Operating Ambient
Temperature Range
LM604AM -55'C s TA s; 125°C
LM604I -40"C s: TA s 85°C
LM604AC, LM604C ty'C s; TA s; 70"C
J Pkg. M Pkg. N Pkg.
Power Dissipation (Note 2) 1,600 mW 1,500 mW 1,900 mW
TJMAX 150°C 150°C 150°C
0 JA (Typical, 75°C/w 83°C/W 65°C/W
Board Mounted)
DC Electrical Characteristics Vsuppu = i15V (Note 3)
LM604AC
LM604AM LM604I LM 6 0 4 C
Parameter Conditions Typlcal Tested Design Tested Design Tested Design U-nlts
Llmit Limit Llmlt leIt Limit Limit tLimit)
(Note 4) (Note 5) (Note 4) (Note 5) (Note 4) (Note 5)
lnputOffsetVoltage Rs = 10 kn LM604 1.0 3.0 5.0 3.0 5.0 mV
Nos) LM604A 0.5 1.0 1.0 3.0 (Max)
vos Temperature 5.5 pV/°C
Input Offset Current 2 10 10 1 2 10 1 2 nA
(los) 1 2 (Max)
los Temperature 10 pA/°C
Input Bias Current LM604 50 80 1 oo 80 1 oo nA
(IB) LM604A 30 50 50 80 (Max)
IB Temperature 55 pA/°C
Input Common Upper Limit 14.0 13.5 13.5 1 3.0 13.5 13.0 V
Mode Voltage 1 3.0 (Min)
Range Lower Limit --15.0 --15.0 -15.0 - 1 5.0 - 15.0 - 1 5.0 V
- 1 5.0 (Max)
Input Resistance 1.0 Meg n
Output Voltage RL = 10 kn Upper Limit 13.4 13.0 13.0 1 2.5 13.0 1 2.5 V
Swing 1 2.5 (Min)
Lower Limit -14.2 -13.8 -13.8 - 13.3 -13.8 _ 13.3 V
- 1 3.3 (Max)
RL = 6000 Upper Limit 12.7 12.3 12.3 10.0 12.3 1 0.0 V
1 0.0 (Min)
Lower Limit - 12.6 - 12.2 - 12.2 - 1 1.7 -12.2 - 1 1 .7 V
- 1 1.7 (Max)
Large Signal VOUT = i10V RL = 2 kft 200 50 50 " 50 " V/mV
Voltage Gain " (Min)
RL = 6000 200 50 50 " 50 "
Common Mode VCM = -15.0Vto 13.5V 100 80 80 TO 80 " dB
Rejection Ratio TO (Min)
1 -348
DC Electrical Characteristics vsu...LY = 115v (Note 3)
LM604AC
LM604AM LM604I LM604C
Parameter Condltlons Typical Tested Design Tested Design Tested Design P"?
Limit Umit Limit Limit Limit Limit (Limit)
(Note 4) (Note 5) (Note 4) (Note 5) (Note 4) (Note 5)
Power Supply VsuppLy = * 5.0V to 116.OV 100 80 80 " 80 TO dB
Rejection Ratio TO (Min)
Output Short Circuit i 35 i 50 , 50 i 60 i 50 i 60 mA
Current t 60 (Max)
Output Leakage VOUT = -13.5V to 13.OV 4.0 10.0 10.0 20.0 10.0 20.0 MA
Current Bi-State Output Disabled 20.0 (Max)
Output Capacitance Bi-State Output Disabled 10 pF
See Figure 1
Suppty Current 7.0 9.0 9.0 1 0.0 9.0 1 0.0 mA
1 0.0 (Max)
AC Electrical Characteristics VSUPPLY = 21:15V(Note 3)
LM604AC
LM604AM LM604I LM604C
Parameter Conditions Typical Tested Deslgn Tested Design Tested Design (Limit)
Limit Umit Limit Llmlt Limit Llmit
(Note 4) (Note 5) (Note 4) (Note 5) (Note 4) (Note 5)
Slew Rate AV = 1, RL = 2 kn 3.0 2.0 2.0 1.5 2.0 1.5 V/ps
1.5 (Min)
Gain Bandwidth f = 100 kHz 7.0 6.0 6.0 3.0 6.0 3.0 MHz
Product 3.0 (Min)
Unity Gain 3.0 2.5 2.5 2.5 MHz
Frequency (Min)
Phase Margin Ru = 2 kn, CL = 200 pF 50 Degrees
Settling Time to AV LTA: -1,Vour = --5.0V to 5.0V 4.0 us
0.1% of Final Value RL = 2 kn
Channel Switching See Figure? tsw1 4.0 5.5 5.5 6.5 5.5 6.5 ps
Time 6.5 (Max)
tswg 5.0 6.5 6.5 6.5
Channel to Channel Rs = 10 MM = 10 kHz 100 dB
Isolation " = 10.0Vp.p
Input Noise Voltage Rs = 100 n,t = 1 kHz 20 nV/JFIE
Input Noise Current f = 1 kHz 0.3 pA/JE
Mux-Amp Enable See Figure 3 tam 3.0 4.0 4.0 5.0 4.0 5.0 ps
Time 5.0 (Max)
tEN2 4.0 5.5 5.5 5.5
Mux-Amp Disable See Figure 3 1.0 2.0 2.0 3.0 2.0 3.0 03
Time (tas) 3.0 (Max)
DC Electrical Characteristics vSUPPLY = 5V (Note 3)
LM604AC
LM604AM LM604I LM 6 0 4 C .
Parameter Conditions Typical Tested Design Tested Design Tested Design (Limit)
Limit Limit Limit Limit Limit Limit
(Note 4) (Note 5) (Note 4) (Note 5) (Note 4) (Note 5)
lnputOffsetVoltage Rs = 10 kn LM604 1.0 3.0 5.0 3.0 5.0 mV
VOUT = 2.0V LM604A 0.5 1.0 1.0 3.0 (Max)
lnputOffsetCurrent VOUT = 2.0V 3.0 10 10 " 10 " nA
" (Max)
Input Bias Current VOUT = 2.0V LM604 70 130 150 130 ISO nA
LM604A 50 80 80 1 1 o (Max)
InputCommon VOUT = 2.0V Upper Limit 4.0 3.5 3.5 3.0 3.5 3.0 V
Mode 3.0 (Min)
Voltage Range Lower Limit 0 O 0 o 0 o
Output Voltage RL = 10 kn Upper Limit 3.5 3.2 3.2 3.0 3.2 3.0 V
Swing 3.0 (Min)
Lower Limit 0.5 0.7 0.7 0.8 0.7 0.8 V
0.8 (Max)
HL = 600n Upper Limit 3.3 3.0 3.0 2.8 3.0 2.8 V
2.8 (Min)
Lower Limit 0.4 0.6 0.6 0.7 0.6 0.7 V
0.7 (Max)
Large Signal VOUT = 0.8V RL = 2 kft 200 50 50 50 V/mV
Voltage to 2.8V " " " (Min)
Gain RL 6000 200 50 50 50
Common Mode VCM = 0V to 3.5V 100 80 80 TO 80 TO dB
Rejection Patio VOUT = 2.0V TO (Min)
PowerSupply V+ = 4.0V to 5.0V 100 80 80 TO 80 TO dB
Rejection Ratio VOUT = 2.0V TO (Min)
DISABLED
' vour
IKST=t100M TL/H/913t-3
TL/H/9131-2
COUT = - X 100 MA
FIGURE 1. Output Capacitance Test
Digital Input Electrical Characteristics vsupm = i15V (Note 6)
LM604AC
LM604AM LM604I LM604c
Parameter Conditions Typical Tested Design Tested Design Tested Design (leu)
Umit Limit lelt Llmit Umlt lelt
(Note 4) (Note 5) (Note 4) (Note 5) (Note 4) (Note ti)
VNH. 1.8 1.8 2.0 1.8 2.0 v
2.0 (Min)
VINLO 1.0 1.0 0.8 1.0 0.8 V
0.8 (Max)
leon 5.0 5.0 t 0.0 5.0 1 0.0 [AA
qo.o (Max)
1mm 5.0 5.0 1 0.0 5.0 1 0.0 ps/N
1 0.0 (Max)
Minimum Pulse 1 oo 1 oo 1 oo ns
Width for wn & cs (Min)
Minimum Set-Up See Figures 3 and 5 1 oo 1 oo t oo ns
Time (ts) (Min)
Minimum Hold See Figures 3 and 5 50 so BO ns
Time (tH) (Min)
Input Capacitance 5 pF
Note 1: Applies to both single and split supply operation. Continuous short circuit operation can result in exceeding the maximum allowed junction temperature.
Note 2: When operating at TA > 25'C, the maximum power dissipation must be derated based on '
Note P. Unless spacitied otherwise, all limits are guaranteed tor TA = TJ = 25°C, VcM = 0V, Vow = OV, and Rt. > 1Megn. Boldtace limits apply at
tPC S Tu S 70°C for LM604AC and LM604C, -40'C g TJ S 85''C for LM604l, and -55''C S T., 125''C tor LM604AM.
Note 4: Guaranteed and 100% production tested.
Note 5: Guaranteed but not 100% production tested. These numbers are not used to calculate outgoing quality levels.
Note 6: Unless specified otherwise, all units are guaranteed at TA = T J = 25'0. Boldface 1imits apply at the junction temperature extremes specified in note 3.
input voltage levels are with respect to digital ground (pin 4) which must be at least 4.0V below V1.
Switching from Channel 1
to 2 with Channel Select
preset to M before W = 4 m
0. This test applies to all -w o-NM,
channels.
TL/H/9131-4
-ift l
to.” or lily
-5.ov k
TL/H/9131-S
FIGURE 2. Channel Switching Tlme Test
ANT INPUT
CHANNEL
v ‘Ovom
TL/H/9131 -8
hrs (10v) ENI tas
VEN(ov) ,qov. or 10v
TL/H/9131-9
FIGURE 3. Bl-State Output Enable
and Disable Time Test
Typical Performance Characteristics (Note 7)
INPUT ems cunnzmnA)
OUTPUT VOLTAGE SWING (VP-P)
COMMON MODS REJECHON RAT10(dB)
OUTPUT VOLTAGE SWING (VP-F)
Input Bias Current vs
Input Common-Mode Voltage
-15 -10 -5 o 5 IO 15
cowon-uon: VOLTAGE (V)
Output Voltage Swing
vs Supply Voltage
RL=10K
o 5 10 15 20 25
SUPPLY VOLTAGE(:V)
Common-Mode Rejection
Ratio vs Frequency
80 'ss
w- , v)ss.
40 2K N.
CM v.)
20 - WRR=0FD4 LOOP GAIN-ZO un..-"-,
1 1 1 1 Ftat
10 100 lk 1tht 100K m ttht
FR£0UENCY(H2)
Undistorted Output Voltage
Swing vs Frequency
Rt =2K
10 Av =1
DISTORTION <1:
1K 10K 100K
razoumcvwz)
OUTPUT VOLTAGE SWING (VF-F) INPUT BIAS CURRENT (HA)
POWER SUPPLY REJECTION RATIO (d8)
015701111011 (7:)
Input Bias Current
vs Temperature
0888888388§
-75-50-25 0 25 50 75 100125150
TEMPERATURE(°C)
Output Voltage Swing
vs Output Load Resistance
RL- OUTPUT mum)
Power Supply Rejection
Ratio vs Frequency
-so PPLY
1K 10x 100K
FREQUENCYGII)
Distortion vs Frequency
0.1 75
0.1 50
0.1 25
tlt Itht
racoumcv (H1)
OUTPUT IMPEDANCE (n) POSITIVE COMMON MODE INPUT VOLTAGE LIMIT(V) SUPPLY CURRENT (mA)
EQUIVALENT INPUT NOISE VOLTAGE (nV/lni)
Supply Current
vs Supply Voltage
o 5 10 15 20 25
SUPPLY VOLTAGE (tV)
Upper Common-Mode Voltage
Limit vs Positive Supply Voltage
- 51A 125°C
SUPPLY vomcuv)
Output Impedance
vs Frequency
100 1K 10K 100tt 1M
FREQUENCYWZ)
Equivalent Input Noise
Voltage vs Frequency
10 100 1K ttht 100K
nlE00CNCr(Hz)
TL/H/9131-6
Typical Performance Characteristics (Note7)
Equivalent Input Noise
Current vs Frequency Positive Current Limit
T? "it? "ii.'
= L' g
'"s - -
3 1 it a
t i' ld
g; F-' F-'
x 4 -l
u 0.1 's 's
o 5 10tli20253035404550
razoumcvmz) OUTPUT souncz CURRENTOM)
Slew Rate vs Temperature Bode Plot
4 A -1 9
3L=2K m.--)-"""" it
FALLING --- x
g: 3 I /RISING g E
it f Iii A' 3
gl k v a
g / z E t',
E 2 o'?, 'g
-so -25 o 25 so 75 100 125
TEMPERATUREPC) ntttyltNCr(uwz)
Unity Gain Frequency
Negative Current Limit
o 5101520253055401550
ouwur smx CURRENT(rnA)
Inverter Settling Time
vs Output Voltage Swing
10 RL =2K
o 1 2 5 4 s s
scmmcnusm)
vs Temperature Open Loop Voltage Gain
'iii" 49 RL = 2K - g
tg M N. 8
il) 30 :?,, lim
E "s, t
6 25 's o
t N p,
y, M §
-7S-50-25 0 25 5O 75 100125150 0 5 10 15 20
TEMPERATUREPC) SUPPLY VOLTAGE(3:V)
Note 7: Unless specified otherwise, TA = T J = 25''C, VS = +-15V, VCM = 0V, VOUT = OV, and RL > 1 Meg.
TL/H/9131-7
Connection Diagrams
" Pin DuaMn-Llrte Package
- A tii
- a WR
- OPEN PIN c‘s
-- DIGITAL GND It"
- V. Your
- - CHANNEL CHANNEL -
-. I 4
- - CHANNEL CHANNEL - -
-. 2 3
Timing Diagrams
CHANNEL 1
CHANNEL 2
ii = LOGIC o
TL/H/9131-25
FIGURE 4
20 Pin Small Outline Package
- A Fr;
- a W?
- OPEN PIN c’s
- mcrm GND v"
- W Vour
- - CHANNEL CHANNEL -
-- OPEN PIN OPEN PIN
- CHANNEL CHANNEL -
TL/H/9131-26
Wt 2fj7 's. ts / gm
A>ESSS§ / h N
a (TiTI 2%
FIGURE s. Channel Switching Timing Diagram
TL/H/9131-11
Functional Description
INPUT CHANNEL SELECTION
The LM604 contains four differential input channels that are
selected one at a time. An input is selected by writing its
binary code to pins A and B when CS" and w-n are a logic 0,
see block diagram. The LM604 always has one of its inputs
selected. In order to isolate all four channels from the out-
put, the Bi-State output can be disabled.
Figure 5 illustrates how the LM604 switches from one chan-
nel to another. The switching begins on the falling edge of
W if A and B are valid before W? is a logic 0, or when A
and B become valid while WA" is a logic 0. In either case, the
channel switching time (tswg) remains the same. It a chan-
nel is to remain selected, its binary code must be valid dur-
ing the rising edge of W as specified by ts and tH.
Channel switching time is specified by tsw1 and tswg as
shown in Figure 2. tsw1 is the time it takes the output to first
reach its new value, and tsw2 is the time it takes the output
to settle to within 0.1% of its new value. Clearly, tswg is a
more useful parameter for specifying switching time, but it is
difficult to test on a production basis. Therefore, tsw1 is
tested and this allows tsw2 to be guaranteed. Channel
switching time will vary as a function of how far the output
swings to reach its new value. This is shown in Figure 6
where tswg is plotted as a function of output voltage swing
(AVourl-
AVOUT (V)
tswa (ps)
TL/H/9131-12
AVOUT = Voor (Selected Channel) - VOUT (Previous Channel)
FIGURE 6. tsw2 VS AVOUT
Bl-STATE OUTPUT
The Bi-State output can be either enabled (on) or disabled
(off). When disabled, the output becomes a high impedance
load that can be driven by another output stage. This allows
several Mux-Amps to be connected together at their outputs
by having only one output enabled at one time. Thus, sever-
al Mux-Amps can be in parallel to the same output to in-
crease the number of multiplexed channels. The Bi-State
output is controlled by m when a and WA are a logic 0,
see block diagram.
When the output is disabled and driven by another output, it
behaves like a small capacitive load with a few microamps
of leakage current. The data sheet specifies this with the
parameters "Output Capacitance" and "Output Leakage
Current", Both parameters vary with temperature, as shown
in Figure F.
'ii " -
a -3 //
-75 -50-25 0 25 50 75 100125150
TEMPERATURE Pc)
TL/Hf9131-13
COUT (PF)
-75-50-25 0 25 50 75 100125150
TEMPERATURE (e)
TL/H/9131-14
FIGURE 7. ILEAKAGE and Cour vs Temperature
Figure 8 illustrates switching between two Mux-Amps that
are connected in parallel to the same output. Switching be-
gins on the falling edge of wm if the EN signals are correctly
set before W is a logic 0, or when the W signals become
valid while W is a logic 0. The Bi-State output takes less
time to become disabled than it does to become enabled,
and this insures the outputs are switched in a "break before
make" method. If an in output is to remain enabled or dis-
abled after WT; becomes a logic 1, m must be valid during
the rising edge of WTI as specified by ts and tH. Note that
when a Mux-Amp has its output enabled, the binary code for
the selected input channel must also be written.
Bi-State output enable time (tgm and tENg) and disable time
(tDIS) are defined in Figure 3. tEN1 is the time it takes the
output to first reach its enabled value (VEN), and tEN2 is the
time it takes the output to settle to within 0.1% of VEN. As
with channel switching time, tEm is a tested parameter that
allows 1EN2 to be guaranteed. tas is the time it takes the
output to become a high impedance. Output enable time will
vary according to how far the output swings from VDIS to
VEN, and this is plotted in Figure 9.
7091!“
Functional Description (Continued)
AVOUT (V)
VI o- .
MUX-AMPI
CHANNEL 1 (M)
CHANNEL 3 (A5)
ET;, (TT
MUX'AMP 2
Tzh, Fi, Fri,, A, it
N, 7111/
- tste
-tots-H
TL/H/9131-15
FIGURE 8. Timing Diagram for Switching Bl-State Outputs
kre (ps)
TLfH/9131-16
AVOUT = VEN - VDIS
FIGURE 9. tere " AVOUT
DIGITAL CONTROL
As mentioned in the previous sections, the input channels
and Bi-State output are controlled by logic levels on pins A,
B, and AN. There are two ways to apply logic levels to these
pins. I) Hardwire WM and CB directly to digital ground so
that the LM604 operates in a "stand alone" mode. This
allows input logic levels to directly control the LM604. 2)
Write digital signals to A, B, and ER as shown in the timing
diagrams of Figures 5 and tr. This method is used when the
LM604 interfaces to a microprocessor. Note that cg and
Thm can occur simultaneously, so set-up and hold times are
not required for E. Also, notice that WA must remain a
logic 1 during the hold time period.
Input logic levels are referenced to a 1.4V threshold voltage,
making the LM604 compatible with TTL and CMOS logic.
This threshold voltage is referenced to digital ground. The
voltage level of digital ground can be as low as v- (pin 15)
and as high as 4V below V+ (pin 5).
1 -356
Application Hints
USING MULTIPLE FEEDBACK LOOPS
Each input channel of the LM604 is used as a single op-
amp with its own feedback loop. Two examples of this are
circuits with multiple inverting gain channels and non-invert-
ing gain channels (Figure 10). These circuits have multiple
feedback loops connected to the same output with one
feedback loop connected to a seiected channel and the
others connected to "off" channels. The feedback loop of
the selected channel determines the gain of these circuits.
The off channel feedback loops affect these circuits in two
ways. 1) They create an additional load at the output. 2)
Feedback loops for inverting gain channels provide feed-
through paths from the inputs of the off channels to the
output.
In Figure to, the loading affect of multiple feedback loops is
given in terms of current flowing through the feedback loops
(IF). In circuits with non-inverting gain channels, Ir: is a func-
tion of VOUT and the resistance of the feedback loops. In
circuits with inverting gain channels, ip is different for each
channel selected because it is also a function of the off
channel input voltages. This additional loading must be ac-
counted for when designing Mux-Amp circuits. Otherwise,
the output load resistance will be less than anticipated.
TL/H/9131-19
Channel Yo
1 VI (1 + 5)
2 v2(1+ %)
3 V3(1+EZ)
4 V4 (1 + bl)
1 1 1 1
|F=v°( + + + )
R1+R2 R3+R4 RS+R6 H7+R8
Multiple Non-lnverting Gain Channels
Figure " illustrates feedthrough in an off inverting gain
channel. Feedthrough occurs because the feedback resis-
tors and the Mux-Amp output impedance (ro) form a voltage
divider. This divider allows a portion of the off channel's
input signal to appear at the output. The amount of signal
that feeds through depends on the ratio of output imped-
ance to feedback loop resistance. Output impedance varies
according to Mux-Amp gain (gain of the selected channel)
and the frequency of the feedthrough signal. This variation
must be considered when calculating feedthrough. and it is
plotted in the "Typical Device Characteristics" section.
hte CHANNEL
TL/H/913t-17
R1 + R2 + r0
FIGURE 11. lnvertlng Gain Channel Feedthrough
VOUT = VIN (
TL/Hf9131-18
Channet Yo IF
1 -v1('l-',?) h+ Vo-Vit Vo-V3 Vo-V4
R1 R2 R3 + R4 R5 + R6 H? + R8
2 -V2 (3) k + yoc-1_/1 Edi E
R3 R4 R1 + R2 R5 + R6 R? + R8
3 -V3 (E) b + M1 £12 £14
R5 R6 R1 + R2 R3 + R4 R7 + R8
4 -V4 (a_s) Vo + Vo - V1 Vo A V2 Vo - v3
R7 R8 R1 + R2 R3 + R4 R5 + R6
Multiple Inverting Gain Channels
FIGURE 10. Circuits Using Multiple Inverting and Non-lnvertlng Gain Channels
1709W'I
Application Hints (Continued)
INPUT CHARGE INJECTION
When the Mux-Amp switches channels, charge is injected
from the inputs of the selected and previous channels, see
Figure M. This causes a positive error voltage at the input
of the selected channel and a negative voltage at the previ-
ous channel, The amplitude of this error voltage equals
tha/thr:, where CIN is the total capacitance at the input
and QINJ is the charge injected. As plotted in Figure M,
QiNJ increases proportionally with the difference in voltage
between a channel's input common mode voltage and the
negative supply. The RC time constant of cm times resist-
ance seen from the input will determine how long the error
voltage remains at the input.
- . "s.
Cm y 0m SELECTED
cz), T CHANNEL
- . ' -
Cm - y QINJ '
oINJ T
- ----
Cm y OINJ PREVIOUS
V cz), T CHANNEL
- - - I...--
Cm T [M
TL/H/9131-20
FIGURE 12. Error Voltage From Input Charge Injection
thtu (PC)
TL/Ftf9131-21
FIGURE 13. QINJ " VCM - v-
MAXIMUM OUTPUT LOAD CONDITIONS
The Mux-Amp is guaranteed to drive a 6000 load as speci-
fied over its entire operating range. Reducing the load re-
sistance below this value may cause the output to current
limit. It may also cause the junction temperature limit to be
exceeded when operating the part near its maximum ambi-
ent temperature.
The Mux-Amp is unconditionally stable with as much as
500 pF connected from the output to ground. If the output is
required to drive a larger capacitive load, the Mux-Amp may
need to operate with at least a gain of 10. Otherwise, it may
become unstable when sinking current.
DIGITAL FEEDTHROUGH
When interfacing the Mux-Amp to a microprocessor, pins A,
B, EN, and W are connected to an address bus where high
frequency digital signals are present. The fast edges of
these signals can propagate into the Mux-Amp's analog sig-
nal path, causing fast transients to appear at the output. To
avoid this problem, the following precautions should be tak-
1) Analog and digital ground must be kept separate. They
can only be connected together back at the power supply or
supply bus.
2) Bypass capacitors should have low inductance to prevent
noise spikes on the voltage supply pins. A ceramic disc ca-
pacitor of 0.1 pLF is usually sufficient.
3) All lead lengths should be kept short to prevent them
from picking up digital signals.
By using these rules, digital signals can be attenuated at the
input channels by typically 100 dB.
Lab measurements have shown a minimum digital feed-
through signal of 2 mV occurs at the output even when the
best layout precautions are taken. This is fine for many ap-
plications. but to completely eliminate digital feedthrough,
any signals coming directly from the bus must be sent to the
Mux-Amp via a Tri-State buffer, see Figure td, This isolates
the Mux-Amp’s digital pins from the address bus to prevent
pin to pin feedthrough. CS can be used to enable the Tri-
State buffers when signals are sent to the Mux-Amp from
the address bus.
( ADDRESS BUS j
' e A [Ti -,
SYSTEM " ADDRESS ens gm
We - USED BY A, a, DI
2" 6,ri0,ri4 1 ,
DM74LS367 ADDRESS Diego:
TRI-STATE BUFFER 19 LOGIC FOR CS
3 7 9 13
18 17 16 -
54 FR c_S
il" 2 ..-.
TL/H/9131-22
FIGURE 14. Isolating Mux-Amp from Address
Bus by Using a Tri-State Buffer
Typical Applications
MUX-ANP 2
Mux-Amp
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TL/H/9131-23
Eight Channel Multiplexer and Ampllfler with a Gain of 10
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Mux-Amp
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1.5nr 110mm
54.9mm T J.
4.32m1z 1.5nF
1.5nF 110mm f,
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1m1z 1.5nF
1.5nF 110K912 5
54.9mm
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1.5nF 110mm
54.9mm
TL/H/9131-24
Channel
Center Frequency
10 khz
15 kHz
20 kHz
Programmable Bandpass Filter: Each channel has a 2 kHz bandwidth and a gain of 1 at the center frequency
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
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LM604IN - product/Im604in?HQS=T|-nu||-nu|I-dscataIog-df-pf-nuII-wwe
LM604IJ - productllm604ij?HQS=T|-nulI-nulI-dscatalog-df—pf-null-wwe
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LM604CM - product/lm604cm?HQS=T|-nu|l-nulI-dscataIog-df-pf-null-wwe
LM604AMJ - product/Im604amj?HQS=TI-null-nulI-dscataIog-df-pf-null-wwe
LM604ACN - product/lm604acn?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
LM604ACM - product/Im604acm?HQS=T|-nu|I-nu|I-dscatalog-df-pf-nulI-wwe
