LIS331DLTR ,"MEMS motion sensor 3-axisApplicationsfull scales of ±2g/±8g and it is capable of ■ Free-Fall detection measuring acceleratio ..
LIS344AL , MEMS inertial sensor 3-axis ultracompact linear accelerometer
LIS344AL , MEMS inertial sensor 3-axis ultracompact linear accelerometer
LIS344ALHTR ,MEMS inertial sensor high performance 3-axis ?/ ?g ultracompact linear accelerometerBlock diagram . . . . 5Figure 2. Pin connection . . . 5Figure 3. LIS344ALH electrical ..
LIS344ALTR , MEMS inertial sensor 3-axis ultracompact linear accelerometer
LIS344ALTR , MEMS inertial sensor 3-axis ultracompact linear accelerometer
LM3242TMX/NOPB ,6MHz, 750mA Miniature, Adjustable, Step-Down DC-DC Converter with Bypass 9-DSBGA -30 to 90 SNOSB48E–OCTOBER 2011–REVISED AUGUST 20155 Pin Configuration and FunctionsYFQ Package9-Pin DSBGATo ..
LM3243TMX/NOPB ,2.7MHz, 2.5A Step-Down DC-DC Converter with Analog Bypass Mode for 2G/3G/4G PAs 16-DSBGA -30 to 90Features 3 DescriptionThe LM3243 is a DC-DC converter optimized for1• Input Voltage Range: 2.7 V to ..
LM324A ,Quad Operational AmplifierLM124ALM224A - LM324ALOW POWER QUAD OPERATIONAL AMPLIFIERS ■ WIDE GAIN BANDWIDTH : 1.3MHz ■ LA ..
LM324A ,Quad Operational Amplifier
LM324A ,Quad Operational AmplifierABSOLUTE MAXIMUM RATINGS Symbol Parameter LM124A LM224A LM324A UnitVSupply voltage ±16 or 32 ..
LM324A ,Quad Operational AmplifierABSOLUTE MAXIMUM RATINGS Symbol Parameter LM124A LM224A LM324A UnitVSupply voltage ±16 or 32 ..
LIS331DL-LIS331DLTR
"MEMS motion sensor 3-axis
April 2008 Rev 3 1/42
LIS331DLMEMS motion sensor
3-axis - ±2g/±8g smart digital output “nano” accelerometer
Features 2.16 V to 3.6 V supply voltage 1.8 V compatible IOs <1 mW power consumption ±2g / ±8g dynamically selectable full-scaleI2 C/SPI digital output interface Programmable interrupt generator Embedded click and double click recognition Embedded free-fall and motion detection Embedded high pass filter Embedded self test 10000 g high shock survivability ECOPACK® RoHS and “Green” compliant
(see Section9)
Applications Free-Fall detection Motion activated functions Gaming and virtual reality input devices Vibration monitoring and compensation
DescriptionThe LIS331DL, belonging to the “nano” family of
ST motion sensors, is the smallest consumer low-
power three axes linear accelerometer. The
device features digital I2 C/SPI serial interface
standard output and smart embedded functions.
The sensing element, capable of detecting the
acceleration, is manufactured using a dedicated
process developed by ST to produce inertial
sensors and actuators in silicon.
The IC interface is manufactured using a CMOS
process that allows to design a dedicated circuit
which is trimmed to better match the sensing
element characteristics.
The LIS331DL has dynamically user selectable
full scales of ±2g/±8g and it is capable of
measuring accelerations with an output data rate
of 100 Hz or 400 Hz.
A self-test capability allows the user to check the
functioning of the sensor in the final application.
The device may be configured to generate inertial
wake-up/free-fall interrupt signals when a
programmable acceleration threshold is crossed
at least in one of the three axes. Thresholds and
timing of interrupt generators are programmable
by the end user on the fly.
The LIS331DL is available in plastic Land Grid
Array package (LGA) and it is guaranteed to
operate over an extended temperature range from
-40 °C to +85 °C.
Table 1. Device summary
Contents LIS331DL2/42
Contents Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.3 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.4 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.3 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
LIS331DL Contents 3/42
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 CTRL_REG3 [interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 26
7.5 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.7 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.9 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.10 FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.11 FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12 FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.13 FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.14 FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.15 FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.16 FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.17 FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.18 CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.19 CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.20 CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.21 CLICK_THSZ (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.22 CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.23 CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.24 CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 358.1 Mechanical characteristics at 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2 Mechanical characteristics derived from measurement in the -40 °C to +85
°C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3 Electrical characteristics at 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Contents LIS331DL4/42
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LIS331DL List of figures
5/42
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. I2C slave timing diagram (4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. LIS331DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Multiple bytes SPI write protocol (2 bytes example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. X axis Zero-g level at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. X axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Y axis Zero-g level at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. Y axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. Z axis Zero-g level at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Z axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. X axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. X axis Sensitivity change vs. temperature at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Y axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Y axis Sensitivity change vs. temperature at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22. Z axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. Z axis Sensitivity change vs. temperature at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. Current consumption in normal mode at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 25. LGA 16: Mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
List of tables LIS331DL
6/42
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Mechanical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted . . . . . . . . . . . . 7
Table 4. Electrical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted. . . . . . . . . . . . . . 8
Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 17
Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17
Table 15. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 19. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 20. CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 21. High pass filter cut-off frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 23. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 24. Data Signal on INT1(2) pad control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 25. STATUS_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 26. STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 27. OUT_X register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 28. OUT_Y register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 29. OUT_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 30. FF_WU_CFG_1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 31. FF_WU_CFG_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 32. FF_WU_SRC_1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 33. FF_WU_SRC_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 34. FF_WU_THS_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 35. FF_WU_THS_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 36. FF_WU_DURATION_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 37. FF_WU_DURATION_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 38. FF_WU_CFG_2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 39. FF_WU_CFG_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 40. FF_WU_SRC_2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 41. FF_WU_SRC_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 42. FF_WU_THS_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 43. FF_WU_THS_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 44. FF_WU_DURATION_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 45. FF_WU_DURATION_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 46. CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 47. CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 48. Click interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LIS331DL List of tables
7/42
Table 49. CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 50. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 51. CLICK_THSY_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 52. CLICK_THSY_X description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 53. CLICK_THSZ register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 54. CLICK_THSZ description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 55. CLICK_TimeLimit register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 56. CLICK_Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 57. CLICK_Window register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Block diagram and pin description LIS331DL
8/42 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connection
LIS331DL Block diagram and pin description
9/42
Table 2. Pin description
Mechanical and electrical specifications LIS331DL
10/42 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted(1) The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V. Typical specifications are not guaranteed Verified by wafer level test and measurement of initial offset and sensitivity Typical zero-g level offset value after MSL3 preconditioning Offset can be eliminated by enabling the built-in high pass filter If STM bit is used values change in sign for all axes Self Test output changes with the power supply. “Self test output change” is defined as OUTPUT[LSb](Self-test bit on CTRL_REG1=1)
-OUTPUT[LSb](Self-test bit on CTRL_REG1=0). 1LSb=4.6g/256 at 8bit representation, ±2.3 g Full-Scale Output data reach 99% of final value after 3/ODR when enabling Self-Test mode due to device filtering ODR is output data rate. Refer to Table 4 for specifications
LIS331DL Mechanical and electrical specifications
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2.2 Electrical characteristics
Table 4. Electrical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted(1) The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V. Typical specification are not guaranteed It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off. Filter cut-off frequency Time to obtain valid data after exiting Power-Down mode
Mechanical and electrical specifications LIS331DL
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2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and top.
Table 5. SPI slave timing values
Figure 3. SPI slave timing diagram (2) Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
LIS331DL Mechanical and electrical specifications
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2.3.2 I2 C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 6. I2 C slave timing values
Figure 4. I2 C slave timing diagram (4) Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports Data based on standard I2 C protocol requirement, not tested in production A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL Cb = total capacitance of one bus line, in pF
Mechanical and electrical specifications LIS331DL
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2.4 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Note: Supply voltage on any pin should never exceed 6.0 V
Table 7. Absolute maximum ratings
This is a mechanical shock sensitive device, improper handling can cause permanent
damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages to
the part
LIS331DL Mechanical and electrical specifications
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2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g
acceleration to it. As the sensor can measure DC accelerations this can be done easily by
pointing the axis of interest towards the center of the Earth, noting the output value, rotating
the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing
so, ± 1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and also over time. The Sensitivity T olerance
describes the range of sensitivities of a large population of sensors.
2.5.2 Zero-g level
Zero-g level Offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface
will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output
is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h,
data expressed as 2’s complement number). A deviation from ideal value in this case is
called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and
therefore the offset can slightly change after mounting the sensor onto a printed circuit
board or exposing it to extensive mechanical stress. Offset changes little over temperature,
see “Zero-g level change vs. temperature”. The Zero-g level tolerance (TyOff) describes the
Standard Deviation of the range of Zero-g levels of a population of sensors.
2.5.3 Self test
Self Test allows to check the sensor functionality without moving it. The self test function is
off when the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the
self-test bit of ctrl_reg1 is programmed to ‘1‘ an actuation force is applied to the sensor,
simulating a definite input acceleration. In this case the sensor outputs will exhibit a change
in their DC levels which are related to the selected full scale through the device sensitivity.
When Self Test is activated, the device output level is given by the algebraic sum of the
signals produced by the acceleration acting on the sensor and by the electrostatic test-force.
If the output signals change within the amplitude specified inside Table 3, then the sensor is
working properly and the parameters of the interface chip are within the defined
specifications.
2.5.4 Click and double click recognition
The click and double click recognition functions help to create man-machine interface with
little software overload. The device can be configured to output an interrupt signal on
dedicated pin when tapped in any direction.
If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial
interrupt pins (INT1 and/or INT2). A more advanced feature allows to generate an interrupt
request when a “double click” stimulus is applied. A programmable time between the two
events allows a flexible adaption to the application requirements. Mouse-button like
application, like clicks and double clicks, can be implemented.
This function can be fully programmed by the user in terms of expected amplitude and
timing of the stimuli.
Functionality LIS331DL
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3 Functionality
The LIS331DL is a nano, low-power, digital output 3-axis linear accelerometer packaged in
an LGA package. The complete device includes a sensing element and an IC interface able
to take the information from the sensing element and to provide a signal to the external
world through an I2 C/SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is in the fF range.
3.2 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which
converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is
finally available to the user by an analog-to-digital converter.
The acceleration data may be accessed through an I2 C/SPI interface thus making the
device particularly suitable for direct interfacing with a microcontroller.
The LIS331DL features a Data-Ready signal (RDY) which indicates when a new set of
measured acceleration data is available thus simplifying data synchronization in the digital
system that uses the device.
The LIS331DL may also be configured to generate an inertial Wake-Up and Free-Fall
interrupt signal accordingly to a programmed acceleration event along the enabled axes.
Both Free-Fall and Wake-Up can be available simultaneously on two different pins.
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).
The trimming values are stored inside the device in a non volatile memory. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be used
during the normal operation. This allows to use the device without further calibration.
LIS331DL Application hints
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4 Application hints
Figure 5. LIS331DL electrical connection
The device core is supplied through Vdd line while the I/O pads are supplied through
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be
placed as near as possible to the pin 14 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I2 C/SPI interface.When using the I2 C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be
completely programmed by the user through the I2 C/SPI interface.
4.1 Soldering information
The LGA package is compliant with the ECOP ACK® , RoHS and “Green” standard. It is
qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendation are available at /mems.
Digital interfaces LIS331DL
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5 Digital interfaces
The registers embedded inside the LIS331DL may be accessed through both the I2 C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2 C interface, CS
line must be tied high (i.e connected to Vdd_IO).
5.1 I2 C serial interface
The LIS331DL I2 C is a bus slave. The I2 C is employed to write data into registers whose
content can also be read back.
The relevant I2 C terminology is given in the table below.
There are two signals associated with the I2 C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LIS331DL. When the bus is free both the lines are high.
The I2 C interface is compliant with fast mode (400 kHz) I2 C standards as well as with the
normal mode.
Table 8. Serial interface pin description
Table 9. Serial interface pin description
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5.1.1 I2 C operation
The transaction on the bus is started through a ST ART (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS331DL is 001110xb. SDO/SA0 pad can be
used to modify less significant bit of the device address. If SDO pad is connected to voltage
supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is
‘0’ (address 0011100b). This solution permits to connect and address two different
accelerometers to the same I2 C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2 C embedded inside the LIS331DL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged. Table 10 explains how
the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 10. SAD+Read/Write patterns
Table 11. Transfer when Master is writing one byte to slave
Table 12. Transfer when Master is writing multiple bytes to slave
Digital interfaces LIS331DL
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Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
5.2 SPI bus interface
The LIS331DL SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Figure 6. Read & write protocol
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Table 13. Transfer when Master is receiving (reading) one byte of data from slave
Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave
LIS331DL Digital interfaces
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Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address will be auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb
first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 7. SPI read protocol
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
