LH79520N0Q000B1 ,System-on-Chip IMPORTANT NOTICE Dear customer, stAs from June 1 , 2007 NXP Semiconductors has acquired the ..
LH79524N0F100A1 ,System-on-ChipFeatures (I S)� High Performance: 76.205 MHz CPU Speed, � Watchdog Timer50.803 MHz maximum AHB cloc ..
LH7A404N0F000B3 ,32-Bit System-on-ChipFeatures include 80 kB on-chip SRAM,� USB 2.0 Full Speed Devicefully static design, power managemen ..
LH8550QLT1G , General Purpose Transistors PNP Silicon
LHI1148 , Quad Element Detector LHi 1148
LHI778 , Dual Element Detector
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorMAXIMUM RATINGSRating Symbol Value UnitInput–Output Voltage Differential V –V 40 VdcI OPower Dissip ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorBlock DiagramInput Vin 3+-Voltage ProtectionReference CircuitryRlimit2VoOutput1VadjRev. 1.0.22002 F ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorMAXIMUM RATINGSRating Symbol Value UnitInput−Output Voltage Differential V −V 40 VdcI OPower Dissip ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorLM317L 3-Terminal Adjustable RegulatorFebruary 2005LM317L3-Terminal Adjustable RegulatorAlso, it ma ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorLM217LLM317LLOW CURRENT1.2 TO 37V ADJUSTABLE VOLTAGE REGULATOR■ OUTPUT VOLTAGE RANGE: 1.2 TO 37V■ O ..
LM317-LZ ,3-Terminal 0.1A Positive Adjustable RegulatorAPPLICATIONSDESCRIPTIONTO-92 SO-8The LM217L/LM317L are monolithic integratedcircuit in SO-8 and TO- ..
LH79520N0Q000B1
System-on-Chip
IMPORTANT NOTICE Dear customer,
As from June 1st , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data
sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use /microcontrollers for indicated sales addresses use (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the
version)
- Copyright © (year) by SHARP Corporation.
is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via
e-mail or phone (details via ). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document.
NXP Semiconductors
LH79520
Product data sheet System-on-Chip
FEATURES Highly Integrated System-on-Chip High Performance (77.4144 MHz CPU Speed) ARM720T™ RISC Core 32-bit ARM7TDMI™ RISC Core8 kB Cache MMU (Windows CE™ Enabled) Write Buffer 32 kB On-Chip SRAM Flexible, Programmable Memory Interface SDRAM Interface 15-bit External Address Bus 32-bit External Data Bus Two Segments (128 MB each) SRAM/Flash/ROM Interface 26-bit External Address Bus 32-bit External Data Bus Seven Segments (64 MB Each) Multi-stream DMA Controller Four 32-bit Burst-based Data Streams Clock and Power Management 32.768 kHz Oscillator for Real Time Clock 14.7456 MHz Oscillator and On-chip PLL for
CPU and Bus Clocks Active, Standby, Sleep and Stop Power Modes Externally-supplied Clock Options Low Power Modes Active Mode: 55 mA (MAX.) Standby Mode: 35 mA (MAX.) Sleep Mode: 5.5 mA (MAX.) Stop Mode 2: 18 A Watchdog Timer Vectored Interrupt Controller 16 Standard and 16 Vectored IRQ Interrupts Hardware Interrupt Priority Software Interrupts FIQ Fast Interrupts Three UARTs 16-byte FIFOs for Rx and Tx IrDA SIR Support Supports Data Rates Up to 460.8 kb/s Two 16-bit Pulse Width Modulators Two Dual Channel Timer Modules Real Time Clock 64 Programmable General Purpose I/O Signals Multiplexed with Peripheral I/O Signals Programmable Color LCD Controller Up to 800 × 600 Resolution Supports STN, Color STN, AD-TFT, TFT Supports 15 Shades of Gray TFT: Supports 64 k Direct Colors or 256 Colors
selected from a Palette of 64,000 Colors Color STN: Supports 3,375 Direct Colors or 256
Colors Selected from a Palette of 3,375 Colors Synchronous Serial Port Supports Data Rates Up to 1.8452 Mb/s Compatible with Common Interface Schemes Motorola SPI™ National Semiconductor MICROWIRE™ Texas Instruments SSI JTAG Debug Interface and Boundary Scan 5 V Tolerant Digital I/O XTALIN and XTAL32IN inputs are 1.8 V ± 10%
DESCRIPTIONThe LH79520, powered by an ARM720T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
The LH79520 combines a 32-bit ARM720T RISC,
Color LCD controller, Cache, Local SRAM, a number of
essential peripherals such as Direct Memory Access,
Serial and Parallel Interfaces, Infrared support, Timers,
Real Time Clock, Watchdog Timer, Pulse Width Modu-
lators, and an on-chip Phase Lock Loop. Debug is
made simple by JTAG support.
This high level of integration lowers overall system
costs, reduces development cycle time and acceler-
ates product introduction. The LH79520’s fully static
design, power management unit, low voltage operation
(1.8 V Core, 3.3 V I/O), on-chip PLL, fast interrupt
response time, on-chip cache and SRAM, powerful
instruction set, and low power RISC core provide high
performance.
To build an advanced portable device, advanced pro-
cessing capability is required. This capability must come
with increased performance in the display system and
peripherals, and yet demand less power from batteries.
The LH79520 is an integrated solution to fit these needs.
LH79520 System-on-Chip
NXP Semiconductors
ORDERING INFORMATION
Table 1. Ordering information
System-on-Chip LH79520
NXP Semiconductors
Figure 1. LH79520 block diagram
LH79520 System-on-Chip
NXP Semiconductors
PIN CONFIGURATION
Figure 2. LH79520 pin configuration
System-on-Chip LH79520
NXP Semiconductors
SIGNAL DESCRIPTIONS
Table 2. LH79520 Signal Descriptions
LH79520 System-on-Chip
NXP Semiconductors
Table 2. LH79520 Signal Descriptions (Cont’d)
System-on-Chip LH79520
NXP Semiconductors
Table 2. LH79520 Signal Descriptions (Cont’d)
LH79520 System-on-Chip
NXP Semiconductors
Table 2. LH79520 Signal Descriptions (Cont’d)
System-on-Chip LH79520
NXP Semiconductors
NOTES: These pin numbers have multiplexed functions. Signals preceded by ‘n’ are Active LOW. Immediately after reset, pin 144 can be programmed to function as INT5, DREQ1 or both.
Software should avoid enabling both of these functions simultaneously. Pin 144 can also be
programmed to function as nWAIT, rendering the INT5/DREQ1 choice unavailable.
Table 2. LH79520 Signal Descriptions (Cont’d)
LH79520 System-on-Chip
NXP Semiconductors
NUMERICAL PIN LIST
Table 3. LH79520 Numerical Pin List
System-on-Chip LH79520
NXP Semiconductors
Table 3. LH79520 Numerical Pin List (Cont’d)
LH79520 System-on-Chip
NXP Semiconductors
Table 3. LH79520 Numerical Pin List (Cont’d)
System-on-Chip LH79520
NXP Semiconductors
Table 3. LH79520 Numerical Pin List (Cont’d)
LH79520 System-on-Chip
NXP Semiconductors
NOTES: Input with internal pull-up. Input with internal pull-down. Output is for crystal oscillator only, no drive capability. Input with Schmitt Trigger. I/O = Input/Output. Software should avoid enabling the INT5 and DREQ1 functions simultaneously. Output Drive Values shown are MAX. See ‘DC Specifications’. Crystal Oscillator Inputs should be driven to a maximum of 1.8 V ± 10%.
Table 3. LH79520 Numerical Pin List (Cont’d)
System-on-Chip LH79520
NXP Semiconductors
NOTES: The Intensity bit is identically generated for all three colors. MUSTN = Monochrome Upper data bit for STN panel. MLSTN = Monochrome Lower data bit for STN panel. CUSTN = Color Upper data bit for STN panel. CLSTN = Color Lower data bit for STN panel. Connect to the LSB of the Red, Green, and Blue inputs of a 6:6:6 panel. Recommended hookups for TFT 5:5:5 + Intensity and 5:6:5 are shown.
This wiring requires the BGR bit in the LCD Control Register to be 0.
Table 4. LCD Data Multiplexing
Table 5. LCD Control and Timing Signals
LH79520 System-on-Chip
NXP Semiconductors
SYSTEM DESCRIPTIONS
ARM720T ProcessorThe LH79520 microcontroller features the ARM720T
cached core with an Advanced High-Performance Bus
(AHB) interface. The ARM720T features: 32-bit ARM7TDMI™ RISC Core8 kB Cache MMU (Windows CE enabled)
The processor is a member of the ARM7T family of
processors. For more information, see the ARM docu-
ment, ‘ARM720T (Rev 3) Technical Reference Manual’,
available on NXP’s’s website at .
The LH79520 MMU provides a means to map Phys-
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is con-
strained by hardware to specific addresses, to be reor-
ganized at addresses identified by the user. These user
identified locations are called Virtual Addresses (VA).
When the MMU is enabled, Code and Data must be
built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU is
directly controlled through the System Control Copro-
cessor, Coprocessor 15 (CP15). The MMU is indirectly
controlled by a Translation Table (TT) and Page Tables
(PT) prepared by the user and established using a por-
tion of physical memory dedicated by the user to stor-
ing the TT and PT’s.
Figure 3. LH79520 Application Diagram Example
System-on-Chip LH79520
NXP Semiconductors
Memory ArchitectureAn integrated SDRAM Controller and Static Memory
Controller provide a glueless interface to external
SDRAM, Flash, SRAM, ROM, and burst ROM. Three
remap options for the physical memory are selectable
by software, as shown in Figures 4, 5, and 6. Memory
is exclusively Little Endian.
SDRAM CONTROLLERThe SDRAM Controller provides the interface
between the internal bus and external (off-chip)
SDRAM memory devices (Figure 2).
The SDRAM Controller provides the following features: Two independently cont rolled chip selects. Transfers data between the controller and SDRAM
in quad-word bursts. Supports both 32-bit and 16-bit SDRAM. Supports 2K, 4K, and 8K row address memory parts,
i.e. typical 256M, 128M, 64M, and 16M parts, with 8,
16, or 32 DQ bits per device. Two reset domains allo w SDRAM contents to be
preserved over a soft reset.
STATIC MEMORY CONTROLLER (SMC)The SMC provides the interface between the internal
bus and external (off-chip) memory devices.
The LH79520 boots from 16-bit memory. The SMC
address space is divided into eight memory banks of MB each. The SMC supports: Static Memory-mapped Devices including RAM,
ROM, Flash, and Burst ROM Asynchronous Operations: Page Mode Reads for non-clocked memory Burst Mode Reads for burst mode ROM 8-, 16-, and 32-bit wide external memory data paths Independent configuration for up to eight memory
banks, each up to 64 MB Programmable Parameters: WAIT States (up to 32) Bus Turnaround Cycles (1 to 16) Initial and Subsequent Burst Read WAIT State for
Burst ROM Devices.
The Static Memory Controller (SMC) also supports
an nWAIT input that can be used by an external device
to vary the wait time.
DMA ControllerThe DMA Controller provides support for DMA-
capable peripherals. The LCD controller uses its own
Figure 4. Memory Remap ‘00’ and ‘11’
Figure 5. Memory Remap ‘10’
LH79520 System-on-Chip
NXP Semiconductors Simultaneous servicing of up to 4 data streams Three transfer modes are supported: Memory to Memory Peripheral to Memory Memory to Peripheral Identical source and destination capabilities Transfer Size Programmable (Byte, Half-word, Word) Burst Size Programmable Address Increment or Address Freeze Transfer Error indication for each stream via an
interrupt 16-word FIFO array with pack and unpack logic
Handles all combinations of byte, half-word or word
transfers from input to output.
Color LCD Controller (CLCDC)The CLCDC provides all the necessary control and
drive signals to interface directly with a variety of color
and monochrome LCD panels. Supports single and dual scan color and mono-
chrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces Supports Thin Film Transi stor (TFT) color displays Programmable resolution up to 800 × 600 800 × 600 (16-bit color can only be supported at65 Hz refresh rates with 800 × 600 resolution). 15 gray-level mono, 3,375 color STN, and 64 k color
TFT support 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN 1-, 2-, 4-, or 8-BPP palettized color displays for color
STN and TFT True-color non-palettized, for color STN and TFT Programmable timing for different display panels 256-entry, 16-bit palette fast-access RAM Frame, line and pixel clock signals AC bias signal for STN or data enable signal for
TFT panels Patented grayscale algorithm Interrupt Generation Events Dual 16-deep programmable 32-bit wide FIFOs for
buffering incoming data.
ADVANCED LCD INTERFACEThe Advanced LCD Interface peripheral allows for
direct connection to ultra-thin panels that do not include
a timing ASIC. It converts TFT signals from the Color
LCD controller to provide the proper signals, timing and
levels for direct connection to a panel’s Row and Col-
Advanced LCD Interface peripheral also provides a
bypass mode that allows the LH79520 to interface to the
built-in timing ASIC in standard TFT and STN panels.
Synchronous Serial Port (SSP)The SSP is a master-only interface for synchronous
serial communication with slave peripheral devices that
support protocols for Motorola SPI, National Semicon-
ductor MICROWIRE, or Texas Instruments Synchro-
nous Serial Interface. Master-only operation Programmable clock rate Separate transmit FIFO and receive FIFO buffers,
16 bits wide, 8 locations deep DMA for transmit and receive Programmable interface protocols: Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port Programmable data frame size from 4 to 16 bits Independent masking of transmit FIFO, receive
FIFO and receive overrun interrupts Available internal loopback test mode.
Universal Asynchronous
Receiver Transmitter (UART)The LH79520 incorporates three UARTs. Programmable use of UART0 or IrDA SIR input/output Separate 16-byte transmit and receive FIFOs to
reduce CPU interrupts Programmable FIFO disabling for 1-byte depth Programmable baud rate generator Independent masking of transmit FIFO, receive
FIFO, receive timeout and modem status interrupts False start bit detection Line Break generation and detection Fully-programmable serial interface characteristics: 5-, 6-, 7-, or 8-bit data word length Even-, odd- or no-parity bit generation and detection 1 or 2 stop bit generation IrDA SIR Encode/Decode block, providing: Programmable use of IrDA SIR or UART0
input/output Supports data rates up to 115.2 Kbps half-duplex Programmable internal clock generator, allowing
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.
System-on-Chip LH79520
NXP Semiconductors
VARIATIONS FROM THE 16C550 UARTThe UART varies from the industry-standard
16C550 UART device in six ways: Receive FIFO trigger levels are fixed at 8 bytes Receive errors are stored in the FIFO, and do not
generate an interrupt. The internal register map address space and each
register’s bit function differ.
The following 16C550 UART features are not sup-
ported: 1.5 stop bits (1 or 2 stop bits only are supported) The forcing stick parity function Independent receive clock.
Pulse Width Modulator (PWM) Two independent output channels with separate
input clocks Up to 16-bit resolution Programmable synchronous mode support Allows external input to start PWM Programmable pulse width (duty cycle), interval (fre-
quency), and polarity Static programming: PWM is stopped Dynamic programming: PWM is running Updates duty cycle, frequency, and polarity at the
end of a PWM cycle Wide programming range.
Vectored Interrupt ControllerThe Vectored Interrupt Controller combines the
interrupt request signals from 20 internal and eight
external interrupt sources and applies them, after
masking and prioritization, to the IRQ and FIQ interrupt
inputs of the ARM7TDMI processor core.
The Interrupt Controller incorporates a hardware
interrupt vector logic with programmable priority for up
to 16 interrupt sources. This logic reduces the interrupt
response time for IRQ type interrupts compared to
solutions using software polling to determine the high-
est priority interrupt source. This significantly improves
the real-time capabilities of the LH79520 in embedded
control applications. 20 internal and eight external interrupt sources Individually maskable Status accessible for software polling IRQ interrupt vector logic for up to 16 channels with
programmable priorities All of the interrupt channels, with the exception of the FIQ interrupt request Non-vectored IRQ interrupt request (software to
poll IRQ source) Vectored IRQ interrupt request (up to 16 chan-
nels total) The Watchdog timer can only generate FIQ interrupt
requests External interrupt inputs programmable Edge triggered or level triggered Rising edge/active HIGH or falling edge/active
LOW
The 28 interrupt channels are shown in Table 6.
Table 6. Interrupt Channels
LH79520 System-on-Chip
NXP Semiconductors
Reset, Clock, and Power
Controller (RCPC)The RCPC generates the various clock signals for the
operation of the LH79520 and provides for an orderly
start-up after power-on and during a wake-up from one
of the power saving operating modes. The RCPC allows
the software to individually select the frequency of the
various on-chip clock signals as required to operate the
chip in the most power-efficient mode. It features: 14.7456 MHz crystal oscillator and PLL for on-chip
Clock generation External Clock input if on -chip oscillator and PLL are
not used 32.768 kHz crystal oscilla tor generating 1 Hz clock
for Real Time Clock Individually controlled cl ocks for peripherals and CPU Clock source for UARTs is selectable between
14.7456 MHz crystal oscillator and external clock
source Programmable clock prescalers for UARTs and
PWMs Five global power control modes are available: Active Standby
–Sleep Stop1 Stop2 CPU and Bus clock frequency can be changed
on the fly Selectable clock output Hardware reset (nRESETIN) and software reset.
The 32.768 kHz crystal oscillator is not required for
chip operation, so it may be left out of the design to
save power. If this crystal is not used, XTALIN should
be pulled to VDD or VSS so the input does not float.
Table 7. Clock and Enable States for Different Power Modes
(Using On-chip Oscillator and PLL)
System-on-Chip LH79520
NXP Semiconductors
Real Time ClockThe RTC can provide a basic alarm function or long
time base counter. This is achieved by generating an
interrupt signal after counting for a programmed num-
ber of cycles of RTC input. Counting in one-second
intervals is achieved by the use of a 1 Hz clock input to
the RTC.
The features of the RTC are: 32-bit up counter with programmable load Programmable 32-bit match compare register Software maskable interrupt when counter and com-
pare registers are identical.
RTC input clock sources:
PLL clock 32.768 kHz clock 1 Hz clock (default).
Watchdog TimerThe Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer to be
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The features of the Watchdog Timer are: Driven by the bus clock 16 programmable time-out periods: 216 through 231
clock cycles Generates a system reset (resets LH79520) or a FIQ
Interrupt whenever a time-out period is reached Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes Protection mechanism guards against interrupt-ser-
vice failure: The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a soft reset.
TimerThe LH79520 incorporates two Timer modules,
each comprising two 16-bit independently programma-
ble timers. This gives a total of four independent timers. Each timer has two operating modes: Free-running mode: After reaching 0x0000 the
timer wraps around to 0xFFFF and generates an
interrupt request. It continues to count down from
0xFFFF. Periodic timer mode: After reaching 0x0000 the
timer is automatically reloaded with its pro-
grammed value and generates an interrupt re-
quest. It continues to count down from the
loaded value. Each timer contains a programmable pre-scaler: Bus clock divided by 1, 16, or 256 Timers can be cascaded to achieve longer timing
periods Carry-out of higher-order timer provides clock signal
for next lower order timer Possible timing ranges:15 (single timer)31 (two timers cascaded)47 (three timers cascaded)63 (four timers cascaded) Output signal of lowest order timer is externally avail-
able as CTOUT1B signal.
Input/Output Configuration SystemThe registers provided by the IOCON System allow
the user to directly control the pin multiplexing of the
device; by setting or clearing bits in a set of registers, the
user can configure the LH79520 for peripheral devices.
General Purpose Input/Output (GPIO)The LH79520 provides up to 64 bits of programma-
ble input/output. These eight 8-bit ports are Ports A
through H, and are multiplexed with other signals. Individually programmable input/output pins All I/O ports default to Input on power-up.
LH79520 System-on-Chip
NXP Semiconductors
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
NOTE: These stress ratings are only for transient conditions. Oper-
ation at or beyond absolute maximum rating conditions may
affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
NOTES: Core Voltage should never exceed I/O Voltage after initial power
up. See the section titled ‘Power Supply Sequencing’. Using 14.7456 MHz Input Crystal and On-Chip PLL. Functional to
DC when using external clock.
System-on-Chip LH79520
NXP Semiconductors
DC/AC SPECIFICATIONS (COMMERCIAL)Unless otherwise noted, all data provided under
commercial DC specifications are based on 0°C to
+70°C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6V,
VDDA = 1.62 V to 1.98 V.
DC Specifications (Commercial)
NOTES: Table 2 details each pin’s buffer type. P-P Sinusoidal; 0.0 V DC offset. Running Typical Application over operating range. Current measured with CPU stopped and all peripherals enabled.
AC Test Conditions
LH79520 System-on-Chip
NXP Semiconductors
AC Specifications All signals described in Table 8 relate to transitions
after a reference clock signal. The illustration in Figure
7 represents all cases of these sets of measurement
parameters; except for the Asynchronous Memory
Interface — which are referenced to Address Valid.
The reference clock signals in this design are: HCLK, the System Bus clock PCLK, the Peripheral Bus clock (locked to HCLK in
the LH79520) SSPCLK, the Synchronous Serial Interface clock UARTCLK, the UART Interface clock LCDDCLK, the LCD Data clock from the
LCD Controller and SDCLK, the SDRAM clock.
All signal transitions are measured from the 50%
point of the clock to the 50 % point of the signal. See
Figure 7.
For outputs from the LH79520, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 8.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the ris-
ing edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 8.
For Inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 8.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the memory output must be held valid
from the rising edge of the reference clock signal. Min-
imum requirements are shown in Table 8.
Figure 7. LH79520 Signal Timing
System-on-Chip LH79520
NXP Semiconductors
Table 8. AC Signal Characteristics (Commercial)
LH79520 System-on-Chip
NXP Semiconductors
NOTES: INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode,
and held Active for a minimum of 20 ns in Edge Sensitive Mode. nDACK0, DACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced,
for a minimum of 20 ns.
Table 8. AC Signal Characteristics (Commercial) (Cont’d)
System-on-Chip LH79520
NXP Semiconductors
DC/AC SPECIFICATIONS (INDUSTRIAL)Unless otherwise noted, all data provided under
industrial DC specifications are based on -40°C to
+85°C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6V,
VDDA = 1.62 V to 1.98 V.
DC Specifications (Industrial)
NOTES: Table 2 details each pin’s buffer type. P-P Sinusoidal; 0.0 V DC offset. Running Typical Application over operating range. Current measured with CPU stopped and all peripherals enabled.
AC Test Conditions
LH79520 System-on-Chip
NXP Semiconductors
CURRENT CONSUMPTION BY OPERATING MODECurrent consumption can depend on a number of
parameters. To make this data more usable, the values
presented in Table 9 were derived under the conditions
presented here.
Maximum Specified ValueThe values specified in the MAXIMUM column were
determined using these operating characteristics: All IP blocks either operating or enabled at maximum
frequency and size configuration Core operating at maximum power configuration All I/O loads at maximum (50 pF) All voltages at maximum specified values Maximum specified ambient temperature.
TypicalThe values in the TYPICAL column were determined
using a ‘typical’ application under ‘typical’ environmental
conditions and the following operating characteristics: SPI, UART, PWMs, and Timer peripherals operat-
ing; all other peripherals disabled LCD enabled with 320 × 240 × 16-bit color, 60 Hz
refresh rate I/O loads at nominal Cache enabled FCLK = 77.4 MHz; HCLK = 51.6 MHz All voltages at typical values Nominal case temperature.
PERIPHERAL CURRENT CONSUMPTIONIn addition to the modal current consumption, Table
10 shows the typical current consumption for each of
the on-board peripheral blocks. The values were deter-
mined with the peripheral clock running at maximum
frequency, typical conditions, and no I/O loads.
NOTE: *ICORE = 58 mA MAX., IIO = 19 mA MAX., all active
Table 9. Current Consumption by Mode
Table 10. Peripheral Current Consumption
