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LH75411N0Q100C0NXPN/a35avaiSystem-on-Chip
LH75411-N0Q100C0 |LH75411N0Q100C0NXPN/a35avaiSystem-on-Chip


LH75411N0Q100C0 ,System-on-Chip IMPORTANT NOTICE Dear customer, stAs from June 1 , 2007 NXP Semiconductors has acquired the ..
LH75411-N0Q100C0 ,System-on-ChipFeatures of the LH75401� Highly Integrated System-on-Chip � Color and Grayscale Liquid Crystal Disp ..
LH79520N0Q000B1 ,System-on-Chip IMPORTANT NOTICE Dear customer, stAs from June 1 , 2007 NXP Semiconductors has acquired the ..
LH79524N0F100A1 ,System-on-ChipFeatures (I S)� High Performance: 76.205 MHz CPU Speed, � Watchdog Timer50.803 MHz maximum AHB cloc ..
LH7A404N0F000B3 ,32-Bit System-on-ChipFeatures include 80 kB on-chip SRAM,� USB 2.0 Full Speed Devicefully static design, power managemen ..
LH8550QLT1G , General Purpose Transistors PNP Silicon
LM317LMX/NOPB ,Small Size 100mA Wide Input Adjustable Voltage Regulator 8-SOIC -40 to 125Block Diagram..... 912 Mechanical, Packaging, and Orderable7.3 Feature Description.... 10Informatio ..
LM317LN ,3-Terminal Adjustable Regulator SNVS775L–MARCH 2000–REVISED JANUARY 20185 Pin Configuration and FunctionsLP Plastic PackageD Packa ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorOrder this document by LM317L/D Order this document by LM317L/D* * * ** *LOW LOW CURRENT CURRENTTHR ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable RegulatorELECTRICAL CHARACTERISTICS OF LM217L (refer to the test circuits, T = - 40 to 125°C,JV -V =5V,I = 4 ..
LM317LZ ,3-Terminal 0.1A Positive Adjustable Regulatorapplications. Since the regulator isn Available in TO-92, SO-8, or 6-Bump micro SMD“floating” and s ..


LH75411N0Q100C0-LH75411-N0Q100C0
System-on-Chip
IMPORTANT NOTICE
Dear customer,
As from June 1st , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data
sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use /microcontrollers for indicated sales addresses use (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the
version)
- Copyright © (year) by SHARP Corporation.
is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via
e-mail or phone (details via ). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document.
NXP Semiconductors
LH75401/LH75411
Product data sheet System-on-Chip
DESCRIPTION

The NXP BlueStreak LH75401/LH75411 family con-
sists of two low-cost 16/32-bit System-on-Chip (SoC)
devices. LH75401 — contains the superset of features. LH75411 — similar to LH75401, without CAN 2.0B.
COMMON FEATURES
Highly Integrated System-on-Chip ARM7TDMI-S™ Core High Performance (84 MHz CPU Speed) Internal PLL Driven or External Clock Driven Crystal Oscillator/Internal PLL Can Operate with
Input Frequency Range of 14 MHz to 20 MHz 32 kB On-chip SRAM 16 kB Tightly Coupled Memory (TCM) SRAM 16 kB Internal SRAM Clock and Power Management Low Power Modes: Standby, Sleep, Stop Eight Channel, 10-bit An alog-to-Digital Converter Integrated Touch Screen Controller Serial interfaces Two 16C550-type UARTs supporting baud rates
up to 921,600 baud (requires crystal frequency of
14.756 MHz). One 82510-type UART supporting baud rates up
to 3,225,600 baud (requires a system clock of MHz). Synchronous Serial Port Motorola SPI™ National Semiconductor Microwire™ Texas Instruments SSI Real-Time Clock (RTC) Three Counter/Timers Capture/Compare/PWM Compatibility Watchdog Timer (WDT) Low-Voltage Detector JTAG Debug Interface and Boundary Scan Single 3.3 V Supply 5 V Tolerant Digital I/O XTALIN and XTAL32IN inputs are 1.8 V ± 10% 144-pin LQFP Package 40C to +85C Operating Temperature
Unique Features of the LH75401
Color and Grayscale Liquid Crystal Display (LCD)
Controller 12-bit (4,096) Direct Mode Color, up to VGA 8-bit (256) Direct or Palettized Color, up to SVGA 4-bit (16) Direct Mode Color/Grayscale, up to XGA 12-bit Video Bus Supports STN, TFT, HR-TFT, and AD-TFT
Displays. CAN Controller that supports CAN version 2.0B.
Unique Features of the LH75411
Color and Grayscale LCD Controller (LCDC) 12-bit (4,096) Direct Mode Color, up to VGA 8-bit (256) Direct or Palettized Color, up to SVGA 4-bit (16) Direct Mode Color/Grayscale, up to XGA 12-bit Video Bus Supports STN, TFT, HR-TFT, and AD-TFT
Displays.
LH75401/LH75411 System-on-Chip
NXP Semiconductors
ORDERING INFORMATION
Table 1. Ordering information
System-on-Chip LH75401/LH75411
NXP Semiconductors
LH75401 BLOCK DIAGRAM
Figure 1. LH75401 Block Diagram
LH75401/LH75411 System-on-Chip
NXP Semiconductors
LH75411 BLOCK DIAGRAM
Figure 2. LH75411 Block Diagram
System-on-Chip LH75401/LH75411
NXP Semiconductors
PIN CONFIGURATION
Figure 3. LH75401/LH75411 pin configuration
LH75401/LH75411 System-on-Chip
NXP Semiconductors
LH75401 Numerical Pin Listing
Table 2. LH75401 Numerical Pin List
System-on-Chip LH75401/LH75411
NXP Semiconductors
Table 2. LH75401 Numerical Pin List (Cont’d)
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Table 2. LH75401 Numerical Pin List (Cont’d)
System-on-Chip LH75401/LH75411
NXP Semiconductors
NOTES:
Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with ‘n’ are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) LINREGEN activation requires a 0  pull-up to VDD.
Table 2. LH75401 Numerical Pin List (Cont’d)
LH75401/LH75411 System-on-Chip
NXP Semiconductors
LH75401 Signal Descriptions
Table 3. LH75401 Signal Descriptions
System-on-Chip LH75401/LH75411
NXP Semiconductors
Table 3. LH75401 Signal Descriptions (Cont’d)
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Table 3. LH75401 Signal Descriptions (Cont’d)
System-on-Chip LH75401/LH75411
NXP Semiconductors
Table 3. LH75401 Signal Descriptions (Cont’d)
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Table 3. LH75401 Signal Descriptions (Cont’d)
System-on-Chip LH75401/LH75411
NXP Semiconductors
LH75411 Numerical Pin Listing
Table 4. LH75411 Numerical Pin List
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Table 4. LH75411 Numerical Pin List (Cont’d)
System-on-Chip LH75401/LH75411
NXP Semiconductors
Table 4. LH75411 Numerical Pin List (Cont’d)
LH75401/LH75411 System-on-Chip
NXP Semiconductors
NOTES:
Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with ‘n’ are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) LINREGEN activation requires a 0  pull-up to VDD.
Table 4. LH75411 Numerical Pin List (Cont’d)
System-on-Chip LH75401/LH75411
NXP Semiconductors
LH75411 Signal Descriptions
Table 5. LH75411 Signal Descriptions
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Table 5. LH75411 Signal Descriptions (Cont’d)
System-on-Chip LH75401/LH75411
NXP Semiconductors
Table 5. LH75411 Signal Descriptions (Cont’d)
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Table 5. LH75411 Signal Descriptions (Cont’d)
System-on-Chip LH75401/LH75411
NXP Semiconductors
NOTES:
These pin numbers have multiplexed functions. Signals preceded with ‘n’ are active LOW.
Table 5. LH75411 Signal Descriptions (Cont’d)
LH75401/LH75411 System-on-Chip
NXP Semiconductors
FUNCTIONAL OVERVIEW
ARM7TDMI-S Processor

The LH75401/LH75411 microcontrollers feature the
ARM7TDMI-S core with an Advanced High-Performance
Bus (AHB) 2.0 interface. The ARM7TDMI-S is a 16/32-bit
embedded RISC processor and a member of the ARM7
Thumb family of processors. For more information, visit
the ARM Web site at www.arm.com.
Bus Architecture

The LH75401/LH75411 microcontrollers use the
ARM Advanced Microcontroller Bus Architecture (AMBA)
2.0 internal bus protocol. Three AHB masters control
access to external memory and on-chip peripherals: The ARM processor fetches instructions and trans-
fers data The Direct Memory Access Controller (DMAC) trans-
fers from memory to memory, from peripheral to
memory, and from memory to peripheral The LCDC refreshes an LCD panel with data from
the external memory or from internal memory if the
frame buffer is 16 kB or less.
The ARM7TDMI-S processor is the default bus mas-
ter. An Advanced Peripheral Bus (APB) bridge is pro-
vided to access to the various APB peripherals.
Generally, APB peripherals are serviced by the ARM
core. However, if they are DMA-enabled, they are also
serviced by the DMAC to increase system performance
Power Supplies

Five-Volt-tolerant 3.3 V I/Os are employed. The
LH75401/LH75411 microcontrollers require a single
3.3 V supply. The core logic requires 1.8 V, supplied by
an on-chip linear regulator. Core logic power may also
be supplied externally to achieve higher system
speeds. See the Electrical Specifications.
Clock Sources

The LH75401/LH75411 microcontrollers may use
two crystal oscillators, or an externally supplied clock.
There are two clock trees: One clock tree drives an internal Phase Lock Loop
(PLL) and the three UARTs. It supports a crystal
oscillator frequency range from 14 MHz to 20 MHz. The other is a 32.768 kHz oscillator that generates a Hz clock for the RTC. (Use of the 32.768 kHz crys-
tal for the Real Time Clock is optional. If not using the
crystal, tie XTAL32IN to VSS and allow XTAL32OUT
to float.)
The 14-to-20 MHz crystal oscillator drives the UART
clocks, so an oscillator frequency of 14.7456 MHz is rec-
ommended to achieve modem baud rates.
The PLL may be bypassed and an external clock
supplied at XTALIN; the SoC will operate to DC with the
PLL disabled. When doing so, allow XTALOUT to float.
The input clock with the PLL bypassed will be twice the
desired system operating frequency, and care must be
taken not to exceed the maximum input clock voltage.
Figure 4. LH75401 System Application Example
System-on-Chip LH75401/LH75411
NXP Semiconductors
Reset Generation
EXTERNAL RESETS

Two external signals generate resets to the
ARM7TDMI-S core: nPOR sets all internal registers to their default state
when asserted. It is used as a Power-On Reset. nRESETIN sets all internal registers, except the
JTAG circuitry, to their default state when asserted.
When nPOR is asserted, nRESETIN defines the
microcontroller Test Mode. When nPOR is released,
nRESETIN behaves during Reset as described
previously.
INTERNAL RESETS

There are two types of Internal Resets generated: System Reset
RTC Reset.
System and RTC Resets are asserted by: An External Reset (a logic LOW signal on the exter-
nal nRESETIN or nPOR input pin) A signal from the internal Watchdog Timer A Soft Reset.
The reset latency depends on the PLL lock state.
AHB Master Priority and Arbitration

The LH75401/LH75411 microcontrollers have three
AHB masters: ARM processor
DMAC LCD Controller.
Each AHB master has a priority level that is perma-
nent and cannot change.
Memory Interface Architecture

The LH75401/LH75411 microcontrollers provide the
following data-path management resources on chip: AHB and APB data buses 16 kB of zero-wait-state TCM SRAM accessible via
processor 16 kB of internal SRAM accessible via processor,
DMAC, and LCDC A Static Memory Controller (SMC) that controls
access to external memory A 4-stream general-purpose DMAC.
All external and internal system resources are
memory-mapped. This memory map partition has three
views, based on the setting of the REMAP bits in the
Reset, Clock, and Power Controller (RCPC).
The second partitioning of memory space is the
dividing of the segments into sections. The external
memory segment is divided into eight 64 MB sections,
of which the first four are used, each having a chip
select associated with it. Access to any of the last four
sections does not result in an external bus access and
does not cause a memory abort. The peripheral regis-
ter segment is divided into 4 kB peripheral sections, 21
of which are assigned to peripherals.
Table 6. Bus Master Priority
Table 7. Memory Mapping
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Static Random Access Memory Controller

The LH75401/LH75411 microcontrollers have 32 kB
of Static Random Access Memory (SRAM) organized
into two 16 kB blocks: 16 kB of TCM 0 Wait State SRAM is available to the
processor as an ARM7TDMI-S bus slave. 16 kB of internal SRAM is available as an AHB slave
and accessible via processor, DMAC, and LCDC.
Each memory segment is 512 MB, though the TCM
and internal SRAMs are 16 kB each in size. Any
access beyond the first 16 kB is mapped to the lower kB, but does not cause a data or prefetch abort.
Static Memory Controller (SMC)

The Static Memory Controller (SMC) is an AMBA
AHB slave peripheral that provides the interface
between the LH75401/LH75411 microcontrollers and
external memory devices.
SMC FEATURES
Provides four banks of external memory, each with a
maximum size of 16 MB. Supports memory-mapped devices, including
Random Access Memory (RAM), Read Only
Memory (ROM), Flash, and burst ROM Supports external bus and external device widths of
8 and 16 bits Supports Asynchronous Burst Mode read access for
Burst Mode ROM devices, with up to 32 independent
wait states for read and write accesses Supports indefinite extended wait states via an
external hardware pin (nWAIT) Supports varied bus turnaround cycles (1 to 16)
between a read and write operation
Direct Memory Access Controller (DMAC)

One central DMAC services all peripheral DMA
requirements for the DMA-capable peripherals listed in
Table 9.
The DMA is controlled by the system clock. It has an
APB slave port for programming of its registers and an
AHB port for data transfers.
DMAC FEATURES
Four data streams that can be used to service: Four peripheral data streams (peripheral-to-
memory or memory-to-peripheral) Three peripheral data streams and one memory-
to-memory data stream. Three transfer modes: Memory to Memory (selectable on Stream3) Peripheral to Memory (all streams) Memory to Peripheral (all streams). Built-in data stream arbiter Seven programmable registers for each stream Ability for each stream to in dicate a transfer error via
an interrupt 16-word First-In, First Out (FIFO) array, with pack
and unpack logic to handle all input/output combina-
tions of byte, half-word, and word transfers APB slave port allows th e ARM core to program
DMAC registers
Table 8. APB Peripheral Register Mapping
Table 9. DMAC Stream Assignments
System-on-Chip LH75401/LH75411
NXP Semiconductors
Color LCD Controller (CLCDC)

The CLCDC is an AMBA master-slave module that
connects to the AHB. It translates pixel-coded data into
the required formats and timings to drive single/dual
monochrome and color LCD panels. Packets of pixel-
coded data are fed, via the AHB interface, to two inde-
pendently programmable, 32-bit-wide DMA FIFOs.
Each FIFO is 16 words deep by 32 bits wide.
The CLCDC generates a single combined interrupt
to the Vectored Interrupt Controller (VIC) when an
interrupt condition becomes true for upper/lower panel
DMA FIFO underflow, base address update significa-
tion, vertical compare, or bus error.
NOTE:
LH75401 and LH75411 microcontrollers support full-color
operation.
CLCDC FEATURES
STN, Color STN, TFT, HR-TFT, and AD-TFT Fully Programmable Timing Controls Advanced LCD Interface for displays with a low
level of integration, such as HR-TFT and AD-TFT Programmable Resolution Up to VGA (640 × 480 DPI), 12-bit Direct Mode
Color Up to SVGA (800 × 600 DPI), 8-bit Direct/Pal-
ettized Color Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/
Grayscale Direct or Palettized Colors Single and Dual Panels Supports Sharp and non-Sharp Panels CLCDC Outputs Availabl e as General Purpose
Inputs/Outputs (GPIOs) if LCDC is Not Needed Additional Features Fully programmable horizontal and vertical timing
for different display panels 256-entry, 16-bit palette RAM physically arranged
as a 128 × 32-bit RAM AC bias signal for STN panels and a data-enable
signal for TFT panels. Programmable Panel-related Parameters STN mono/color or TFT display Bits-per-pixel STN 4- or 8-bit Interface Mode STN Dual or Single Panel Mode AC panel bias Panel clock frequency Number of panel clocks per line Signal polarity, active HIGH or LOW
ADVANCED LCD INTERFACE

The Advanced LCD Interface (ALI) allows for direct
connection to ultra-thin panels that do not include a tim-
ing ASIC. It converts TFT signals from the Color LCD
controller to provide the proper signals, timing and levels
for direct connection to a panel’s Row and Column driv-
ers for AD-TFT, HR-TFT, or any technology of panel that
allows for a connection of this type. The ALI also pro-
vides a bypass mode that allows interfacing to the built-
in timing ASIC in standard TFT and STN panels.
NOTES:
The Advanced LCD Interface pertains to the LH75401 and
LH75411 microcontrollers. VGA and XGA modes require 66 MHz core speed.
Universal Asynchronous
Receiver Transmitters (UARTs)

The LH75401/LH75411 microcontrollers incorporate
three UARTs, designated UART0, UART1, and UART2.
UART 0 AND 1 FEATURES
Similar functionality to the industry-standard 16C550 Supported baud rates up to 921,600 baud (given an
external crystal frequency of 14.756 MHz) Supported character formats: Data bits per character: 5, 6, 7, or 8 Parity generation and detection: Even, odd, stick,
or none Stop bit generation: 1 or 2 Full-duplex operation Separate transmit and receive FIFOs, with: Programmable depth (1 to 16) Programmable-service ‘trigger levels’ (1/8, 1/4,
1/2, 3/4, and 7/8) Overrun protection. Programmable baud-rate generator that: Enables the UART input clock to be divided by 16
to 65,535 × 16 Generates an internal clock common to both
transmit and receive portions of the UART. DMA support Support for generating and detecting breaks during
UART transactions Loopback testing.
LH75401/LH75411 System-on-Chip
NXP Semiconductors
UART 2 FEATURES
Similar functionality to the industry-standard 82510 Supported baud rates up to 3,225,600 baud (given a
system clock of 51.6096 MHz) 5, 6, 7, 8, or 9 data bits per character Even, odd, HIGH, LOW, software, or no parity-bit
generation and detection 3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation LAN address flag Full-duplex operation Separate transmit and receive FIFOs, with program-
mable depth (1 or 4). Each FIFO has overrun protec-
tion and: Programmable receive trigger levels: 1/4, 1/2,
3/4, or full Programmable transmit trigger levels: empty, 1/4,
1/2, 3/4. Two 16-bit baud-rate generators. One interrupt that can be triggered by transmit and
receive FIFO thresholds, receive errors, control
character or address marker reception, or timer
timeout Generation and detection of breaks during UART
transactions Support for local loopback, remote loopback, and
auto-echo modes LAN Address Mode.
Timers

The LH75401/LH75411 microcontrollers have three
16-bit timers. The timers are clocked by the system
clock, but have an internal scaled-down system clock
that is used for the Pulse Width Modulator (PWM) and
compare functions.
All counters are incremented by an internal pre-
scaled counter clock or external clock and can gener-
ate an overflow interrupt. All three timers have separate
internal prescaled counter clocks, with either a com-
mon external clock or a prescaled version of the sys-
tem clock. Timer 0 has five Capture Registers and two Com-
pare Registers. Timer 1 and Timer 2 have two Capture and two Com-
pare Registers each.
The Capture Registers have edge-selectable inputs
and can generate an interrupt. The Compare Registers
can force the compare output pin either HIGH or LOW
upon a match.
The timers support a PWM Mode that uses the two
Timer Compare Registers associated with a timer to
create a PWM. Each timer can generate a separate
interrupt. The interrupt becomes active if any enabled
compare, capture, or overflow interrupt condition
occurs. The interrupt remains active until all compare,
capture, and overflow interrupts are cleared.
Real Time Clock (RTC)

The RTC is an AMBA slave module that connects to
the APB. The RTC provides basic alarm functions or
acts as a long-time base counter by generating an inter-
rupt signal after counting for a programmed number of
cycles of an RTC input. Counting in 1-second intervals
is achieved using a 1 Hz clock input to the RTC.
RTC FEATURES
32-bit up-counter with programmable load Programmable 32-bit match Compare Register Software-maskable interrupt that is set when the Coun-
ter and Compare Registers have identical values.
Controller Area Network (CAN)

The CAN 2.0B Controller is an AMBA-compliant
peripheral that connects as a slave to the APB. The
CAN Controller is located between the processor core
and a CAN Transceiver, and is accessed through the
AMBA port.
CAN communications are performed serially, at a
maximum frequency of 1 MB/s, using the TX (transmit)
and RX (receive) lines. The TX and RX signals for data
transmission and reception provide the communications
interface between the CAN Controller and the CAN bus.
All peripherals share the TX and RX lines, and always
see the common incoming and outgoing data.
Bus arbitration follows the CAN 2.0A and CAN 2.0B
specifications. The bus is always controlled by the
node with the highest priority (lowest ID). Only after the
bus has been released can the next highest priority
node control it. Transmit and receive errors are han-
dled according to the CAN protocol.
Bus timing is critical to the CAN protocol. Therefore,
the CAN Controller has two programmable Bus Timing
Registers that define timing parameters.
NOTE:
The CAN Controller pertains to the LH75401 microcon-
trollers.
System-on-Chip LH75401/LH75411
NXP Semiconductors
CAN 2.0B FEATURES
Full compliance with 2.0A and 2.0B Bosch
specifications Supports 11-bit and 29-bit identifiers Supports bit rates up to 1Mbit/s 64-byte receive FIFO Software-driven bit-rate detection for hot plug-in
support Single-shot transmission option Acceptance filtering Listen Only Mode Reception of ‘own’ messages Error interrupt generated for each CAN bus error Arbitration-lost interrupt with record of bit position Read/write error counters Last error register Programmable error-limit warning.
Analog-to-Digital Converter (ADC)/
Brownout Detector

The ADC is an AMBA-compliant peripheral that con-
nects as a slave to the APB. The ADC block consists of
an 8-channel, 10-bit Analog-to-Digital Converter with
integrated Touch Screen Controller. The complete
Touch Screen interface is achieved by combining the
front-end biasing, control circuitry with analog-to-digital
conversion, reference generation, and digital control.
The ADC also has a programmable measurement
clock derived from the system clock. The clock drives
the measurement sequencer and the successive-
approximation circuitry.
The ADC includes a Brownout Detector. The Brown-
out Detector is an asynchronous comparator that com-
pares a divided version of the 3.3 V supply and a
bandgap-derived reference voltage. If the supply dips
below a Trip point, the Brownout Detector sets a status
register bit. The status bit is wired to the VIC and can
interrupt the processor core. This allows the Host Con-
troller to warn users of an impending shutdown and may
provide the ADC with sufficient time to save its state.
ADC/BROWNOUT DETECTOR FEATURES
10-bit fully differential Successive Approximation
Register (SAR) with integrated sample/hold 8-channel multiplexer for routing user-selected inputs
to the ADC in Single Ended and Differential Modes 16-entry × 16-bit-wide FIFO that holds the 10-bit
ADC output and a 4-bit tag number Front bias-and-control network for Touch Screen Touch-pressure sensing circuits Pen-down sensing circuit and interrupt generator Voltage-reference generator that is independently
controlled Conversion automation function to minimize control-
ler interrupt overhead Brownout Detector.
Synchronous Serial Port (SSP)

The SSP is a master-only interface for synchronous
serial communication with slave peripheral devices that
have a Motorola SPI, National Semiconductor
Microwire, or Texas Instruments DSP-compatible
Synchronous Serial Interface (SSI).
The SSP performs serial-to-parallel conversion on
data received from a peripheral device. The transmit and
receive paths are buffered with internal FIFO memories.
These memories store eight 16-bit values independently
in both transmit and receive modes. During transmission: Data writes to the transmit FIFO via the APB
interface. The transmit data is queued for parallel-to-serial
conversion onto the transmit interface. The transmit logic formats the data into the appropri-
ate frame type: Motorola SPI National Semiconductor Microwire Texas Instruments DSP-compatible SSI.
SSP FEATURES
SSI in Master Only M ode. The SSP performs serial
communications as a master device in one of three
modes: Motorola SPI Texas Instruments DSP-compatible synchronous
serial interface National Semiconductor Microwire. Two 16-bit-wide, 8-entry-deep FIFOs, one for data
transmission and one for data reception. Supports interrupt-driven data transfers that are
greater than the FIFO watermark. Programmable clock bit rate. Programmable data frame size, from 4 to 16 bits long,
depending on the size of data programmed. Each
frame transmits starting with the most-significant bit. Four interrupts, each of which can be individually
enabled or disabled using the SSP Control Register
bits. A combined interrupt is also generated as an
OR function of the individual interrupt requests.
LH75401/LH75411 System-on-Chip
NXP Semiconductors
Watchdog Timer (WDT)

The WDT consists of a 32-bit down-counter that
allows a selectable time-out interval to detect malfunc-
tions. The timer must be reset by software periodically.
Otherwise, a time-out occurs, interrupting the system.
If the interrupt is not serviced within the timeout period,
the WDT triggers the RCPC to generate a System
Reset. If the WDT times out, it sets a bit in the RCPC
Reset Status Register.
The WDT supports 16 selectable time intervals, for
a time-out of 216 through 231 system clock cycles. All
Control and Status Registers for the Watchdog Timer
are accessed through the APB.
WDT FEATURES
Counter generates an interrupt at a set interval and
the count reloads from the pre-set value after reach-
ing zero. Default timeout period is set to the minimum timeout
of 216 system clock cycles. WDT is driven by the APB. Built-in protection mechanism guards against
interrupt-service failure. WDT can be programmed to trigger a System Reset
on a timeout. WDT can be programmed to trigger an interrupt on
the first timeout; then, if the service routine fails to
clear the interrupt, the next WDT timeout triggers a
System Reset.
Table 10. SSP Modes
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