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LH0023CGNSN/a47avaiSAMPLE AND HOLD CIRCUITS
LH0043CGNSN/a2avaiSAMPLE AND HOLD CIRCUITS
LH0043GNSN/a4avaiSAMPLE AND HOLD CIRCUITS


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LH0023CG-LH0043CG-LH0043G
SAMPLE AND HOLD CIRCUITS
LH0023I LH0023C/ LH0043/LH0043C
I National
Semiconductor
LH0023/LH0023C/LH0043/LH0043C Sample
and Hold Circuits
General Description
The LH0023/LH0023C and LH0043/LH004SC are com-
plete sample and hold circuits including input buffer amplifi-
er, FET output amplifier, analog signal sampling gate, TTL
compatible logic circuitry and level shifting. They are de-
signed to operate from standard k15V DC supplies, but
provision is made on the LH0023/LH00230 for connection
of a separate + 5V logic supply in minimum noise applica-
tions. The principal difference between the LH0023/
LH0023C and the LH0043/LH0043C is a 10:1 trade-off in
performance between sample accuracy and sample acquisi-
tion time. Devices are pin compatible except for TTL logic
polarity.
The LH0023/LH00230 and LH0043/LH00430 are ideally
suited for a wide variety of sample and hold applications
including data acquisition, analog to digital conversion, syn-
chronous demodulation, and automatic test setup. They of-
fer significant cost and size reduction over equivalent mod-
ule or discrete designs. Each device is available in a her-
metic TO-8 package and is completely specified over both
full military and industrial temperature ranges.
The LH0023 and LH0043 are specified for operation over
the -55"C to + 125°C military temperature range. The
LH0023C and LH0043C are specified for operation over the
- 25''C to + 85''C temperature range.
Features
LH0023n.H0023C
II Sample atxruracy-0.01% max
I Hold drift rattr-0.5 mV/sec typ
11 Sample acquisition titma-100 HS max for 20V
I: Aperture time-150 ns typ
a Wide analog input range- 110V min
I: Logic input-TTL/DTL compatible
u Offset adjustable to zero with single 10k pot
II Output short circuit proof
LH0043ILH00430
l: Sample acquisition tirtw-15 p.s max for 20V
4 us typ for 5V
I: Aperture time-20 ns typ
I: Hold drift rate-I mV/see typ
a Sample ttttcurator-thes max
I: Wide analog input range- :e 10V min
I: Logic input-TTL/DTI. compatible
u Offset adiustahla to zero with single 10k pot
n Output short circuit protection
Connection Diagrams
LH0023/ LH0023C
" STORAGE
ADJUST
MNT ttttWOT
GROUND
LH0043/LH0043C
" S‘I‘MMGE
OFFSET
ADIUSI
ANALOG
lOGIC -
IMU‘I V
"Tie for operation . IL. tmtr00
with v+ z 15V only ttec u.c.
mp win
my mm TL/K/5693-8
TL/K15693-1
Order Number LHOOZSG or
LH0023CG or LH0043G or
LH0043CG
See Package Number G123
Block Diagrams
LH0023n.H0023C
urrssr
ADJUST
s, T T
AnALoc I
I r'-'o OUTPUT
I swam:
I I cAucnon
LOGIC I J -NVV-o lt'
----0 To.
‘Tle to pin 8 for operation without Voc supply. ' Itcc
-o ttMt
---o ll"
TL/K/5693-9
LH0043ILH0043C
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TL/K/5693-10
08700H1ISVOOH'l/OSZOOH'I/SZOOH'I
LH0023/LH0023C/LH0043/LH0043C
Absolute Maximum Ratings
If Mllltary/Aerospace speclfled devices are required,
please contact the National Semlconductor Sales
OfflCefDlstrtttutttra for availability and specifications.
Power Dissipation
Output Short Circuit Duration
Operating Temperature Range
See graph
Continuous
SUPP" Voltage (VS) * 20V LH0023, LH0043 --55% to + 125°C
Pit' Supply Voltage (Vcc) LH0023, LH0023C + 7.0V LH0023C, LH00430 - 25'C to + 85'C
Logic lnputVoltage Nts) + 5.5V Storage Temperature Range -65'C to - 150°C
Analog Input Voltage (Ms) * 15V Lead Soldering (10 seconds) 300''C
Electrical Characteristics LH0023/LH0023C (Note 1)
Parameter thmdrtlontt LH0023 LH00230 Units
Min Typ Max Mln Typ Max
Sample (Logic "I'') Vcc = 4.5V 2.0 2.0 V
Input Voltage
Sample (Logic "I'') 1/s = 2.4V, Vcc = 5.5V 5.0 5.0 WA
Input Current
Hold (Logic "O") Voc = 4.5V 0.8 0.8 V
Input Voltage
Hold (Logic "0") V5 = 0.4V, VCC = 5.5V 0.5 0.5 mA
Input Current
Analoglnput k10 sell t10 All V
Voltage Range
Supply Current - ho Vs = 0V, Vs = 2V, 4 5 6 4.5 6 mA
V1 1 = 0V
Supply Current - I12 Vs = ov, V6 = 0.4V, 4.5 6 4.5 6 mA
V11 = 0V
Supply Current - Its V8 = 5.0V, Vs = 0 1.0 1.6 1.0 1.6 mA
Sample Accuracy VOUT = 1 10V (Full Scale) 0.002 0.01 0.002 0.02 %
DC Input Resistance Sample Mode 500 1000 300 1000 kft
Hold Mode 20 25 20 25 kit
Input Current - Is Sample Mode 0.2 1.0 0.3 1.5 11A
Input Capacitance 3.0 3.0 pF
Leakage Current - Vs = i10V; V11 = d:10V, 10.0 200 20.0 500 pA
pin 1 -55°CSTA s 125''C
Vs = :10V;V11 = i10V 5.0 2.0 nA
Drift Rate VOUT = A5V, Cs = 0.01 pF, 0.5 0.5 mV/s
TA = 25''C
Drift Rate VOUT = i10V, 1.0 20 2.0 50 mV/s
Cs = 0.01 pF, TA = 25'C
Drift Rate vour = i10V, 0.50 0.2 mV/ms
Cs = 0.01 11F
Aperture Time 150 150 ns
Sample Acquisition AVouT = 20V, 50 100 50 100 ps
Time Cs = 0.01 pF
Output Amplifier 1.5 3.0 1.5 3.0 V/ps
Slew Rate
Output Offset Voltage Rs 3 10k, Vs = ov, , 20 i 20 mV
(without null) V6 == 2,0V
Analog Voltage RL 21k,TA = 25'C :10 *11 210 211 v
OutputRange RL 2 2k :10 112 k10 :12 V
Not. 1: Unless otherwise noted, these specifications apply for v+ = +15V, Vcc = +5V, - " -15V, pin 9 grounded, a 0.01pF capacitor connected between
pln 1 and ground over the temperature range -SS'C to +125'C tor the LH0023, and -2IPC to +85'Ctor the LH0023C. Alt typieal values are for TA -- 25'C.
Electrical Characteristics LHoo43/LH0043C: (Note 2)
Parameter Conditions LH0043 LH0043C Unlts
Min Typ Max Min Typ Max
Hold (Logic "1") 2.0 2.0 V
Input Voltage
Hold (Logic"1") V6 = 2.4V 5.0 5.0 pA
Input Current
Sample (Logic "o'') 0.8 0.8 V
Input Voltage
Sample (Logic "o") Ve = 0.4V 1.5 1.5 mA
Input Current
Analoglnput i10 111 i10 All V
Voltage Range
Supply Current Vs = 0V, V6 = 2V, V11 = 0V 20 22 20 22 mA
Vs == ov, Ve = 0.4V, 14 18 14 18 mA
V11 -- 0V
Sample Accuracy VOUT = 110V (Full Scale) 0.02 0.1 0.02 0.3 M,
DC Input Resistance To = 25'C 1010 1012 1010 1012 n
Input Current - Is 1.0 5.0 2.0 10.0 nA
Input Capacitance 1.5 1.5 pF
Leakage Current- Vs -- i10V; V11 = At0, 10 25 20 50 PA
pin 1 Tc = 25°C
Vs = i10V;V11 = i10V 10 25 2 5 nA
Drift Rate VOUT = 11W, Cs = 0.001 pF, 10 25 20 50 mV/s
To = 25°C
Drift Rate VOUT --- h10V, Cs = 0.001 pF 10 25 2 5 mV/ms
Drift Rate VOUT = i10V. Cs == 0.01 pf, 1 2.5 2 5 mV/s
To = 25°C
Drift Rate VOUT = i10V, Cs = 0.01 pF 1 2.5 0.2 0.5 mV/ms
Aperture Time 20 60 20 60 ns
Sample Acquisition AVOUT = 20V, Cs --- 0.001 p. F 10 15 10 15 us
Time AVOUT = 20V, Cs == 0.01 pF 30 50 30 50 us
AVOUT = 5V, Cs = 0.001 11F 4 4 p3
OutputAmplifier VOUT == w, Cs = 0.001 pF 1.5 3.0 1.5 3.0 V/ps
Slew Rate
Output OffsetVoltage Rs s 10k, Vs = 0V, V6 T.= 0V &40 A40 mV
(without null)
Analog Voltage RL21k,TA = 25°C 110 t11 :10 tll V
OutputFlange RL22k :10 t12 1:10 tlt! V
Note 2: Unless otherwise noted, these specifications apply for V+ = 115V, v- = -15V, pin 9 grounded. a 6000 pF capacitor connected between pin 1 and
ground over the temperature range - 55'C to +125'C for the LHOMS. and -25t to +85''C tor the LH00430. All typical values are for T3 _ 25'C.
OSPOOH‘IIEVOOH'IIOGZOOH'IISZOOH'I
LH0023ILH0023C/LH0043/LH0043C
Typical Performance Characteristics
Power Dlsslpation
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TEMIATIMN'CI
Sample Acqulsltlon
T1rmt--LH0028
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UUWUT VOLTAGE (V)
Drift " Capadtanco
(LH0023)
t " I trt
01:31 MI MI " I "
CAPAEIYIICE w
(LH0023)
I." H , " 1” Il II "Ot ttMN ma
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Sample Acquisition
Tmt-LH0048
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Pln 1 Leakage Current
" Temperature
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(LH0043)
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TL/K/5693-3
Typical Applications
How to Bulld a Sample and Hold Module
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TLlK/5693-4
Note 1: C1 is polystyrene.
Note 2: C2, C3, C4 are ceramic disc.
Note 3: Jumper 7-8 and C4 not required for LH0043.
Note 4.. R1 optional if zero trim is required.
Forcing Function Setup Ior Automatic: Test Gear
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TL/K/5693-1 1
‘See op amp selection guide tor details Most popular types Include LH0052, LM108, LM1 12, LHOOM, LHOOGS. and LH0038.
08700H1[SWOH'I/GSZOOH'l/SZOOH'I
LH0023/LHOO23C/LH0043/LH0043C
Typical Applications (Continued)
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Single Pulse Sampler
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TUK15693-13
Applications Information
1.0 DRIFT ERROR MINIMIZATION
In order to minimize drift error, care in selection of Cs and
layout of the printed circuit board is required. The capacitor
should be of high quality Teflon, polycarbonate. or polysty-
rene construction. Board cleaniness and layout are critical
particularly at elevated temperatures. See AN-63 for do.
tailed recommendations. A guard conductor connected to
the output surrounding the storage node (pin I) will be help-
ful in meeting severe environmental conditions which would
otherwise cause leakage across the printed circuit board.
2.0 CAPACITOR SELECTION
Tho size of the capacitor is dictated by the required drift rate
and acquisition time. The drift is determined by the leakage
current at pin 1 and may be calculated by d3? = b,, where IL
is the total leakage current at pin 1 of the device, and CS is
the value of the storage capacitor.
2.1 Capattitor Selection - LH0023
At room temperature leakage current for the LH0023 is ap-
proximately 100 pA. A drift rate of 10 mV/sec would require
a 0.01 pF capacitor.
For values of Cs up to 0.01 p.F the acquisition time is limited
by the slew rate of the input buffer amplifier, Al, typically 0.5
V/p.s. Beyond this point, current availability to charge Cs
also enters the picture. The acquisition time is given by:
2Aeo ROS
- = x -3
1A a " fi-t x106 2 IO JAeo RC,
where: Fl =the internal resistance in series with Cs
Aeo = change in voltage sampled
An average value for R is approximately 600 ohms. The
expression for tA reduces to:
Aeo Cs
For a -10V to +10V change and Cs-- .05 pF, acquisition
time is typically 50 ps.
2.2 Capacitor Seletttltm-LH0043
At 25°C case temperature. the leakage current for the
LH0043G is approximately 10 pA. so a drift rate of 5 mV/s
would require a capacitor of Cs = 10ot012/5o103 = 2000
pF or larger.
For values of Cs below about 5000 pF, the acquisition time
of the LH0043G will be limited by the slew rate of the output
amplifier (the signal will be acquired, in the sense that the
voltage will be stored on the capacitor, in much less time as
dictated by the slew rate and current capacity of the input
amplifier, but it will not be available at the output). For larger
values of storage capacitance, the limitation is the current
sinking capability of the input amplifier, typically 10 mA. With
Cs -- 0.01 pF, the slew rate can be estimated by
Pd = 10 ot0-3
dt 0.01 o To-ty
signal change of 5ps.
3.0 OFFSET NULL
Provision is made to null both the LH0023 and LH0043 by
use of a 10k pot between pins 3 and 4. Offset null should be
accomplished in the sample mode at one half the input volt.
age range tor minimum average error.
4.0 SWITCHING SPIKE MlNlMlZATION-LHOO43
A capacitive divider is formed by the storage capacitor and
the capacitance of the internal FET switch which causes a
small error current to be injected into the storage capacitor
at the termination of the sample interval. This can be con-
sidered a negative DC offset and nulled out as described in
(3.0), or the transient may be nulled by coupling an equal
but opposite signal to the storage capacitor. This may be
accomplished by connecting a capacitor of about 30 pF (or
a trimmer) between the logic input (pin 6) and the storage
capacitor (pin I). Note that this capacitor must be chosen as
carefully as the storage capacitor itself with respect to leak-
age. The LH0023 has switch spike minimization circuitry
built into the device.
5.0 ELIMINATION OF THE 5V LOGIC SUPPLY - LH0023
The 5V logic supply may be eliminated by shorting pin 7 to
pin 8 which connects a 10k dropping resistor between the
+15V and Vc. Decoupling pin 8 to ground through 0.1 pF
disc capacitor is recommended in order to minimize tran-
sients in the output.
6.0 HEAT SINKING
The LH0023 and LH0043G may be operated without dam-
age throughout the military temperature range of ~55 to
+125°C (-25 to +85°C for the LHOOZSCG and
LH0043CG) with no explicit heat sink, however power dissi-
pation will cause the internal temperature to rise above am-
bient. A simple clip-on heat sink such as Wakefield
'215--1.9 or equivalent will reduce the internal tempera-
ture about 20°C thereby cutting the leakage current and drift
rate by one fourth at max. ambient. There is no internal
electrical connection to the case, so it may be mounted
directly to a grounded heat sink.
7.0 THEORY OF OPERATION-LH0023
The LH0023/LH00230 is comprised of input butter amplifi-
er, A1, analog switches, SI and sa a TTL to MOS level
= IV/ps or a slewing time for a 5 volt
OSVOOH'l/SVOOH'IIOSZOOH'I/SZOOH'I
LH0023/LH0023C/LH0043ILH0043C
Applications Information (Continued)
translator. and output buffer amplifier, A2. In the "sample"
mode, the logic input is raised to logic "I'' (Ve S 2.0V)
which closes S1 and opens S2. Storage capacitor, Cs, is
charged to the input voltage through S1 and the output
slews to the input voltage. In the "hold" mode, the logic
input is lowered to logic "0" (vs g 0.8V) opening SI and
closing S2. Cs retains the sample voltage which is applied to
the output via A2. Since SI is open, the input signal is over-
riden, and leakage across the MOS switch is therefore mini-
mized. With S1 open, drift is primarily determined by input
bias current of A2, typically 100 pA at 25'C.
7.1 Theory of Operation-LH0043
The LH0043/LH00430 is comprised of input buffer amplifier
A1, FET switch S1 operated by a TTL compatible level
translator, and output buffer amplifier A2. To enter the
"sample" mode, the logic input is taken to the TTL logic "0"
state (V6=0.8V) which commands the switch S1 closed
Alli.“
IOGIC'
mm J. l
TL/Kmma-7
and allows A1 to make the storage capacitor voltage equal
to the analog input voltage. in the "hold" mode (V6=2.0V).
SI is opened isolating the storage capacitor from the input
and leaving it charged to a voltage equal to the last analog
input voltage before entering the hold mode. Tho storage
capacitor voltage is brought to the output by low leakage
amplifier A2.
8.0 DEFINITIONS
Vs: The voltage at pin 5, e.g., the analog input voltage.
Vs: The voltage at pin 6, 9.9.. the logic control input sig-
V11: The voltage at pin 11, 6.9.. the output signal.
TA: The temperature of the ambient air.
Te. The temperature of the device case at the Center of
the bottom of the header.
Acquisition Time:
The time required for the output (pin 11) to settie within the
rated accuracy after a specified input change is applied to
the input (pin 5) with the logic input (pin 6) in the low state.
Aperture Time:
The time indeterminacy when switching from sample mode
to hold including the delay from the time the mode control
signal (pin 6) passes through its threshold (IA volts) to the
time the circuit actually enters the hold mode.
Output Offset Voltage:
The voltage at the output terminal (pin 11) with the analog
input (pin 5) at ground and logic input (pin 6) in the "sample"
mode. This will always be adjustable to zero using a 10k pot
between pins 3 and 4 with the wiper arm returned to V-.
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
LH0023CG - product/lh0023cg?HQS=T|-nu|I-nuII-dscataIog-df-pf-null-wwe
LH0023C - product/Ih0023c?HQS=T|-nulI-nu|I-dscataIog-df-pf-null-wwe
LH0023 - product/Ih0023?HQS=T|-nu|I-nu|I-dscatalog-df—pf-nuII-wwe
LH0043 - product/Ih0043?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
LH0043C - product/Ih00430?HQS=T|-nu||-nu|I-dscataIog-df-pf-null-wwe
LH0043CG - product/lhOO43cg?HQS=TI-nu|I-null-dscatalog-df-pf—nuII-wwe
LH0043G - productllh00439?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
LH0023G - product/Ih00239?HQS=T|—nul|—nulI-dscatalog-df—pf-nuII-wwe
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