IC Phoenix
 
Home ›  LL16 > LD39150-LD39150DT25-R-LD39150PT-R,Ultra low drop BiCMOS voltage regulator
LD39150-LD39150DT25-R-LD39150PT-R Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
LD39150STN/a24172avaiUltra low drop BiCMOS voltage regulator
LD39150DT25-R |LD39150DT25RSTN/a12015avaiUltra low drop BiCMOS voltage regulator
LD39150PT-R |LD39150PTRSTN/a34989avaiUltra low drop BiCMOS voltage regulator


LD39150PT-R ,Ultra low drop BiCMOS voltage regulatorLD39150Ultra low drop BiCMOS voltage regulatorDatasheet - production data• Temperature range: -40 t ..
LD3985G18R ,ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REGULATORS LOW ESR CAPACITORS COMPATIBLEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
LD3985G25R ,ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REGULATORS LOW ESR CAPACITORS COMPATIBLELD3985SERIESULTRA LOW DROP-LOW NOISE BICMOS VOLTAGEREGULATORS LOW ESR CAPACITORS COMPATIBLE

LD39150-LD39150DT25-R-LD39150PT-R
Ultra low drop BiCMOS voltage regulator
January 2014 DocID13159 Rev 4 1/26
LD39150

Ultra low drop BiCMOS voltage regulator
Datasheet - production data
Features
1.5 A guaranteed output current Ultra low dropout voltage (200 mV typ. @ 1.5 A
load, 40 mV typ. @ 300 mA load) Very low quiescent current (1 mA typ. @ 1.5 A
load, 1 μA max @ 25 °C in off mode) Logic-controlled electronic shutdown Current and thermal internal limit ± 1.5% output voltage tolerance @ 25 °C Fixed and ADJ output voltages: 1.8 V, 2.5 V,
3.3 V, ADJ Temperature range: -40 to 125 °C Fast dynamic response to line and load
changes Stable with ceramic capacitor Available in PPAK, DPAK and DFN6 (3x3 mm)
Applications
Microprocessor power supply DSPs power supply Post regulators for switching suppliers High efficiency linear regulator
Description

The LD39150 is a fast ultra low drop linear
regulator which operates from 2.5 V to 6 V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
Table 1. Device summary
Available on request.
Contents LD39150
2/26 DocID13159 Rev 4
Contents Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26LD39150 Diagram
1 Diagram

(*) Not present on ADJ versions.
Figure 1. Block diagram
Pin configuration LD39150
4/26 DocID13159 Rev 4 Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN)
Table 2. Pin description
DocID13159 Rev 4 5/26
LD39150 Typical application circuits Typical application circuits

(CI and CO capacitors must be placed as close as possible to the IC pins)
Note: Inhibit pin is not internally pulled down/up then it must not be left floating. Disable the device
when connected to GND or to a positive voltage less than 0.3 V.
Note: Set R2 as close as possible to 4.7 kΩ
Figure 3. LD39150 fixed version with inhibit
Figure 4. LD39150 adjustable version
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED