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LD39080PT-R
Ultra low drop BICMOS voltage regulator
March 2014 DocID13158 Rev 2 1/25
LD39080Ultra low drop BiCMOS voltage regulator
Datasheet - production data
Features 0.8 A guaranteed output current Ultra low-dropout voltage (150 mV typ. @ 0.8 A
load, 20 mV typ. @150 mA load) Very low quiescent current (1 mA typ. @ 0.8 A
load, 1 µA max.@ 25 °C in off mode) Logic-controlled electronic shutdown Current and thermal internal limit ±1.5% output voltage tolerance @ 25 °C Fixed and ADJ output voltages: 1.22 V, 1.8 V,
2.5 V, 3.3 V, ADJ Temperature range: -40 to 125 °C Fast dynamic response to line and load
changes Stable with ceramic capacitor Available in PPAK, DPAK and DFN8 (4x4 mm)
Applications Microprocessor power supply DSP power supply Post regulators for switching suppliers High efficiency linear regulator
DescriptionThe LD39080 is a fast, ultra low drop linear
regulator which operates from 2.5 V to 6 V input
supply.
A wide range of output options is available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessors and memory applications. The
device is developed on the BiCMOS process
which allows the low quiescent current operation
regardless of the output load current.
Table 1. Device summary Available on request.
Contents LD390802/25 DocID13158 Rev 2
Contents Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.1 External capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25LD39080 Diagram
1 Diagram
(*) Not present on ADJ version.
Figure 1. Block diagram
Pin configuration LD39080
4/25 DocID13158 Rev 2 Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN8)
Table 2. Pin description
DocID13158 Rev 2 5/25
LD39080 Typical application circuits Typical application circuits
(CI and CO capacitors have to be placed as closer as possible to the IC pin)
Note: The inhibit pin is not internally pulled down/up, therefore it must not be left floating. The
device has to be disabled when it is connected to GND or to a positive voltage less than
0.3V.
Note: Set R2 as closer as possible to 4.7 KΩ.
Figure 3. LD39080 fixed version with inhibit
Figure 4. LD39080 adjustable version
Typical application circuits LD39080
6/25 DocID13158 Rev 2
Figure 5. LD39080 DPAK
Figure 6. Timing diagram
DocID13158 Rev 2 7/25
LD39080 Maximum ratings
4 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All values are referred to GND.
Table 3. Absolute maximum ratings
Table 4. Thermal data With a PCB ground plane and heatsink.
Electrical characteristics LD39080
8/25 DocID13158 Rev 2
5 Electrical characteristics
TJ = 25 °C, VI = VO+1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = 2 V, unless otherwise
specified.
Table 5. Electrical characteristics
DocID13158 Rev 2 9/25
LD39080 Electrical characteristics Guaranteed by design.
Table 5. Electrical characteristics (continued)
Typical performance characteristics LD39080 Typical performance characteristics
TJ = 25 °C, VI = VO+1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = VI, unless otherwise
specified.
Figure 7. Output voltage vs temperature Figure 8. Dropout voltage vs temperature
Figure 9. Dropout voltage vs output current Figure 10. Quiescent current vs output current
LD39080 Typical performance characteristics
Figure 11. Quiescent current vs supply voltage Figure 12. Off-state current vs temperature
Figure 13. Quiescent current vs temperature Figure 14. Short-circuit current vs temperature
Figure 15. Output voltage vs input voltage Figure 16. Supply voltage rejection vs
temperature
Typical performance characteristics LD39080
Figure 17. Stability region vs CO and ESR
(at 100 kHz)
Figure 18. Stability region vs CO and low ESR
(at 100 kHz)
Figure 19. Load transient Figure 20. Line transient
DocID13158 Rev 2 13/25
LD39080 Application notes
7 Application notes
7.1 External capacitor
The LD39080 requires external capacitors to assure the stability. These capacitors have to
meet the requirements of minimum capacitance and equivalent series resistance (see
Figure 17 Figure 18). The input/output capacitors cannot be farther than 1 cm from the
relative pins and have to be connected directly to the input/output ground pins using traces
without any current flowing through them. Ceramic or electrolytic capacitors can be used.
7.2 Input capacitor
An input capacitor, whose minimum value is 1 µF, is required (the amount of capacitance
can be increased without any limit). This capacitor cannot be farther than 1 cm from the
input pin of the device and has to return to clean analog ground. Ceramic, tantalum or film
capacitors can be used.
7.3 Output capacitor
Ceramic or tantalum capacitors can be used but the output capacitor has to meet the
requirements of minimum capacitance and ESR (equivalent series resistance) value. A
minimum capacitance of 2.2 µF is a good choice to guarantee the stability of the regulator.
Anyway, other CO values can be used as per Figure 17 Figure 18, where the allowable ESR
range is seen as a function of the output capacitance. The curve represents the stability
region over the full temperature and IO range.
7.4 Thermal note
The output capacitor has to maintain its ESR in the stable region over the operating
temperature range to assure the stability. Besides, capacitor tolerance and temperature
variation have to be taken into account to assure the minimum amount of capacitance all
time.
7.5 Inhibit input operation
The inhibit pin can be used to turn off the regulator when pulled down, therefore by reducing
the current consumption below 1 µA. When the inhibit feature is not used, this pin has to be
tied to VI to turn on the regulator output all the time. To assure the right operation, the signal
source, used to drive the inhibit pin, has to swing above and below the specified thresholds
listed in Section 5: Electrical characteristics (VIH VIL). The inhibit pin must not be left floating
because it is not internally pulled down/up.
