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L99MD01XPTR
Standard Functions, Motor Drivers
September 2013 Doc ID 17242 Rev 6 1/54
L99MD01 Octal half-bridge driver with SPI control
for automotive application
Features 8 half bridges RON =typ. 0.9 Ω (HS), 0.64 Ω (LS)
@Tj =25°C Current limit of each output at min. 0.8 A Intrinsic DC/DC step up converter driving an
external MOSFET PWM mode option for all half bridges for hold
current Internal PWM generation Two current monitor outputs SPI interface for data communication Temperature warning All outputs overtemperature protected All outputs short circuit protected VCC supply voltage 3.0 to 5.3V Very low current consumption in standby mode
typ. 5 µA VS operating range compliant: 6 V – 18V
Applications Stepper motor driver and / or DC Intended to drive HVAC flaps
DescriptionThe L99MD01 is an octal half-bridge driver for
automotive applications.
The device is intended to drive DC and/or stepper
motors. Using the boost converter it’s possible to
drive 4 stepper motors simultaneously. Without
boost converter the system is able to run 3
stepper motors in sequential mode or 2 stepper
motors simultaneously. The octal half bridge
configuration allows also to drive 4 DC-motors
simultaneously and 7 DC-motors sequentially.
The integrated 24 bit standard Serial Peripheral
Interface (SPI) controls all outputs and provides
diagnostic information: normal operation, open-
load in on-state, overcurrent, temperature
warning and overtemperature.
Table 1. Device summary
Contents L99MD01
2/54 Doc ID 17242 Rev 6
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Power supply: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Power supply: VSA, VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 SMPS Switched Mode Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.8 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . 9
2.10 VS, VS2, VSA, VSB monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.11 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.12 Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.13 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.1 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2 SPI timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L99MD01 Contents
Doc ID 17242 Rev 6 3/54
5.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 Read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6 Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SPI control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1 ECOPACK® package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2 PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
List of tables L99MD01
4/54 Doc ID 17242 Rev 6
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. VS, VS2, VSA, VSB monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Current monitor dynamic characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. SMPS switched mode power supply gate driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14. Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 15. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 16. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 17. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 18. Command byte (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. Data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 20. Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 21. Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 24. ROM memory map (access with OC0 and OC1 set to ‘1’) . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 25. Control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 26. Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 27. Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 28. Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 29. Wobble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 30. Frequency deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 31. Control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 32. Ratio for CURR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 33. Ratio for CURR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 34. Control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 35. Control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 36. Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 37. Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 38. Status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 39. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 40. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
L99MD01 List of figures
Doc ID 17242 Rev 6 5/54
List of figures
Figure 1. Detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Pin connection (top view- not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Output turn-on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. SMPS timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. SPI frame structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Indication of the global error flag on SDO when CSN is low and SCK is stable. . . . . . . . . 26
Figure 10. Driving 4 bipolar stepper motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Driving 2 bipolar stepper motors simultaneously and 3 DC-motors sequentially . . . . . . . . 40
Figure 12. Driving 2 bipolar stepper motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. Driving 1 bipolar stepper motor and 2 DC-motors simultaneously . . . . . . . . . . . . . . . . . . . 42
Figure 14. Driving 3 bipolar stepper motors sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Driving 4 DC-motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Driving 3 DC-motors simultaneously and 2 DC-motors sequentially . . . . . . . . . . . . . . . . . 45
Figure 17. Driving 7 DC-motors sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18. Driving simultaneously 4 unipolar winded stepper motors in bipolar mode . . . . . . . . . . . . 46
Figure 19. Cost saving impact using L99MD01 as stepper motor driver inside HVAC systems . . . . . 47
Figure 20. PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21. PowerSSO-36 thermal impedance junction ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22. PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Block diagram L99MD01
1 Block diagram
Figure 1. Detailed block diagram
L99MD01 Detailed description
Doc ID 17242 Rev 6 7/54
2 Detailed description
2.1 Power supply: V CC
The supply voltage VCC (3.3 V / 5 V) supplies the whole device. In case of power-on (VCC
increases from undervoltage to VPOR OFF = 2.75 V, typical) the circuit is initialized by an
internally generated power-on-reset (POR). If the voltage VCC decreases under the
minimum threshold (VPOR ON = 2.55 V, typical), the outputs are switched off in 3-state (high
impedance). The status registers are cleared and the control registers are reset to their
default.
Figure 2. Power on reset
2.2 Power supply: V SA , V SB
Each VSA and VSB supplies 4 half bridges independently.
VSA Out 1 to Out 4
VSB Out 5 to Out 8
2.3 Standby mode
The standby mode of the L99MD01 is activated by EN pin to low. The inputs and outputs are
switched off. The status registers are cleared and the control registers are reset to their
default values.
In the standby mode the current consumption is typ. 5 µA.
2.4 PWM mode
The PWM Mode is intended to generate a hold current for stepper motors.
PWM frequency typ. 100 Hz.
Duty cycle (SPI 2bit): 15 %, 30 %, 45 % and 60 %.
Each half-bridge is independently addressable (SPI 8bit).
Detailed description L99MD01
8/54 Doc ID 17242 Rev 6
2.5 SMPS Switched Mode Power Supply
External MOSFET
Spread spectrum technique: Wobble oscillator, programmable by SPI (1.95 K / 3.9 K / 7.8 K / 15.6 KHz). Frequency modulation programmable by SPI (0 / 5 / 10 / 20%).
VS2 level concept: Microcontroller measuring pulse of SMPS frequency (dependent on internal oscillator
frequency).
Due to the Oscillator frequency of L99MD01 the µC can calculate the on/off counts to
program the SMPS frequency and duty cycle. Microcontroller sending by SPI SMPS 6-bit on counter value, microcontroller sending
by SPI SMPS 6-bit off counter value.
Basing on the on and off counter value the duty cycle and the SMPS frequency can be
programmed.
The VS2 voltage is strongly related to the duty cycle of SMPS.
2.6 Current monitor
The current monitor output sources a current image at the current monitor output which has
a programmable ratio (1/250, 1/500, 1/750, 1/1000) of the instantaneous current of the
selected half bridge (high-side or low-side). Via SPI it can be programmed which of the
outputs are multiplexed to the current monitor output.
The current monitor output allows a more precise analysis of the actual state of the load
rather than the detection of an open or overload condition. For example this can be used to
detect the motor state (starting, free-running, stalled).
2.7 Inductive loads
Each half bridge is built by an internally connected high-side and a low-side power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs.
2.8 Diagnostic functions
All diagnostic functions (over/open-load, temperature warning and thermal shutdown,
over/undervoltage) are internally filtered and the condition has to be valid for at least 32 µs
(open-load: typ. 2 ms, respectively) before the corresponding status bit in the status
registers is set. The filters are used to improve the noise immunity of the device. Open-load
and temperature warning function are intended for information purpose and not changes the
state of the output drivers. On contrary, the overload and thermal shutdown condition
disables the corresponding driver (overload) or all drivers (thermal shutdown), respectively.
The microcontroller has to clear the overcurrent status bit to reactivate the corresponding
driver.
L99MD01 Detailed description
Doc ID 17242 Rev 6 9/54
2.9 Temperature warning and thermal shutdown
If the junction temperature rises above TjTW ON a temperature warning flag is set and is
detectable via the SPI. If the junction temperature increases above the second threshold
TjSD ON, the thermal shutdown bit is set and power DMOS transistors of all output stages
are switched off to protect the device. Temperature warning flag and thermal shutdown bits
are latched. In order to reactivate the output stages, the junction temperature must
decrease below TjSD ON and the thermal shutdown bit has to be cleared by the
microcontroller.
2.10 VS , VS2 , V SA , V SB monitoring
VS undervoltage: Status bit is set. All outputs and SMPS are switched off.
The microcontroller needs to clear the status bits to reactivate the
drivers and SMPS.
VS overvoltage: Status bit is set. All outputs are switched off (default).
The microcontroller needs to clear the status bits to reactivate the
drivers Can be deactivated via SPI.
VSA undervoltage: Status bit is set. Out 1 to Out 8 are switched off.
The microcontroller needs to clear the status bits to reactivate the
drivers.
VSB undervoltage: Status bit is set. Out 1 to Out 8 are switched off.
The microcontroller needs to clear the status bits to reactivate the
drivers.
VS2 undervoltage: Status bit is set. Only if SPMS is active.
The microcontroller needs to clear the status bits to reactivate SMPS
VS2 overvoltage: Status bit is set. SMPS is switched off (default).
The microcontroller needs to clear the status bits to reactivate
SMPS. If the VS2 recovery bit is set, and the VS2 voltage falls below
the threshold, the SMPS goes in active mode and the status bit is
cleared.
Table 2. VS, VS2, VSA, VSB monitoring
Detailed description L99MD01
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2.11 Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for at least 2 ms (tdOL) the corresponding
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3 ms) can be used to test the open-load status without
changing the mechanical/electrical state of the loads.
2.12 Overload detection
In case of an overcurrent condition, a flag is set in the corresponding status register. If the
overcurrent signal is valid for at least tISC=32 µs, the overcurrent flag is set and the
corresponding switch is switched off to reduce the power dissipation and to protect the
integrated circuit. The microcontroller has to clear the status bit to reactivate the
corresponding driver.
2.13 Cross-current protection
The device is cross-current protected by an internal delay time. If one driver (LS or HS) is
turned-off the activation of the other driver of the same half bridge are automatically delayed
by the cross-current protection time. After the cross-current protection time is expired the
slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the
opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always
guaranteed that the previously activated driver is totally turned-off before the opposite driver
starts to conduct. If wrong SPI commands try to turn-on both driver (LS and HS)
simultaneously, the high-side and the low-side are (or stay) deactivated (3-state).
L99MD01 Pin definitions and functions
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Table 3. Pin description
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Figure 3. Pin connection (top view- not in scale)
Table 3. Pin description (continued)
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4 Electrical specifications
4.1 Absolute maximum ratings
Note: All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
4.2 ESD protection
Table 4. Absolute maximum ratings
Table 5. ESD protection HBM according to EIA/JESD22-A114-E. HBM with all unzapped pins grounded.
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4.3 Thermal data
4.4 Electrical characteristics
VS = 6 to 18 V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 °C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 6. Operating junction temperature
Table 7. Temperature warning and thermal shutdown
Table 8. Supply
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Table 8. Supply (continued)
Table 9. Overvoltage and undervoltage detection
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Table 10. Switches
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Figure 4. Output turn-on/off delays and slew rates
Table 10. Switches (continued)
Table 11. Current monitor output
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Table 11. Current monitor output (continued)
Table 12. Current monitor dynamic characteristics
Table 13. SMPS switched mode power supply gate driver output
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Figure 5. SMPS timings
4.4.1 SPI electrical characteristicsS = 6 to 18 V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 °C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 13. SMPS switched mode power supply gate driver output
Table 14. Oscillator
Table 15. DC characteristics
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Table 16. AC characteristics Guaranteed by design
Table 17. Dynamic characteristics(1)
Table 15. DC characteristics (continued)
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4.4.2 SPI timing parameter definition
Figure 6. SPI timing See Section 4.4.2: SPI timing parameter definition.
Table 17. Dynamic characteristics(1)
Functional description of the SPI L99MD01
22/54 Doc ID 17242 Rev 6 Functional description of the SPI
5.1 Signal description
5.1.1 Serial clock (SCK)
This input signal provides the timing of the serial interface. Data present at Serial Data Input
(SDI) is latched on the rising edge of Serial Clock (SCK). Data on Serial Data Out (SDO) is
shifted out at the falling edge of Serial Clock (see2H Figure7).
The SPI can be driven by a microcontroller with its SPI peripherals running in following
mode: CPOL=0 and CPHA=0 (see3H Figure 7).
5.1.2 Serial data input (SDI)
This input is used to transfer data serially into the device. It receives the data to be written.
Values are latched on the rising edge of Serial Clock (SCK).
Serial data output (SDO)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (SCK). SDO also reflects the status of the
(Bit 7 of the ) while CSN is low and no clock signal is present.
Chip select not (CSN)
When this input signal is High, the device is deselected and Serial Data Output (SDO) is
high impedance (3-state). Driving this input low enables the communication. The
communication must start and stop on a low level of Serial Clock (SCK).
Figure 7. Clock polarity and clock phase
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Figure 8. SPI frame structure
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5.2 SPI communication flow
5.2.1 General description
The proposed SPI communication is based on a standard SPI interface structure using CSN
(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)
signal lines. Maximum SPI frequency is 1 MHz.
At the beginning of each communication the master reads the register
(ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length
(24-bit for the L99MD01) and the availability of additional features.
Each communication frame consists of an instruction byte which is followed by 2 data bytes
(see 4HFigure 8).
The data returned on SDO within the same frame always starts with the
register. It provides general status information about the device. It is followed by 2bytes (i. e.
‘In-frame-response’, Figure 8).
For write cycles the register is followed by the previous content of the
addressed register.
For read cycles the register is followed by the content of the addressed
register.
5.2.2 Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (, , , Device Information>) and a 6 bit address.
Table 18. Command byte (8 bit)
Table 19. Data byte
Table 20. Operating code definition
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The and operations allow access to the RAM of the device,
i. e. write to control registers or read status information.
A operation addressed to a device specific status register reads
back and subsequently clear this status register. A operation with
address 3FH clears all status registers at a time and reads back the
register.
A operation addressed to an unused RAM address register is
identical to a operation (in case of unused RAM address, the second byte is
equal to 00H).
allows access to the ROM area which contains device related
information such as the product family, product name, silicon version and register width.
The is generated by an OR-combination of all failure events of the
device (i.e. bit 0 to bit 6 of the .
Table 21. Global status byte
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Figure 9. Indication of the global error flag on SDO when CSN is low and SCK is stable.
The bit 0 of the is a combination of an under/overvoltage warning and
a software warning: If the bit 5 is one (this is the standard after a correct SPI
communication), bit 0 is the logical OR of all under- and overvoltage status bits.
On the other hand, if there has been an SPI communication error or a chip reset (bit 5 is
zero), then bit 0 gives a better indication about the SPI error: An SDI stuck-at error leads to
a software reset and sets bit 0, while a clock pulse error only sets the communication error
bit, clears bit 5 and clears also bit 0. This leads to the following table of possible states
(assuming there is no under/overvoltage, overcurrent, openload or thermal error):
Writing to the selected data input register is only enabled if exactly one frame length is
transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are
counted within one frame, the complete frame is ignored and a SPI frame error is signaled in
the Global Status register. This safety function is implemented to avoid an unwanted
activation of output stages by a wrong communication frame.
Table 22. Reset
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For read operations, the bit in the is set, but
the register to be read is still transferred to the SDO pin. If the number of clock cycles is
smaller than the frame width, the data at SDO are truncated. If the number of clock cycles is
larger than the frame width, the data at SDO are filled with ‘0’ bits.
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
Note: As the frame width is 24 bits, an initial Read of using a 16 bits
communication sets the of the . A
subsequent correct length transaction is necessary to correct this bit.
5.3 Write operation
OC0, OC1: operating code (00 for ‘write’ mode)
The write operation starts with a command byte followed by 2 data bytes.
For write cycles the register is followed by the previous content of the
addressed register.
The RAM memory area consists of 16 bit registers. All unused RAM addresses are read as
‘0’.
Failures are indicated by activating the corresponding bit of the register.
Note: RAM address 00H is unused. An attempt to access this address is recognized as a
communication line error (‘Data-in stuck to GND’) and all internal registers are cleared
(software reset).
5.4 Read operation
OC0, OC1: operating code (01 for ‘read’ mode)
The read operation starts with a command byte followed by 2 data bytes. The content of the
data bytes is ‘don’t care’. The content of the addressed register is shifted out at SDO within
the same frame (‘in-frame response’).
The returned data byte represents the content of the register to be read.
Failures are indicated by activating the corresponding bit of the register.
5.5 Read and clear status operation
OC0, OC1: operating code (10 for ‘read and clear status’ mode)
The ‘Read and Clear Status’ operation starts with a command byte followed by 2 data bytes.
The content of the data bytes is ‘don’t care’. The content of the addressed status register is
transferred to SDO within the same frame (‘in-frame response’) and is subsequently
cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all Status registers
simultaneously.
