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L9826TRSTN/a6970avaiOCTAL LOW-SIDE DRIVER FOR RESISTIVE AND INDUCTIVE LOADS WITH SERIAL/PARALLEL INPUT CONTROL, OUTPUT PROTECTION AND DIAGNOSTIC


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L9826TR
OCTAL LOW-SIDE DRIVER FOR RESISTIVE AND INDUCTIVE LOADS WITH SERIAL/PARALLEL INPUT CONTROL, OUTPUT PROTECTION AND DIAGNOSTIC
1/12
L9826

April 2004 OUTPUTS CURRENT CAPABILITY UP TO
450mA RON = 2.2Ω at TJ = 25°C PARALLEL CONTROL INPUTS FOR
OUTPUTS 1 AND 2 SPI CONTROL FOR OUTPUTS 1 TO 8 RESET FUNCTION WITH RESET SIGNAL AT
NRES PIN OR UNDERVOLTAGE AT VCC INTRINSIC OUTPUT VOLTAGE CLAMPING
AT TYP. 50V OVERCURRENT SHUTDOWN AT OUTPUTS
3 TO 8 SHORT CIRCUIT CURRENT LIMITATION
AND SELECTIVE THERMAL SHUTDOWN AT
OUTPUTS 1 AND 2 OUTPUT STATUS DATA AVAILABLE ON THE SPI
Table 1. Order Codes
DESCRIPTION

The L9826 is a Octal Low-Side Driver Circuit, ded-
icated for automotive applications. Output voltage
clamping is provided for flyback current recircula-
tion, when inductive loads are driven. Chip Select
and Serial Peripheral Interface for outputs control
and diagnostic data transfer. Parallel Control in-
puts for two outputs.
Octal Low-Side Driver for resistive and inductive loads with
serial/parallel input control, output protection and diagnostic
BLOCK DIAGRAM
L9826
PIN FUNCTION
PIN CONNECTIONS (Top view)
3/12
L9826
ABSOLUTE MAXIMUM RATINGS

For voltages and currents applied externally to the device
Notes:1. All inputs are protected against ESD according to MIL 883C; tested with HBM at 2KV. It corresponds to a dissipated energy E ≤
0,2mJ. Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.
For currents determined within the device: When operating the device with short circuit at more than 2 outputs at the same time, damage due to electrical overstress may
occur.
THERMAL DATA
L9826
ELECTRICAL CHARACTERISTCS (4.5V ≤ VCC ≤ 5,5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified)
5/12
L9826
ELECTRICAL CHARACTERISTCS (continued)
L9826
FUNCTIONAL DESCRIPTION
General

The L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using
the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power
outputs features voltage clamping function for flyback current recirculation and are protected against short cir-
cuit to Vbat.
The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 , overcurrent and ther-
mal overload for outputs 1 and 2 in switch-on condition and 2) open load or short to GND in switch-off condition
for all outputs. The outputs status can be read out via the serial interface.
The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes
signal.
Output Stages Control

Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1
and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These
inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open.
The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1.
The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every
falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers.
ELECTRICAL CHARACTERISTCS (continued)
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