L9348 ,QUAD LOW SIDE DRIVERBlock DiagramVSVoltage RegulatorVS+VREG–=V VDD CCC 166kHz ENQ1V VDDSIN1ENFAIL ‡ 1OLSCPPGND1VREGTSD5 ..
L9349 ,QUAD INTELLIGENT POWER LOW SIDE SWITCHL9349QUAD INTELLIGENT POWER LOW SIDE SWITCH■ Quad power low side driver with 2 x 5A and 2 x 3A outp ..
L9349-LF ,four channel valve driverElectrical characteristics . . . . . . . 83.5 Diagnostic . 103.6 Circuit description ..
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L9351 ,HIGH SIDE DRIVERL9351HIGH SIDE DRIVERADVANCE DATA. LOW SATURATION VOLTAGE. TTL COMPATIBLE INPUT. WIDE SUPPLY VOLTAG ..
L9352B ,INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCHL9352BINTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH■ L9352B Quad low-side switch■ 2 x 5A designed ..
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LC7385 ,DTMF ReceiverPin Assignment16 15 14 13 12 11 1018 17912 3 45 67 8Pin FunctionsPe in No. NO amIn / Descriptio+1N ..
LC7385. ,DTMF ReceiverAbsolute Maximum Ratings at Ta=25– 2˚C, V =0VSSPl arameter Ss ymbo Cs ondition Rt ating UniMV aximu ..
LC7385M ,DTMF ReceiverFeatures 18 10• Single +5V power supply.• Decodes all 16 DTMF digits.• Built-in differential input ..
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L9348
QUAD LOW SIDE DRIVER
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L9348March 2002 SUPPLY VOLTAGE RANGE: 4.8 TO 18V OUTPUT VOLTAGE UP TO 40V OUTPUT VOLTAGE CLAMP DURING
RECIRCULATION OF INDUCTIVE LOADS OUTPUT CURRENT CAPABILITY 2 X 5A AND
2 X 3A LOW POWER DISSIPATION DURING
RECIRCULATION OF INDUCTIVE LOADS BY
INTEGRATED FREE WHEELING DIODES
(3A-DRIVERS ONLY) LOW ON-RESISTANCE 2 X 0.2Ω , 2 X 0.35Ω (TYP.) OUTPUT SHORT CIRCUIT CURRENT
PROTECTION REAL TIME DIAGNOSTIC FUNCTIONS OVERTEMPERATURE SHUTDOWN SIGNAL- AND POWER-GROUND-LOSS
SHUTDOWN 3.3V CMOS COMPATIBLE INPUTS AND
STATUS
DESCRIPTIONThe L9348 is a monolithic integrated quad low side
driver realized in advanced Multipower-BCD technol-
ogy. It is intended to drive inductive loads (relays,
electromagnetic valves) in automotive and industrial
applications.
QUAD LOW SIDE DRIVER
Figure 1. Block Diagram
L9348 2/13
Figure 2. Pin Connection
Table 1. Pin Description
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L9348
Table 2. Thermal Data
Table 3. Absolute Maximum RatingsThe absolute maximum ratings are the limiting values for this device. Damage may occur if this device is
subjected to conditions which are beyond these values.
Note: Human Body Model according to MIL883C. The device withstands ST1 class level.
Table 4. Operating Range.
L9348 4/13
Table 5. Electrical Characteristcs The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified
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L9348(1).See chapter 2.0 Timing Diagrams; resistive load condition; VS ≥ 9V
(2).This parameter will not be tested but assured by design
(3).Wafer-measurement
(4).Measured on P-SO36 devices
(5).Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
Table 5. Electrical Characteristcs The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified
L9348 6/13
1.0 FUNCTIONAL DESCRIPTION
1.1 OverviewThe four low-side switches are designed to drive inductive loads (relays, electromagnetic valves). For the 3A
switches (Q3/4) integrated free-wheeling diodes (D3/4) are available and can be used as recirculation path for
inductive loads. If either integrated nor external free-wheeling diodes are used the output voltage is clamped
internally during discharge of inductive loads. The switches are controlled by CMOS compatible inputs (IN1-4)
if the enable input is set to “high”. The status of each switch is monitored by the related status output (ST1-4).
1.2 Input CircuitsThe control and enable inputs are active high, featuring switching thresholds with hysteresis and pull-down cur-
rent sources. Not connected inputs are interpreted as “LOW”. If the enable input is set to “LOW” the outputs are
switched off independent of the control input state (IN1-4).
1.3 Switching StagesThe four power outputs consist of DMOS-power transistors. The output stages are protected against short circuit
to supply. Integrated output voltage clamp limits the output voltage in case of inductive load current flyback. In-
ternal pull down current sources are provided at the outputs to assure a defined conditon in OFF mode. They
will be disconnected in the disable mode (ENA=L). If the supply of the device gets lost but the loads and D3/4
are still supplied, an internal pull down resistor discharges the gate of the DMOS-power transistor to avoid
switch on due to capacitive coupling.
1.4 Status OutputsThe CMOS compatible status outputs indicate the state of the drivers (LOW-level indicates driver in OFF state,
HIGH-level indicates driver in ON state). If an error occurs the status output voltage changes like described in
chapter 1.6 Error Detection.
1.5 Protective CircuitsThe outputs are protected against current overload, overtemperature, and Power-GND-loss.
1.6 Error DetectionTwo main error types are distinguished in the diagnostic logic. If current overload, overtemperature, signal-
GND-loss or a power-GND-loss occurs, the status output signal is inverted, an internal register is set and the
driver is shutdown. The reset is done by switching off the corresponding control input or the enable input for at
least the time tD (defined to 1.5ms typ.). See also Figure 6 in chapter 2.0 Timing Diagrams.
All other errors (openload, active output voltage clamp) only cause an inverted status output signal but no shut-
down of the driver. An internal register is set too, but the reset is triggered automatically after the time tD, if the
error condition is no longer valid (see Figure 7 and Figure 8).
Excepting the detection of the active output voltage clamp all errors are digitally filtered before they are inter-
preted by the diagnostic logic.
The table 6 below shows the different failure conditions monitored in ON and OFF state:
Table 6.
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L9348
1.7 Diagnostic Output at Pulse Width Operation (PWM)If an input is operated with a pulsed signal (f ≥ 1/tD = 667 Hz typ.), the status does not follow each single pulse.
An internal delay tD of typ. 1.5ms leads to a continuous status output signal (see Figure 4 in chapter 2.0 Timing
Diagrams).
1.8 Diagnostic TableIn general the diagnostic follows the input signal in normal operating conditions. If any error is detected the di-
agnostic is inverted.
Table 7.
Table 6.
