L6996 ,DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUsABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L6997 ,STEP DOWN CONTROLLER FOR LOW VOLTAGES OPERATIONSAbsolute Maximum RatingsSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L6997S ,STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONSElectrical Characteristics (continued)(V = V = 3.3V; T = 0°C to 85°C unless otherwise specified)CC ..
L6997STR ,STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONSAbsolute Maximum RatingsSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L702B ,2A QUAD DARLINGTON SWITCHL7022A QUAD DARLINGTON SWITCHSUSTAINING VOLTAGE: 70 V2 A OUTPUTHIGH CURRENT GAINIDEAL FOR DRIVING S ..
L702N ,2A QUAD DARLINGTON SWITCHABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVCEX Collector-emitter Voltage (input open) 90 V ..
LC4128V-5T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-5T144C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-5TN128C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75T144I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75TN100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6996
DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUs
1/26
L6996July 2002 5 BIT DAC WITH AVAILABLE EXTERNAL
OUTPUT VOLTAGE. 0.6 TO 1.750V, DYNAMICALLY ADJUSTABLE
OUTPUT VOLTAGE RANGE. ±1% OUTPUT ACCURACY OVER LINE AND LOAD. ACTIVE DROOP. CONSTANT ON TIME TOPOLOGY ALLOWS
LOW DUTY CYCLE AND FAST LOAD
TRANSIENT. 90% EFFICIENCY FROM 12V TO 1.35V/8A. 1.750V TO 28V BATTERY INPUT RANGE. OPERATING FREQUENCY UP TO 1MHZ. INTEGRATED HIGH CURRENT DRIVERS. LATCHED OVP AND UVP PROTECTIONS.
OCP PROTECTION. 350μA TYP. QUIESCENT CURRENT. 7μA TYP. SHUTDOWN SUPPLY CURRENT. PGOOD AND OVP SIGNALS. ZERO-CURRENT DETECTION AND PULSE-
FREQUENCY MODE.
APPLICATIONS ADVANCED MOBILE CPUs SUPPLY WITH
DYNAMIC TRANSITIONS. NOTEBOOK/LAPTOP, CONCEPT PC CPUs
SUPPLY. DC/DC FROM BATTERY SUPPLY EQUIPMENTS.
DESCRIPTIONThe device is dc-dc controller specifically designed to
provide extremely high efficiency conversion for mo-
bile advanced microprocessors.
The "constant on-time" topology assures fast load
transient response. The embedded "voltage feedfor-
ward" provides nearly constant switching frequency
operation.
A precise 5-bit DAC allows select output voltage from
0.6V to 1V with 25mV steps and from 1V to 1.75V
with 50mV steps.
L6996 is capable of supporting CPUs VID combina-
tion changing during normal operation.
The active droop allows adjust both the output load-
line slope and the zero-load output voltage.
DINAMICALLY PROGRAMMABLE SYNCHRONOUS
STEP DOWN CONTROLLER FOR MOBILE CPUs
APPLICATION DIAGRAM
L6996 2/26
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
3/26
L6996
PIN FUNCTIONS
L6996 4/26
ELECTRICAL CHARACTERISTICS (VCC = VDR = 5V; Tamb = 0°C to 70°C unless otherwise specified)
5/26
L6996
Table 1. DAC Output Voltage
ELECTRICAL CHARACTERISTICS (continued)(VCC = VDR = 5V; Tamb = 0°C to 70°C unless otherwise specified)
L6996 6/26
Figure 1. Functional & Block Diagram
7/26
L6996
TYPICAL OPERATING CHARACTERISTICSThe test conditions refer to the component list the table 5. VIN = 20V VOUT = 1.8V FSW = 270kHz Tamb = 25°C
unless otherwise noted.
Figure 2. Dynamic Output Voltage Transition
1.55V -> 1.35V
Figure 3. Dynamic Output Voltage Transition
1.35V -> 1.55V
Figure 4. Load Transient 0-15A
Figure 5. Startup with Zero Load
Figure 6. Startup with 10A
L6996 8/26
Figure 7. Test Condition: Vin = 20V, V5v=5V, Fsw = 300kHz, Tamb = +25°C
Figure 8. Test Condition: Vout = 1.75V, Fsw = 300kHz, V5v = 5V, Tamb = +25°C
Figure 9. Test Condition: Vout = 1.75V, V5v = 5V, Tamb = +25°C
9/26
L6996
Figure 10. Typical Application with Active Voltage Droop
Figure 11. Typical Application without Active Voltage Droop
L6996 10/26
DEVICE DESCRIPTION
1.1 Constant On Time PWM Topology
Figure 12. Loop block schematic diagramThis device implements a Constant On Time control, where the Ton is the on time duration forced by a one-shot
circuit. The controller calculates the one-shot time directly proportional to the VCS- pin voltage and inversely to
the OSC pin voltage as in Eq 1:
Eq 1
where KOSC=180ns and τ is the internal propagation delay time (Typ. 40ns). The system imposes in steady
state a minimum on time corresponding to VOSC = 2V. In fact if the VOSC voltage increases above 2V the cor-
responding Ton will not decrease. Connecting OSC pin to a voltage partition from VIN to GND, it allows steady-
state switching frequency FSW independent of VIN. It results:
Eq 2
where
Eq 3
The above equations allow setting the frequency divider ratio aOSC once output voltage has been set; note that
such equations hold only if VOSC<2.A minimum off-time constrain of about 500nS is introduced in order to as-
sure the boot capacitor charge and to limit switching frequency after a load transient as well as to mask PWM
comparator output against switching noise and spikes.
The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if threeON K OSC CS- OSC
--------------- τ+=SW OUTIN
--------------- 1ON
----------- ⋅α OSC→ FSWK OSC⋅== OSC OSCIN
--------------- R22 R1+---- ----------------==
11/26
L6996conditions are met contemporarily: the PWM comparator output is low (i.e. the output voltage is below the ref-
erence voltage), the minimum off time is passed and the current limit comparator is not triggered (i.e. the induc-
tor current is under the current limit programmed value). The voltage on the OSC pin must range between 50mV
and 2V to ensure the system linearity.
1.2 Closing the loopThe loop is closed connecting the output voltage to the FB- pin. The FB- pin is linked internally to the comparator
negative pin and the positive pin is connected to the programmed voltage as in Figure 12. When the FB- goes
lower than FB+, the PWM comparator output goes high and sets the flip-flop output, turning on the high side
MOSFET. This condition is latched to avoid noise spike. After the on-time (calculated as described in the pre-
vious section) the system resets the flip-flop and then turns off the high side MOSFET and turns on the low side
MOSFET. Internally the device has more complex logic than a flip-flop to manage the transition in correct way.
For more details refers to the schematic Fig. 1. Because the system implements a valley loop control, the aver-
age output voltage is different from the programmed one as shown in figure 13.
Figure 13. Valley Regulation
Figure 14. Voltage positioning networkThe L6996 performs an externally adjustable active droop, achieving a 4m V/A load line slope using a 1.5mΩ
sense resistor without use an external amplifier. Focusing the attention on the control part of the system (Figure
14), it can be considered that the inductor current can revert (the PFM function is deal towards) and the current
L6996 12/26
has an average value equal to Io. The intention is to find the output average value called Vo. It is important to
remember that the loop is closed a valley of the ripple, in this conditions the inputs of PWM comparator must be
equal, so the VFB+ =VFB-. Suppose R4=0 and R3=open.
Considering this and watching the figure 14 it can be written two equations at the VFB+ and VFB- node:
Eq 4 Rsense · Io = Vc
Eq 5
Imposing Eq4=Eq5 it can be found the VOVALLEY value:
Eq 6 Vovalley = Vprog + Rs · (1 + R1/R2) · Io
Form Eq6 it can be noted the active drop effect due to R1, R2 resistors; it can be also noted the output average
value is different from the VPROG value, the error is due to the valley control, and it is equal to half of the ESR
voltage ripple.
To reduce the error of the average output voltage we can change the VPROG value using resistors. In fact con-
sidering the R3 resistor we can make a Thevenin equivalent:
Eq 7 Vprogeq = Vprog · R3/(R3 + R2)
Eq 8 Req = R3//R2
How it can be seen the VPROGEQ is less the VPROG and so we can reduce the average output error. Remember
that the R1, R2 and RSENSE are selected in base at the Voltage Positioning needs.
The R4 resistor can be used to set also a positive offset at zero load. Considering the PWM comparator inputs:
Eq 9 Vo = VFB+ + R4 · 5μA
Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hys-
teretic system the frequency can change with some parameters (input voltage, output current). In L6996 is im-
plemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate
operation with the input voltage variation. There are many factors affecting switching frequency accuracy in
steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver.
Others related to the external components as high side MOSFET gate charge and gate resistance, voltage
drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance.
During a positive load transient, (the output current increases), the converter switches at its maximum frequency
(the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output
current decreases), the device stops to switch (high side MOSFET remains off).
1.3 Transition from PWM to PFMTo achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM
mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turns-
on the low side MOSFET, until the current reaches the zero A value, when the zero-crossing comparator turns
off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground, through
the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps the low
side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow through the
low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in fact in PFM
mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when
the output voltage goes down a reference value. The device works in discontinuous mode at light load and in ovalley V prog– () R1⋅ R2+ ------------------------------------------------------------ Vc=
13/26
L6996continuous mode at high load. The transition from PFM to PWM occurs when load current is around half the
inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the inductor val-
ue is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the transient
response is. In PFM mode the frequency changes, with the output current changing, more than in PWM mode;
in fact if the output current increase, the output voltage decreases more quickly; so the successive turn-on ar-
rives before, increasing the switching frequency. The PFM waveforms may appear more noisy and asynchro-
nous than normal operation, but this is normal behaviour mainly due to the very low load. The NOSKIP feature
cannot be disabled.
1.4 SoftstartIf the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side
MOSFET off and the low side MOSFET on. After the SHDN pin is turned on the SS pin voltage begins to in-
crease and the system starts to switch. The softstart is realized by gradually increasing the current limit thresh-
old to avoid output overvoltage. The active soft start range (where the output current limit increase linearly)
starts from 0.6V to 1.5V. In this range an internal current source (5μA typ) charges the capacitor on the SS pin.
The reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage
and it saturates at 5μA (typ.) when SS voltage is close to 1.5V; so the maximum current limit is active. Output
protections like undervoltage is disabled until SS pin voltage reaches 1.5V, instead the overvoltage is always
present.
Once the SS pin voltage reaches the 1.5V value, the voltage on SS pin doesn't impact the system operation
anymore. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first
turn-on the power section and after the logic section (VCC pin).
Figure 15. Soft-start diagram
1.5 Current limitThe current limit comparator senses inductor current through the sense resistor when the low side MOSFET is
on and compares this value with the ILIM pin voltage. While the current is above the prefixed value, the control
inhibits the one-shot start.
To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current
depends on the inductor value, VIN e VOUT.
Eq 10 IOUTCL = IMAX_VALLEY + ΔIL / 2
