L6926 ,HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATORAbsolute Maximum RatingsSymbol Parameter Value UnitV Input voltage -0.3 to 6 V6V Output switching v ..
L6926D1013TR ,HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATORElectrical Characteristics (T = 25°C, V = 3.6V unless otherwise specified)j CCSymbol Parameter Test ..
L6926D1013TR ,HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATORFEATURES■ 2V TO 5.5V BATTERY INPUT RANGE■ HIGH EFFICIENCY: UP TO 95%■ INTERNAL SYNCHRONOUS SWITCHVF ..
L6928 ,High efficiency monolithic synchronous step down regulatorfeatures and protections . . . 105.1 DROPOUT operation 105.2 PGOOD (Power Good output) ..
L6928D013TR ,HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATORElectrical Characteristics (T = 25°C, V = 3.6V unless otherwise specified)j CCSymbol Parameter Test ..
L6928Q1TR ,High efficiency monolithic synchronous step down regulatorAbsolute maximum ratingsSymbol Parameter Value UnitV Input voltage -0.3 to 6 V6V Output switching v ..
LC4128B-75T128C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128B-75TN100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T128C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6926-L6926D1013TR
HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATOR
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L6926November 2004
FEATURES 2V TO 5.5V BATTERY INPUT RANGE HIGH EFFICIENCY: UP TO 95% INTERNAL SYNCHRONOUS SWITCH NO EXTERNAL SCHOTTKY REQUIRED EXTREMELY LOW QUIESCENT CURRENT 1µA MAX SHUTDOWN SUPPLY CURRENT 800mA MAX OUTPUT CURRENT ADJUSTABLE OUTPUT VOLTAGE FROM 0.6V LOW DROP-OUT OPERATION: UP TO100%
DUTY CYCLE SELECTABLE LOW NOISE/LOW
CONSUMPTION MODE AT LIGHT LOAD POWER GOOD SIGNAL ±1% OUTPUT VOLTAGE ACCURACY CURRENT-MODE CONTROL 600kHz SWITCHING FREQUENCY EXTERNALLY SYNCHRONIZABLE FROM
500kHz TO 1.4MHz OVP SHORT CIRCUIT PROTECTION
APPLICATIONS BATTERY-POWERED EQUIPMENTS PORTABLE INSTRUMENTS CELLULAR PHONES PDAs AND HAND HELD TERMINALS DSC GPS
DESCRIPTIONThe device is dc-dc monolithic regulator specifically
designed to provide extremely high efficiency.
L6926 supply voltage can be as low as 2V allowing
its use in single Li-ion cell supplied applications. Out-
put voltage can be selected by an external divider
down to 0.6V. Duty Cycle can saturate to 100% al-
lowing low drop-out operation. The device is based
on a 600kHz fixed-frequency, current mode-architec-
ture. Low Consumption Mode operation can be se-
lected at light load conditions, allowing switching
losses to be reduced. L6926 is externally synchroni-
zable with a clock which makes it useful in noise-sen-
sitive applications. Other features like Powergood,
Overvoltage protection, Shortcircuit protection and
Thermal Shutdown (150°C) are also present.
HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS
STEP DOWN REGULATOR
Figure 2. Application Test CircuitRev. 4
L6926
Table 2. Absolute Maximum Ratings
Figure 3. Pin Connection
Table 3. Thermal Data
Table 4. Pin Functions
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L6926
Table 5. Electrical Characteristics (Tj = 25°C, VCC = 3.6V unless otherwise specified)
L6926 (*) Guaranteed by design
OPERATION DESCRIPTIONThe main loop uses slope compensated PWM current mode architecture. Each cycle the high side MOSFET
is turned on, triggered by the oscillator, so that the current flowing through it (the same as the inductor current)
increases. When this current reaches the threshold (set by the output of the error amplifier E/A), the peak current
limit comparator PEAK_CL turns off the high side MOSFET and turns on the low side one until the next clock
cycle begins or the current flowing through it goes down to zero (ZERO CROSSING comparator). The peak in-
ductor current required to trigger PEAK_CL depends on the slope compensation signal and on the output of the
error amplifier.
In particular, the error amplifier output depends on the VFB pin voltage. When the output current increases, the
output capacitor is discharged and so the VFB pin decreases. This produces increase of the error amplifier out-
put, so allowing a higher value for the peak inductor current. For the same reason, when due to a load transient
the output current decreases, the error amplifier output goes low, so reducing the peak inductor current to meet
the new load requirements.
The slope compensation signal allows the loop stability also in high duty cycle conditions (see related section)
Figure 4. Device Block Diagram
4.1 Modes of OperationDepending on the SYNC pin value the device can operate in low consumption or low noise mode. If the SYNC
pin is high (higher than 1.3V) the low consumption mode is selected while the low noise mode is selected if the
SYNC pin is low (lower than 0.5V).
4.1.1 Low Consumption Mode
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L6926In this mode of operation, at light load, the device operates discontinuously based on the COMP pin voltage, in
order to keep the efficiency very high also in these conditions. While the device is not switching the load dis-
charges the output capacitor and the output voltage goes down. When the feedback voltage goes lower than
the internal reference, the COMP pin voltage increases and when an internal threshold is reached, the device
starts to switch. In these conditions the peak current limit is set approximately in the range of 200mA-400mA,
depending on the slope compensation (see related section).
Once the device starts to switch the output capacitor is recharged. The feedback pin increases and, when it
reaches a value slightly higher than the reference voltage, the output of the error amplifier goes down until a
clamp is activated. At this point, the device stops to switch. In this phase, most of the internal circuitries are off,
so reducing the device consumption down to a typical value of 25µA.
4.1.2 Low Noise ModeIf for noise reasons, the very low frequencies of the low consumption mode are undesirable, the low noise mode
can be selected. In low noise mode, the efficiency is a little bit lower compared with the low consumption mode
in very light load conditions but for medium-high load currents the efficiency values are very similar.
Basically, the device switches with its internal free running frequency of 600KHz. Obviously, in very light load
conditions, the device could skip some cycles in order to keep the output voltage in regulation.
4.1.3 SynchronizationThe device can also be synchronized with an external signal from 500KHz up to 1.4MHz.
In this case the low noise mode is automatically selected. The device will eventually skip some cycles in very
light load conditions.
The internal synchronization circuit is inhibited in shortcircuit and overvoltage conditions in order to keep the
protections effective (see relative sections).
4.2 Short Circuit ProtectionDuring the device operation, the inductor current increases during the high side turn on phase and decrease
during the high side turn off phase based on the following equations:
In strong overcurrent or shortcircuit conditions the VOUT can be very close to zero. In this case ∆ION increases
and ∆IOFF decreases. When the inductor peak current reaches the current limit, the high side mosfet turns off
and so the TON is reduced down to the minimum value (250ns typ.) in order to reduce as much as possible ∆ION.
Anyway, if VOUT is low enough it can be that the inductor peak current further increases because during the
TOFF the current decays very slowly.
Due to this reason a second protection that fixes the maximum inductor valley current has been introduced. This
protection doesn't allow the high side MOSFET to turn on if the current flowing through the inductor is higher
that a specified threshold (valley current limit). Basically the TOFF is increased as much as required to bring the
inductor current down to this threshold.
So, the maximum peak current in worst case conditions will be:
Where IPEAK is the valley current limit (1.4A typ.) and TON_MIN is the minimum TON of the high side MOSFET.
4.3 Slope CompensationONIN V OUT– ()------------------ -----------------TON⋅= OFF OUT()------- ------------T OFF⋅= PEAK I VALLEYIN---------T ON_MIN⋅+=
L6926 In current mode architectures, when the duty cycle of the application is higher than approximately 50%, a pulse-
by-pulse instability (the so called sub harmonic oscillation) can occur.
To allow loop stability also in these conditions a slope compensation is present. This is realized by reducing the
current flowing through the inductor necessary to trigger the COMP comparator (with a fixed value for the COMP
pin voltage).
With a given duty cycle higher than 50%, the stability problem is particularly present with an higher input voltage
(due to the increased current ripple across the inductor), so the slope compensation effect increases as the input
voltage increases.
From an application point of view, the final effect is that the peak current limit depends both on the duty cycle (if
higher than approximately 40%) and on the input voltage.
4.4 Loop StabilitySince the device is realized with a current mode architecture, the loop stability is usually not a big issue. For
most of the application a 220pF connected between the COMP pin and ground is enough to guarantee the sta-
bility. In case very low ESR capacitors are used for the output filter, such as multilayer ceramic capacitors, the
zero introduced by the capacitor itself can shift at very high frequency and the transient loop response could be
affected. Adding a series resistor to the 220pF capacitor can solve this problem.
The right value for the resistor (in the range of 50K) can be determined by checking the load transient response
of the device. Basically, the output voltage has to be checked at the scope after the load steps required by the
application. In case of stability problems, the output voltage could oscillates before to reach the regulated value
after a load step.
ADDITIONAL FEATURES AND PROTECTIONS
5.1 DROPOUT OperationThe Li-Ion battery voltage ranges from approximately 3V and 4.1V-4.2V (depending on the anode material). In
case the regulated output voltage is from 2.5V and 3.3V, it can be that, close to the end of the battery life, the
battery voltage goes down to the regulated one. In this case the device stops to switch, working at 100% of duty
cycle, so minimizing the dropout voltage and the device losses.
5.2 PGOOD (Power Good Output)A power good output signal is available. The VFB pin is internally connected to a comparator with a threshold
set at 90% of the of reference voltage (0.6V). Since the output voltage is connected to the VFB pin by a resistor
divider, when the output voltage goes lower than the regulated value, the VFB pin voltage goes lower than 90%
of the internal reference value. The internal comparator is triggered and the PGOOD pin is pulled down.
The pin is an open drain output and so, a pull up resistor should be connected to him.
If the feature is not required, the pin can be left floating.
5.3 ADJUSTABLE OUTPUT VOLTAGEThe output voltage can be adjusted by an external resistor divider from a minimum value of 0.6V up to the input
voltage. The output voltage value is given by:
5.4 OVP (Overvoltage Protection)The device has an internal overvoltage protection circuit to protect the load.
If the voltage at the feedback pin goes higher than an internal threshold set 10% (typ) higher than the reference
voltage, the low side power mosfet is turned on until the feedback voltage goes lower than the reference one.
During the overvoltage circuit intervention, the zero crossing comparator is disabled so that the device is also OUT 0.6 1 R21-------+ ⋅=
