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L6910STMN/a11avaiADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION
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L6910-L6910TR
ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION
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L6910

April 2002
FEATURE
OPERATING SUPPLY VOLTAGE FROM 5V
TO 12V BUSES UP TO 1.3A GATE CURRENT CAPABILITY ADJUSTABLE OUTPUT VOLTAGE N-INVERTING E/A INPUT AVAILABLE 0.9V ±1.5% VOLTAGE REFERENCE VOLTAGE MODE PWM CONTROL VERY FAST LOAD TRANSIENT RESPONSE 0% TO 100% DUTY CYCLE POWER GOOD OUTPUT OVERVOLTAGE PROTECTION HICCUP OVERCURRENT PROTECTION 200kHz INTERNAL OSCILLATOR OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50kHz TO 1MHz SOFT START AND INHIBIT PACKAGE: SO-16
APPLICATIONS
SUPPLY FOR MEMORIES AND TERMI-
NATIONS COMPUTER ADD-ON CARDS LOW VOLTAGE DISTRIBUTED DC-DC MAG-AMP REPLACEMENT
DESCRIPTION

The device is a pwm controller for high performance
dc-dc conversion from 3.3V, 5V and 12V buses.
The output voltage is adjustable down to 0.9V; higher
voltages can be obtained with an external voltage di-
vider.
High peak current gate drivers provide for fast switch-
ing to the external power section, and the output
current can be in excess of 20A.
The device assures protections against load overcur-
rent and overvoltage. An internal crowbar is also pro-
vided turning on the low side mosfet as long as the
over-voltage is detected. In case of over-current de-
tection, the soft start capacitor is discharged and the
system works in HICCUP mode.
ADJUSTABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
BLOCK DIAGRAM
L6910
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ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION (Top view)
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PIN FUNCTION
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ELECTRICAL CHARACTERISTICS (Vcc = 12V, TJ =25°C unless otherwise specified)
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Device Description

The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and
protection for a high performance step-down DC-DC converter. It is designed to drive N Channel Mosfets in a
synchronous-rectified buck topology. The output voltage of the converter can be precisely regulated down to
900mV with a maximum tolerance of ±1.5% when the internal reference is used (simply connecting together
EAREF and VREF pins). The device allows also using an external reference (0.9V to 3V) for the regulation. The
device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that
is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V/μs slew
rate that permits to realize high converter bandwidth for fast transient performance. The PWM duty cycle can
range from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode. The de-
vice monitors the current by using the rDS(ON) of the upper MOSFET(s) that eliminates the need for a current
sensing resistor. The device is available in SO16 narrow package.
Oscillator

The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 50μA (Fsw = 200KHz) and may be varied using an external resistor (RT) connected between
OSC pin and GND or VCC. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is var-
ied proportionally to the current sunk (forced) from (into) the pin.
In particular connecting RT vs. GND the frequency is increased (current is sunk from the pin), according to the
following relationship:
Connecting RT to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according
to the following relationships:
VCC = 12V
VCC = 5V
Switching frequency variation vs. RT are repeated in Fig. 1.
Note that forcing a 50μA current into this pin, the device stops switching because no current is delivered to the
oscillator. OSC,RT 200KHz 4.94 106⋅T KΩ()-- -----------------------+= OSC,RT 200KHz 4.306 107⋅T KΩ()------- ----------------------–= OSC,RT 200KHz 15 106⋅T KΩ()------- --------------–=
Figure 1. Reference

A precise ±1.5% 0.9V reference is available. This ref-
erence must be filtered with 1nF ceramic capacitor to
avoid instability in the internal linear regulator. It is
able to deliver up to 100μA and may be used as ref-
erence for the device regulation and also for other de-
vices. If forced under 70% of its nominal value, the
device enters in Hiccup mode until this condition is
removed.
Through the EAREF pin the reference for the regula-
tion is taken. This pin directly connects the non-in-
verting input of the error amplifier. An external
reference (or the internal 0.9V ±1.5%) may be used.
The input for this pin can range from 0.9V to 3V. It
has an internal pull-down (300kΩ resistor) that forces
the device shutdown if no reference is connected (pin
floating). However the device is shut down if the volt-
age on the EAREF pin is lower than 650mV (typ).
L6910
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Soft Start

At start-up a ramp is generated charging the external capacitor CSS with an internal current generator. The initial
value for this current is of 35μA and speeds-up the charge of the capacitor up to 0.5V. After that it becames
10μA until the final charge value of approximatively 4V.
When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to dis-
charge the output capacitor. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper
MOS begins to switch and the output voltage starts to increase.
No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.
If VCC and OCSET pins are not above their own turn-on thresholds and VEAREF is not above 650mV, the Soft-
Start will not take place, and the relative pin is internally shorted to GND. During normal operation, if any under-
voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor
is rapidly discharged.
Figure 2. Soft Start (with Reference Present)
Driver Section

The driver capability on the high and low side drivers allows using different types of power MOS (also multiple
MOS to reduce the RDSON), maintaining fast switching transition.
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the
high side turn-off.
The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 3.3nF capac-
itive load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ VCC = 12V and 500mA @ VCC = 5V, and the sink peak
current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V.
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ Vboot-
Vphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
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L6910
Figure 3. High Side driver peak current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)
Figure 4. Low Side driver peak current. VCC = 12V (right) VCC = 5V (left)
Monitoring and Protections

The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the
powergood output is forced low.
The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.)
greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the
over-voltage is detected.
Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the
RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the
upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship:
Where the typical value of IOCS is 200μA. To calculate the ROCS value it must be considered the maximum
RdsON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of
overcurrent protection this relationship must be satisfied:P OCSI OCS⋅ dsON
---------------------------------=
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Where ΔI is the inductance ripple current and IOUTMAX is the maximum output current.
In case of over current detectionthe soft start capacitor is discharged with constant current (10μA typ.) and when
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-
ways active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is dis-
charged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,
as shown in figure 5. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on. PI OUTMAX IΔ-----+≥ I PEAK=
Figure 5. Hiccup Mode Figure 6. Inductor ripple current vs. Vout
CH1 = SS; CH4 = Inductor current
Inductor design

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current ΔIL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 6 shows
the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-
rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
imate response time for ΔI load transient in case of enough fast compensation network response:
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available. VIN V OUT–sw ILΔ⋅ ------------------------------V OUTIN
---------------⋅= applicationΔ⋅IN V OUT–- ---------------- ------------- t removalΔ⋅ OUT
---------------==
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L6910
Output Capacitor

The output capacitor is a basic component for the fast response of the power supply. In fact, during load tran-
sient, for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output
voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
during load transient and the lower is the output voltage static ripple.
Input Capacitor

The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are:
Compensation network design

The control loop is a voltage mode (figure 7). The output voltage is regulated to the input Reference voltage
level (EAREF). The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide
a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. This wave is filtered by the
output filter. The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function
has a double pole at frequency FLC depending on the L-Cout resonance and a zero at FESR depending on the
output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak
oscillator voltage ΔVOSC. OUTΔ I OUTΔ ESR⋅= OUTΔ I OUTΔ L⋅ OUT V INMIND MAX V OUT–⋅ ()⋅⋅---------------------------- --------------- --------------- --------------- --------------------= rms I OUT= ESRI rms⋅=
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Figure 7. Compensation Network

The compensation network consists in the internal error amplifier and the impedance networks ZIN (R3, R4 and
C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with
the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain
in DC conditions to minimize the load regulation.
A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include
worst-case component variations when determining phase margin.
To locate poles and zeroes of the compensation networks, the following suggestions may be used:
Modulator singularity frequencies:
Compensation network singularity frequency: Put the gain R5/R3 in order to obtain the desired converter bandwidth;
–Place ωZ1 before the output filter resonance ωLC;
–Place ωZ2 at the output filter resonance ωLC;
–Place ωP1 at the output capacitor ESR zero ωESR;
–Place ωP2 at one half of the switching frequency; Check the loop gain considering the error amplifier open loop gain.LC 1
------ ω ESR 1
ESRC OUT⋅ ---------------------------------==P1 1 C18 C19⋅
C18 C19+--------------- --------------⋅
-------- --------------- ----------------------- - ωP2 1 C20⋅----- -------------------==Z1 1 C19⋅ ----------------------- - ωZ2 1 R4+ () C20⋅------ --------------- ----------------------==
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