L6706 ,VR11.1 single phase controller with integrated driverElectrical characteristics . . . . . . 114 Voltage identifications . . . . . . 135 Device ..
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L6706
VR11.1 single phase controller with integrated driver
January 2010 Doc ID 15698 Rev 2 1/47
L6706VR11.1 single phase controller with integrated driver
Features 8-bit programmable output up to 1.60000 V -
Intel® VR11.1 DAC High current embedded driver High output voltage accuracy Programmable droop function Imon output Load transient boost LTB Technology™ to
minimize the number of output capacitors Full differential current sense across inductor Differential remote voltage sensing Adjustable voltage offset LSLess startup to manage pre-biased output Feedback disconnection protection Preliminary overvoltage protection Programmable overcurrent protection Programmable overvoltage protection Adjustable switching frequency SSEND and OUTEN signal VFQFPN-40 6x6 mm package with exp. pad
Applications VTT and VAXG rails CPU power supply High density DC/DC converters
DescriptionThe device implements a single phase step-down
controller with integrated high current driver in a
compact 6x6 mm body package with exposed
pad.
The device embeds VR11.x DACs: the output
voltage ranges up to 1.60000 V managing D-VID
with high output voltage accuracy over line and
temperature variations.
Imon capability guarantee full compatibility with
VR11.1 enabling additional power saving
technique.
Programmable droop function allows to supply all
the latest Intel CPU rails.
Load transient boost L TB Technology™ reduces
system cost by providing the fastest response to
load transition.
The controller assures fast protection against load
over current and under / over voltage. Feedback
disconnection prevents from damaging the load in
case of disconnections in the system board.
In case of over-current, the system works in
constant current mode until UVP.
Table 1. Device summary
Contents L67062/47 Doc ID 15698 Rev 2
Contents Principle application circuit and block diagram . . . . . . . . . . . . . . . . . . . 41.1 Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 62.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DAC and current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208.1 Offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.2 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Droop thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output current monitoring (IMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Load transient boost technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
L6706 Contents
Doc ID 15698 Rev 2 3/47
14.1 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 34
15.1 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15.2 Preliminary overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15.3 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.5 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
20.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
20.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 43
20.3 Embedding L6706 - Based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Principle application circuit and block diagram L6706
4/47 Doc ID 15698 Rev 2 Principle application circuit and block diagram
1.1 Principle application circuit
Figure 1. Principle application circuit (a) Refer to the application note for the reference schematic.
L6706 Principle application circuit and block diagram
Doc ID 15698 Rev 2 5/47
1.2 Block diagram
Figure 2. Block diagram
Pins description and connection diagrams L6706
6/47 Doc ID 15698 Rev 2 Pins description and connection diagrams
Figure 3. Pins connection (top view)
2.1 Pin description
Table 2. Pin description
L6706 Pins description and connection diagrams
Doc ID 15698 Rev 2 7/47
Table 2. Pin description (continued)
Pins description and connection diagrams L6706
8/47 Doc ID 15698 Rev 2
Table 2. Pin description (continued)
L6706 Pins description and connection diagrams
Doc ID 15698 Rev 2 9/47
2.2 Thermal data
Table 3. Thermal data
Table 2. Pin description (continued)
Electrical specifications L6706
10/47 Doc ID 15698 Rev 2
3 Electrical specifications
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
L6706 Electrical specifications
Doc ID 15698 Rev 2 11/47
3.2 Electrical characteristics
VCC = 12 V ± 15%, TJ = 0 °C to 70 °C unless otherwise specified
Table 5. Electrical characteristics
Electrical specifications L6706
12/47 Doc ID 15698 Rev 2
Table 5. Electrical characteristics (continued)
L6706 Voltage identifications
Doc ID 15698 Rev 2 13/47
4 Voltage identifications
Table 6. Voltage Identification (VID) mapping Intel VR11.x
Table 7. Voltage Identification (VID) Intel VR11.x(1)
Voltage identifications L6706
14/47 Doc ID 15698 Rev 2
Table 7. Voltage Identification (VID) Intel VR11.x(1) (continued)
L6706 Voltage identifications
Doc ID 15698 Rev 2 15/47
According to INTEL specs, the device automatically regulates output voltage 19 mV lower to avoid any
external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage
is than what extracted from the table lowered by 19 mV.
Table 7. Voltage Identification (VID) Intel VR11.x(1) (continued)
Device description L6706
16/47 Doc ID 15698 Rev 2
5 Device description
L6706 is single phase PWM controller with embedded high current drivers providing
complete control logic and protections for a high performance step-down DC-DC voltage
regulator optimized for advanced microprocessor power supply.
L6706 is a dual-edge asynchronous PWM controller featuring load transient boost LTB echnology™: the device turns on the phase as soon as a load transient is detected
allowing to minimize system cost by providing the fastest response to load transition. Load
transition is detected (through LTB pin) measuring the derivate dV/dt of the output voltage
and the dV/dt can be easily programmed extending the system design flexibility. Moreover,
load transient boost (LTB) Technology™ gain can be easily modified in order to keep under
control the output voltage ring back.
LTB T echnology™ can be disabled and in this condition the device works as a dual-edge
asynchronous PWM.
L6706 permits easy system design by allowing current reading across inductor in fully
differential mode. Also a sense resistor in series to the inductor can be considered to
improve reading precision.
The controller allows compatibility with both Intel VR11.0 and VR11.1 processors
specifications, also performing D-VID transitions accordingly.
The device is VR11.1 compatible implementing IMON signal.
Low-side-less startup allows soft-start over pre-biased output avoiding dangerous current
return through the main inductor as well as negative spike at the load side.
L6706 provides a programmable over-voltage protection to protect the load from dangerous
over stress, latching immediately by turning ON the lower driver and driving high the
OSC/FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect
load from dangerous OVP when VCC is not above the UVLO threshold or OUTEN is low.
The overcurrent protection is externally adjustable through a single resistor. The device
keeps constant the peak of the inductor current ripple working in constant current mode until
the latched UVP.
A compact 6 x 6 mm body VFQFPN-40 package with exposed thermal pad allows
dissipating the power to drive the external MOSFET through the system board.
L6706 DAC and current reading
Doc ID 15698 Rev 2 17/47
DAC and current reading
L6706 embeds VRD11.x DAC (see Table 7) that allows to regulate the output voltage with a
tolerance of ±0.5% recovering from offsets and manufacturing variations.
The device automatically introduces a -19 mV (both VRD11.x) offset to the regulated
voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy
and, as a consequence, the calculated system TOB.
Output voltage is programmed through the VID pins: they are inputs of an internal DAC that
is realized by means of a series of resistors providing a partition of the internal voltage
reference. The VID code drives a multiplexer that selects a voltage on a precise point of the
divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the
set-point of the error amplifier, VREF).
L6706 embeds a flexible, fully-differential current sense circuitry that is able to read across
inductor parasitic resistance or across a sense resistor placed in series to the inductor
element. The fully-differential current reading rejects noise and allows placing sensing
element in different locations without affecting the measurement's accuracy.
Reading current across the inductor DCR, the current flowing trough phase is read using the
voltage drop across the output inductor or across a sense resistor in its series and internally
converted into a current. The trans-conductance ratio is issued by the external resistor Rg
placed outside the chip between CS- pin toward the reading points.
The current sense circuit always tracks the current information, no bias current is sourced
from the CS+ pin: this pin is used as a reference keeping the CS- pin to this voltage. To
correctly reproduce the inductor current an R-C filtering network must be introduced in
parallel to the sensing element.
The current that flows from the CS- pin is then given by the following equation (see
Figure 4):
Where IPHASE is the current carried by the relative phase.
Figure 4. Current reading connections
Considering now to match the time constant between the inductor and the R-C filter applied
(Time constant mismatches cause the introduction of poles into the current reading network CS- DCR------------- 1s LDCR()⁄⋅+RC⋅⋅+ -------------------------------------------I⋅ PHASE⋅=
DAC and current reading L6706
18/47 Doc ID 15698 Rev 2
causing instability. In addition, it is also important for the load transient response and to let
the system show resistive equivalent output impedance), it results:
Where I INFO is the current information reproduced internally.
The Rg trans-conductance resistor has to be selected using the following formula, in order
to guarantee the correct functionality of internal current reading circuitry:
Where IOUT MAX is the maximum output current, DCR MAX the maximum inductor DCR.
DCR------------- RC ICS- DCR-------------I PHASE⋅=⇒⋅ I INFO I INFO DCR-------------I PHASE⋅=⇒== DCR MAX
20μA------------------------I OUT MAX⋅=
L6706 Differential remote voltage sensing
Doc ID 15698 Rev 2 19/47
Differential remote voltage sensing
The output voltage is sensed in fully-differential mode between the FB and FBG pin.
The FB pin has to be connected through a resistor to the regulation point while the FBG pin
has to be connected directly to the remote sense ground point.
In this way, the output voltage programmed is regulated between the remote sense point
compensating motherboard or connector losses.
Keeping the FB and FBG traces parallel and guarded by a power plane results in common
mode coupling for any picked-up noise.
Figure 5. Differential remote voltage sensing connections
Voltage positioning L6706
20/47 Doc ID 15698 Rev 2
8 Voltage positioning
Output voltage positioning is performed by selecting the internal reference value through
VID pins and by programming the droop function and offset to the reference (see Figure6
on page 20). The currents sourced/sunk from FB pin cause the output voltage to vary
according to the external RFB.
The output voltage is then driven by the following relationship:
where:
OFFSET function can be disabled shorting to SGND the OFFSET pin.
Figure 6.
8.1 Offset (optional)
The OFFSET pin allows programming a positive offset (VOS) for the output voltage by
connecting a resistor ROFFSET vs. SGND as shown in Figure 7; this offset has to be
considered in addition to the one already introduced during the production stage (VPROG =
VID-19 mV).
OFFSET function can be disabled shorting to SGND the OFFSET pin.
The OFFSET pin is internally fixed at 1.240 V (Table 5) a current is programmed by
connecting the resistor ROFFSET between the pin and SGND: this current is mirrored and
then properly sunk from the FB pin as shown in Figure 7. Output voltage is then
programmed as follow: OUTI OUT() V PROG RFBI DROOPI OUT()I OFFSET– []⋅–= PROG VID 19mV–= OFFSET 1.240V OFFSET
------------------------=
L6706 Voltage positioning
Doc ID 15698 Rev 2 21/47
where:
Offset resistor can be designed by considering the following relationship (RFB is fixed by the
Droop effect):
Offset automatically given by the DAC selection differs from the offset implemented through
the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5% error over
load and line variations
Figure 7. Voltage positioning with positive offset
8.2 Droop function
This method “recovers” part of the drop due to the output capacitor ESR in the load
transient, introducing a dependence of the output voltage on the load current: a static error
proportional to the output current causes the output voltage to vary according to the sensed
current.
As shown in Figure 6, the ESR drop is present in any case, but using the droop function the
total deviation of the output voltage is minimized. Moreover, more and more high-
performance CPUs require precise load-line regulation to perform in the proper way.
DROOP function is not then required only to optimize the output filter, but also becomes a
requirement of the load.
The device forces a current I DROOP , proportional to the read current, into the feedback RFB
resistor implementing the load regulation dependence. Since I DROOP depends on the
current information, the output characteristic vs. load current is then given by (neglecting the
OFFSET voltage term):
Where DCR is the inductor parasitic resistance (or sense resistor when used) and I OUT is
the output current of the system. The whole power supply can be then represented by a OUTI OUT() V PROG RFB DROOPI OUT() 1.240V OFFSET
------------------------–⋅–=OS RFB 1.240V OFFSET
------------------------⋅= OFFSET RFB 1.240VOS
----- --------------⋅= OUT V PROG RFBI DROOP⋅– V REF RFB DCR-------------I OUT⋅⋅– V PROG R DROOPI OUT⋅–== =
Voltage positioning L6706
22/47 Doc ID 15698 Rev 2
“real” voltage generator with an equivalent output resistance RDROOP and a voltage value of
VPROG. RFB resistor can be also designed according to the RDROOP specifications as follow:FB R DROOP Rg
DCR-------------⋅=
L6706 Droop thermal compensation
Doc ID 15698 Rev 2 23/47
Droop thermal compensation
Current sense element (DCR inductor) has a non-negligible temperature variation. As a
consequence, the sensed current is subjected to a measurement error that causes the
regulated output voltage to vary accordingly (when droop function is implemented). o recover from this temperature related error, NTC resistor can be added into feedback
compensation network, as shown in Figure8.
The output voltage is then driven by the following relationship (neglecting the OFFSET
voltage term):
where RFB is the equivalent feedback resistor and it depends on the temperature through
NTC resistor.
Considering the relationships between IDROOP and the IOUT, the output voltage results:
where T is the temperature.
If the inductor temperature increases the DCR inductor increases and NTC resistor
decreases. As a consequence the equivalent RFB resistor decreases keeping constant the
output voltage respect to temperature variation.
NTC resistor must be placed as close as possible to the sense element (phase inductor).
Figure 8. NTC connections for DC load line thermal compensation OUT V PROG RFBI DROOP⋅ ()–= OUT TI OUT(, )[] V PROG RFBT[] DCRT[]------ ----------------I OUT⋅⋅ ⎝⎠⎛⎞–=
Output current monitoring (IMON) L6706
24/47 Doc ID 15698 Rev 2
10 Output current monitoring (IMON)
The device sources from IMON pin a current proportional to the load current (the sourced
current is a copy of droop current).
Connect IMON pin through a RIMON resistor to remote ground (GND Core) to implement a
load indicator, as shown in Figure9.
As INTEL VR11.1 specification required, on the IMON voltage as to be added a small
positive offset to avoid under-estimation of the output load (due to elements accuracy).
The voltage across IMON pin is given by the following formula:
where:
The IMON pin voltage is clamped to 1.100 V max to preserve the CPU from excessive
voltages as INTEL VR11.1 specification required.
Figure 9. Output monitoring connection (left) and thermal compensation (right)
Current sense element (DCR inductor) has a non-negligible temperature variation. As a
consequence, the sensed current is subjected to a measurement error that causes the
monitoring voltage to vary accordingly. o recover from this temperature related error, NTC resistor can be added into monitoring
network, as shown in Figure9.
The monitoring voltage is then driven by the following relationship (neglecting the offset term
for simplicity):
where now the RIMON is the equivalent monitoring resistor and it depends on the
temperature through NTC resistor.
Considering the relationships between IDROOP and the IOUT, the voltage results: MONITORING IMONROS⋅ IMON ROS+--------------------- --------------I DROOP⋅ V REF IMON IMON ROS+--------- --------------------------⋅+= MONITORING IMONROS⋅ IMON ROS+-----------------------------------I DROOP⋅ R IMONROS⋅ IMON ROS+------------------ ----------------- DCR-------------I OUT⋅⋅==
