L6599N ,High-voltage resonant controllerBlock diagramVcc H.V. 12 16 VBOOTDISABLE DIS 8+DIS15 HVGS QUV - HVG 1.85V C17V BOOT DETECTIONR D ..
L6599N ,High-voltage resonant controllerFeatures■ 50 % duty cycle, variable frequency control of resonant half-bridge■ High-accuracy oscill ..
L6599N ,High-voltage resonant controllerApplicationsvoltage rise■ 600 V-rail compatible high-side gate driver with ■ LCD and PDP TVintegrat ..
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LC4064B-25T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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LC4064V-10T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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L6599D-L6599DTR-L6599N
High-voltage resonant controller
Not for new designFebruary 2009 Rev 3 1/36
L6599 High-voltage resonant controller
Features 50 % duty cycle, variable frequency control of
resonant half-bridge High-accuracy oscillator Up to 500 kHz operating frequency Two-level OCP: frequency-shift and latched
shutdown Interface with PFC controller Latched disable input Burst-mode operation at light load Input for power-ON/OFF sequencing or
brownout protection Non-linear soft-start for monotonic output
voltage rise 600 V-rail compatible high-side gate driver with
integrated bootstrap diode and high dV/dt
immunity -300/800 mA high-side and low-side gate
drivers with UVLO pull-down DIP-16, SO-16N packages
Applications LCD and PDP TV Desktop PC, entry-level server Telecom SMPS AC-DC adapter, open frame SMPS
Table 1. Order code
Figure 1. Block diagram
Contents L65992/36
Contents Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.5 Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.7 Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.8 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
L6599 Device description 3/36
1 Device description
The L6599 is a double-ended controller specific for the resonant half-bridge topology. It
provides 50 % complementary duty cycle: the high-side switch and the low-side switch are
driven ON\OFF 180° out-of-phase for exactly the same time.
Output voltage regulation is obtained by modulating the operating frequency. A fixed dead-
time inserted between the turn-OFF of one switch and the turn-ON of the other one
guarantees soft-switching and enables high-frequency operation. o drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage
floating structure able to withstand more than 600 V with a synchronous-driven high-voltage
DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the designer to set the operating frequency range of the converter by means
of an externally programmable oscillator.
At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a
programmable maximum value and progressively decays until it reaches the steady-state
value determined by the control loop. This frequency shift is non linear to minimize output
voltage overshoots; its duration is programmable as well.
The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep
converter's input consumption to a minimum.
IC's functions include a not-latched active-low disable input with current hysteresis useful for
power sequencing or for brownout protection, a current sense input for OCP with frequency
shift and delayed shutdown with automatic restart.
A higher level OCP latches off the IC if the first-level protection is not sufficient to control the
primary current. Their combination offers complete protection against overload and short
circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or
OVP.
An interface with the PFC controller is provided that enables to switch off the pre-regulator
during fault conditions, such as OCP shutdown and DIS high, or during burst-mode
operation.
Pin settings L6599
4/36
2 Pin settings
2.1 Connection
Figure 2. Pin connection (top view)
2.2 Functions
Table 2. Pin functions
L6599 Pin settings 5/36
Table 2. Pin functions (continued)
Typical system block diagram L6599
6/36 Typical system block diagram
Figure 3. Typical system block diagram
Table 2. Pin functions (continued)
L6599 Electrical data 7/36
4 Electrical data
4.1 Maximum ratings
Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V
4.2 Thermal data
Table 3. Absolute maximum ratings
Table 4. Thermal data
Electrical characteristics L6599
8/36
5 Electrical characteristics
TJ = 0 to 105 °C, VCC = 15 V, VBOOT = 15 V , CHVG = CLVG = 1 nF; CF = 470 pF;
RRFmin = 12 kΩ; unless otherwise specified.
Table 5. Electrical characteristics
L6599 Electrical characteristics 9/36
Table 5. Electrical characteristics (continued)
Electrical characteristics L6599
10/36 Values traking each other
Table 5. Electrical characteristics (continued)
L6599 Typical electrical performance 11/36 Typical electrical performance
Figure 4. Device consumption vs supply
voltage
Figure 5. IC consumption vs
junction temperature
Figure 6. VCC clamp voltage vs
junction temperature
Figure 7. UVLO thresholds vs
junction temperature
Typical electrical performance L6599
12/36
Figure 8. Oscillator frequency vs junction
temperature
Figure 9. Dead-time vs
junction temperature
Figure 10. Oscillator frequency vs
timing components
Figure 11. Oscillator ramp vs
junction temperature
L6599 Typical electrical performance 13/36
Figure 12. Reference voltage vs
junction temperature
Figure 13. Current mirroring ratio vs junction
temperature
Figure 14. OCP delay source current vs
junction temperature
Figure 15. OCP delay thresholds vs junction
temperature
Typical electrical performance L6599
14/36
Figure 16. Standby thresholds vs junction
temperature
Figure 17. Current sense thresholds vs
junction temperature
Figure 18. Line thresholds vs
junction temperature
Figure 19. Line source current vs junction
temperature
Figure 20. Latched disable threshold vs
junction temperature
L6599 Application information 15/36
7 Application information
The L6599 is an advanced double-ended controller specific for resonant half-bridge
topology. In these converters the switches (MOSFETs) of the half-bridge leg are alternately
switched on and OFF (180° out-of-phase) for exactly the same time. This is commonly
referred to as operation at "50 % duty cycle", although the real duty cycle, that is the ratio of
the ON-time of either switch to the switching period, is actually less than 50 %. The reason
is that there is an internally fixed dead-time TD, inserted between the turn-OFF of either
MOSFET and the turn-ON of the other one, where both MOSFETs are OFF. This dead- time
is essential in order for the converter to work correctly: it will ensure soft-switching and
enable high-frequency operation with high efficiency and low EMI emissions. o perform converter's output voltage regulation the device is able to operate in different
modes (Figure 21), depending on the load conditions: Variable frequency at heavy and medium/light load. A relaxation oscillator (see
"Oscillator" section for more details) generates a symmetrical triangular waveform,
which MOSFETs' switching is locked to. The frequency of this waveform is related to a
current that will be modulated by the feedback circuitry. As a result, the tank circuit
driven by the half-bridge will be stimulated at a frequency dictated by the feedback loop
to keep the output voltage regulated, thus exploiting its frequency-dependent transfer
characteristics.
2. Burst-mode control with no or very light load. When the load falls below a value, the
converter will enter a controlled intermittent operation, where a series of a few
switching cycles at a nearly fixed frequency are spaced out by long idle periods where
both MOSFETs are in OFF-state. A further load decrease will be translated into longer
idle periods and then in a reduction of the average switching frequency. When the
converter is completely unloaded, the average switching frequency can go down even
to few hundred Hz, thus minimizing magnetizing current losses as well as all frequency-
related losses and making it easier to comply with energy saving recommendations.
Figure 21. Multi-mode operation
Application information L6599
16/36
7.1 Oscillator
The oscillator is programmed externally by means of a capacitor (CF), connected from pin 3
(CF) to ground, that will be alternately charged and discharged by the current defined with
the network connected to pin 4 (RFmin). The pin provides an accurate 2 V reference with
about 2 mA source capability and the higher the current sourced by the pin is, the higher the
oscillator frequency will be. The block diagram of Figure 22 shows a simplified internal
circuit that explains the operation.
The network that loads the RFmin pin generally comprises three branches: A resistor RFmin connected between the pin and ground that determines the minimum
operating frequency;
2. A resistor RFmax connected between the pin and the collector of the (emitter-grounded)
phototransistor that transfers the feedback signal from the secondary side back to the
primary side; while in operation, the phototransistor will modulate the current through
this branch - hence modulating the oscillator frequency - to perform output voltage
regulation; the value of RFmax determines the maximum frequency the half-bridge will
be operated at when the phototransistor is fully saturated;
3. An R-C series circuit (CSS + RSS) connected between the pin and ground that enables
to set up a frequency shift at start-up (see Chapter 7.3: Soft-start). Note that the
contribution of this branch is zero during steady-state operation.
Figure 22. Oscillator's internal block diagram
The following approximate relationships hold for the minimum and the maximum oscillator
frequency respectively:min 1
3CFRFmin⋅⋅----------- --------------------------= max 1
3CF RFmin RFmax|| ()⋅⋅-------------- ---------------------------------- -----------------=
L6599 Application information 17/36
After fixing CF in the hundred pF or in the nF (consistently with the maximum source
capability of the RFmin pin and trading this off against the total consumption of the device),
the value of RFmin and RFmax will be selected so that the oscillator frequency is able to
cover the entire range needed for regulation, from the minimum value fmin (at minimum input
voltage and maximum load) to the maximum value fmax (at maximum input voltage and
minimum load):
A different selection criterion will be given for RFmax in case burst-mode operation at no-load
will be used (see "Operation at no load or very light load" section).
Figure 23. Oscillator waveforms and their relationship with gate-driving signals
In Figure 23 the timing relationship between the oscillator waveform and the gate-drive
signals, as well as the swinging node of the half-bridge leg (HB) is shown. Note that the low-
side gate-drive is turned on while the oscillator's triangle is ramping up and the high-side
gate-drive is turned on while the triangle is ramping down. In this way, at start-up, or as the
IC resumes switching during burst-mode operation, the low-side MOSFET will be switched
on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor will always be
charged and ready to supply the high-side floating driver.min 1
3CFfmin⋅⋅------------------------------= maxminmaxmin
---------------------=
Application information L6599
18/36
7.2 Operation at no load or very light load
When the resonant half-bridge is lightly loaded or unloaded at all, its switching frequency will
be at its maximum value. To keep the output voltage under control in these conditions and to
avoid losing soft-switching, there must be some significant residual current flowing through
the transformer's magnetizing inductance. This current, however, produces some
associated losses that prevent converter's no-load consumption from achieving very low
values. o overcome this issue, the L6599 enables the designer to make the converter operate
intermittently (burst-mode operation), with a series of a few switching cycles spaced out by
long idle periods where both MOSFETs are in OFF-state, so that the average switching
frequency can be substantially reduced. As a result, the average value of the residual
magnetizing current and the associated losses will be considerably cut down, thus
facilitating the converter to comply with energy saving recommendations.
The device can be operated in burst-mode by using pin 5 (STBY): if the voltage applied to
this pin falls below 1.25 V the IC will enter an idle state where both gate-drive outputs are
low, the oscillator is stopped, the soft-start capacitor CSS keeps its charge and only the 2 V
reference at RFmin pin stays alive to minimize IC's consumption and VCC capacitor's
discharge. The IC will resume normal operation as the voltage on the pin exceeds 1.25 V by
50 mV. o implement burst-mode operation the voltage applied to the STBY pin needs to be related
to the feedback loop. Figure 24 shows the simplest implementation, suitable with a narrow
input voltage range (e.g. when there is a PFC front-end).
Figure 24. Burst-mode implementation: narrow input voltage range
Figure 25. Burst-mode implementation: wide input voltage range
