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L6254STN/a467avai


L6254 BLOCK DIAGRAMCHARGE FREQUENCY SPINDLE SEQUENCERCS A OUT_APUMP LOCK LOOPCTAPBEMF B OUT_BPROCESSINGST ..
L6258 ,PWM CONTROLLEDL6258®PWM CONTROLLED - HIGH CURRENTDMOS UNIVERSAL MOTOR DRIVERABLE TO DRIVE BOTH WINDINGS OF A BI-P ..
L6258 ,PWM CONTROLLEDABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVs Supply Voltage 36 VVCC Logic Supply Voltage 7 ..
L6258E ,PWM CONTROLLEDL6258EPWM CONTROLLED - HIGH CURRENTDMOS UNIVERSAL MOTOR DRIVER■ ABLE TO DRIVE BOTH WINDINGS OF A BI ..
L6258E ,PWM CONTROLLEDABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage 45 VsV Logic Supply Voltage 7 V ..
L6258EA ,PWM CONTROLLED
LC331632M-12 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
LC331632M-70 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
LC338128M-70 ,1 MEG (131072 words x 8 bit) pseudo-SRAMFeatures. 131072 words x 8 bits configuration. CE access time, COE access time, cycle time, operati ..
LC338128M-80 ,1 MEG (131072 words x 8 bit) pseudo-SRAMPin AssignmentAuA1:A7A5"A:"A2Al"1/0:1/021/0:END 1DIP32, SOP32VccA15Ax:1/051/07TADSvns1/04Top viewAu ..
LC33832M-10 ,256K (32768word x 8bit) Pseudo-SRAMFeatures3133-DIP28• 32768 words · 8 bits configuration• Single 5 V ±10% power supply[LC33832S, SL]• ..
LC33832M-70 ,256K (32768word x 8bit) Pseudo-SRAMOrdering number : EN4430CCMOS LSILC33832P, S, M, PL, SL, ML-70/80/10256 K (32768 words · 8 bits) Ps ..


L6254

GENERAL
12V (±10%) OPERATION.
REGISTER BASED ARCHITECTURE
MINIMUM EXTERNAL COMPONENTS
BICMOS+ VERTICAL DMOS (1.5mm)
VCM DRIVER

1.5A DRIVE CAPABILITY
0.9W TOTAL BRIDGE IMPEDANCE AT 25°C
LINEAR MODE
PHASE SHIFT MODULATION(PWM MODE)
INSTANTANEOUS, (GLICH FREE) SWITCH
BETWEEN THE2 MODES
CLASS AB OUTPUT DRIVERS
ZERO CROSSOVERDISTORSION BIT DAC DEFINE OUTPUT CURRENT
SELECTABLETRANSCONDUCTANCE PROGRAMMABLE PARKING VOLTAGE
DYNAMIC BRAKE
SPINDLE DRIVER

2.0A DRIVE CAPABILITY
0.8W TOTAL BRIDGE IMPEDANCE AT 25°C
BEMF, INTERNAL OR EXTERNAL, PROC-
ESSING
SENSOR-LESSMOTOR COMMUTATION
PROGRAMMABLE COMMUTATION PHASE
DELAY
LINEAR MODE AND CONSTANT TOFF PWM
OPERATIONMODE
INTERNAL FREQUENCY LOCKED LOOP
SPEED CONTROL (FLL)
BEMF RECTIFICATION DURING RETRACT
BUILT-IN ALIGNAMENT&GO START-UP
INDUCTIVE SENSING START UP OPTION
RESYNCHRONIZATION
DYNAMIC& REVERSE BRAKE
CONTROLLABLE OUTPUT SLEW RATE
OTHER FUNCTIONS

12V AND 5V MONITORING WITH EXTERNAL
SET TRIPPOINTS AND HYSTERESIS
POWERUP/DOWN SEQUENCING
LOW VOLTAGE SENSE
SLUG FOR POWERDISSIPATION
THERMAL SHUTDOWN AND PRETHERMAL
WARNING
DESCRIPTION

The L6254 integrates intoa single chip both spin-
dle and VCM controllersas wellas power stages.
The deviceis designedfor 12V diskdrive applica-
tion requiring upto 2.0Aof spindle and 1.5Aof
VCM peak currents. serialport withupto25 MHz capability provides
easy interfaceto the microprocessor.A register
controlled Frequency Locked Loop (FLL) allows
flexibilityin setting the spindle speed. Integrated
BEMF processing, digital masking, digital delay,
and sequencing minimize the numberof external
componentsrequired.
Power On Reset (POR) circuitryis included. Upon
detectionofa low voltage condition, PORis as-
serted, the internal registers are reset, and spin-
dle power circuitryis tri-stated.The BEMFis recti-
fied providing power for actuator retraction
followedby dynamic spindle braking.
The deviceis builtin BICMOS technology allow-
ing dense digital/analog circuitryto be combined
witha high power DMOS output stage.
April 1999
TQFP44 (10x10mm)
ORDERING NUMBER: L6254
L6254

12V DISK DRIVE SPINDLE & VCM, POWER CONTROL “COMBO”
PRODUCT PREVIEW
BICMOS TECHNOLOGY

1/17
CHARGE
PUMP
ISO
DRIVER
SUPPLY
FAULT
MONITORS
FREQUENCY
LOCK LOOP SPINDLESEQUENCER
REFERENCE
VOLTAGE
GENERATORBIT
VCMDAC
ZERO CROSS
DETECTION
A=4SUPPLY FLL_RESFLL_FILTER SYS_CLK FCOM SPN_COMP BRK_CAP PWM/SLEW VCC
POR_DELAY
PORB
VDDGND
DGND
V12/2
VCM_CAL
ERROR_IN
ERROR_OUT
SENSE_OUT
OUT_A
OUT_B
RSENSE
OUT_C
VCM_A+
VCC
VCM_A-
SENSE_IN-
SENSE_IN+
D99IN1042
VCM_GND
CTAP
SW1
SDATA
SCLK
SDEN
TR_12V
TR_5V
ISENSE
INDEX
THERMAL
DAC
VCM
CALIBRATION
BEMF
RECTIFICATION
PARKING
VCMCURRENT
CONTROL PSM/LIN
START-UP
RE_SYNC
DYNAMIC/
REVERSE
BRAKE
SPINDLE
CURRENT
CONTROL
PWM/LIN
BEMF
PROCESSING
SERIAL
INTERFACE REGISTERS-
BLOCK DIAGRAM
19202122434241 3940 3837363534
R_SENSE
I_SENSE
OUT_C
CTAP
FCOM
PWM/SLEW
INDEX
OUT_A
R_SENSE
OUT_B
GND
BRK_CAP
VCC
DGND
SYS_CLK
SDATA
SDEN
SCLK
VDD
V12/2
FLL_FILTER
VCM_CAL
SPN_COMPVCCAGNDDAC ERROR_INTR-12V ERROR_OUTSENSE_OUTPOR_DELAYTR_5VPORB
VCM_GND
SENSE_IN+
VCM_A-
VCC
SW1
FLL_RES
VCC
SENSE_IN-
VCM_A+
D98IN84713141516
PIN CONNECTION
L6254

2/17
PIN DESCRIPTION(Pin Types:D= Digital,P= Power,A= Analog) Name Function FCOM Outputof the Spindle zero crossor Current Sense circuit. CTAP Spindle Central Tap usedfor differential BEMF sensing. PWM/SLEW RC network sets the Spindle Linear Slew Rate and PWM OFF-Time. OUT_C Spindle DMOS Half Bridge Output and InputCfor BEMF sensing. I_SENSE Inputto sensethe voltagethe SPINDLE Sense Resistor. R_SENSE Output connectionfor the Motor Current Sense Resistorto ground. OUT_B Spindle DMOS Half Bridge Output and InputBfor BEMF sensing. GND Spindle Ground (Substrate). R_SENSE Output connectionfor the Motor Current Sense Resistorto ground. OUT_A Spindle DMOS Half Bridge Output and InputAfor BEMF sensing. INDEX Inputto allow Spindletobe lockedto Index (servo) pulse. BRK_CAP Storage Capacitorfor brake circuit. typically 5.9V. VCC +12V PowerSupplyfor SpindlePower section. DGND Digital Ground. SYS_CLK Clock Frequencyfor system timers and counters. SDEN Serial DataEnable. Active high inputpinfor the serialport enable. SDATA Serial PortData. Input/Outputpinfor serial data, 8bitsof instruction/address followedby8
bitsof data. Openpinisat logic lowasan input. SCLK Serial PortData Clock. Positive edge triggered clock inputforthe serial data. VDD Digital/Analog power supply. +5V nominally. V12/2 Reference Outputfor VCM control loop. Typically, halfof the VCC except when parking. FLL_FILTER Speed loop R/C compensation connection usedfor FLL mode operation. VCM_CAL VCM loop offset voltage usedfor calibration. CP External Main Charge Pump Capacitor, Typically, Vz+Vccis about 17.8V CS External Charge Pump Capacitor. VCC +12V PowerSupplyfor VCM Power section. VCM_A- VCM Power Amplifier negative output terminal. SENSE_IN+ Non inverting Inputofthe Sense Amplifierfor VCM block. VCM_GND Groundfor VCM Power section. SENSE_IN- Inverting Inputofthe Sense Amplifierfor VCM block. VCM_A+ VCM Power Amplifier positive output terminal. VCC +12V PowerSupplyfor VCM Power section. FLL_RES Resistorfor setting accurate bias current sourcesfor the chip (62K required). SW1 External ISOFET driver. PORB Poweron Reset Output. Low signal indicatesthe failureofthe supplies. TR_5V Set Point Inputfor5V Supply Monitor( 2Vthreshold, 100mV Hysteresis) POR_DELAY Capacitor connectionto setthe Poweron Reset Delay (3V threshold, 2μA charging) SENSE_OUT Outputof the Sense Amplifier. ERROR_OUT Outputof the Error Amplifier. ERROR_IN Inverting Inputofthe Error Amplifier. TR_12V Set Point Inputfor 12VSupply Monitor(2V threshold, 100mV Hysteresis) DAC Outputof the VCM DAC. AGND Analog Ground. For bang gap voltage reference. VCC +12V PowerSupplyfor SpindlePower section. SPN_COMP External RC network that definesthe compensationof theSpindle Transconductance Loop Linear Mode.
L6254

3/17
ELECTRICAL CHARACTERISTICS (All specifications are for0< Tamb <70°C, VCC= 12V; VDD= 5V,
FLL_RES= 62kΩ, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
POWER SUPPLIES

VCC 12V Supply 10.8 13.2 V
IVCC VCC Current SPINDLE+ VCM 20 mA
SPINDLE ONLY 7 mA
VCM ONLY 12 mA
Vrectified VCC Supply Rectified 3.5 13.2 V
Vdd 5V supply 4.5 5.5 V
IVdd 5V supply SPINDLE+ VCM 6 mA
SPINDLE ONLY 7 mA
VCM ONLY 12 mA
ABSOLUTEMAXIMUM RATINGS
Symbol Parameter Value Unit

VCC Maximum Supply voltage -0.5to14 V
Vdd Maximum Logic supply -0.5to6 V
Vinmax Maximum digital input voltage Vdd +0.3V V
Vinmin Minimum digital input voltage GND- 0.3V V
SPINDLE Ipeak Spindle peak sink/source output current 2.1 A
VCM Ipeak VCM peak sink/source output current 1.6 A
Ptot (*) Maximum Total Power Dissipation ≈ 1.7 W
Tstg,Tj Maximum Storage/Junction Temperature -40to 150 °C
THERMAL DATA
Symbol Parameter Value Unit

Rth j-case Thermal Resistance Junction toCase ≈20 °C/W
Rth j-amb(*) Thermal Resistanceto Junctionto ambient ≈4025 with soldered slug
°C/W
°C/W
(*)In typicalapplication with multilayer120x120mm Printed CircuitBoard.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit

VCC Supply voltage 10.8to 13.2 V
Vdd Maximum Logic supply 4.5to5.5 V
Tamb Operating AmbientTemperature 0to70 °C Junction Temperature 0to 125 °C
L6254

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Symbol Parameter Test Condition Min. Typ. Max. Unit
THERMAL SENSING

TSD Shutdown Temperature 150 180 °C
THYS Hysteresis 60 °C
TEW Early Warning TSD-25 °C
SUPPLY MONITOR

VTR Trip Point Input Rising 1.92 2 2.08 V
VHYS Hysteresis Voltage Input falling 100 mV
IDLY Porb Delay Current TR_5V, TR_12V> VTR
Vpordly=2V
1.5 2 2.5 μA
Ron_por Porb Pull Down Ron Vdd>2V and sink 1mA
Vpordly =2V
500 Ω
VDLY Porb Dly Threshold TR_5V, TR_12V> VTR 2.5 3.0 3.5 V
IIN Input Current VIN <4V -1 1 μA
VOLTAGE BOOST

VBOOST Output Voltage VCC+5 VCC+6.3 V
Fosc Internal Oscillator 130 200 250 kHz
SW1 OUTPUT

RGATE Gate Driverfor External Mosfet Internal ResistortoCP 200 kΩ
VGATE Off Gate State Voltagefor
External Mosfet= 1mA VCC= 3.5V 0.7 V
DIGITAL LOGIC LEVELS

VIH Input Logic”1” VDD= 5.5V 2.4 V
VIL Input Logic”0” VDD= 4.5V 0.5 V
VOH Output Logic”1” ISOURCE =20μAVdd-0.2 V
VOL Output Logic”0” ISOURCE= -400μA 0.4 V
FSYSCLK System Clock 20 25 MHz
VCM, DAC

Resolution 14 Bits
Differential Linearity 1 LSB Change
-Tested design
LSB
Integral Linearity 9 Bits
Midscale Offset Referencedto VCC/2 -5 5 mV Convertion Time 5 μs
Full Scale Voltage Referencedto VCC/2 ±1V
Full Scale Error -4 4 %
VCM, ERROR AMPLIFIER

AVOL Open Loop Gain DC 50 db
VOS Input Offset Voltage -5 5 mV
IIB Input Bias Current -250 250 nA
ELECTRICAL CHARACTERISTICS
(Continued)
L6254

5/17
Symbol Parameter Test Condition Min. Typ. Max. Unit
VICM Input Common Mode Range VCC/2-
VCC/2+
Vclamp Output Clamp Voltage -1mALowside/Highside clamp
VCC/2±
2.2V
FODB Unity Gain Bandwidth 10 MHz
VCM, POWER STAGE

RDS(ON) Output ON Resistance (Each
device) =25°C= 125°C
0.8 Operating Current 1.3 A
IO(LEAK) Output Leakage Current VCC= 14V 1.0 mA
VCM, CURRENT SENSE ANPLIFIER
Voltage Gain 3.88 4 4.12 V/V
VICM Input Common Mode Range -0.3 VCC+0.3 V
VOCM Output Common Mode Range -3mAVOS Output Offset Voltage SENSE_IN (±)= VCC/2 -15 15 mV
F3dB 3dB Bandwidth 1 MHz
CMRR Input Common Mode Rejection 50 dB
PSRR Power Supply Rejection Ratio 60 dB
VCM, RETRACT

Vpark RETRACT VOLTAGE PKV_1=0& PKV_2=0
PKV_1=0& PKV_2=1
PKV_1=1& PKV_2=0
PKV_1=1& PKV_2=1
Tretract Retract Time
limitedby the internal oscillator
200kHz
RT0=0& RT1=0
RT0=0& RT1=1
RT0=1& RT1=0
RT0=1& RT1=1
SPINDLE, PWM CURRENT SENSE COMPARATOR
TDLY Delayto FCOM Out 200 500 ns
SPINDLE, POWER STAGE

RDS(ON) OutputOn Resistance (Each
device) =25°C= 125°C
0.74 Start-Up Current 2A
IO(LEAK) Output Leakage Current VCC= 14V 1.0 mA
dVO/dt Output Slew Rate (Linear) Rslew= 100kΩ 0.2 0.3 0.5 V/μs
Output Slew Rate (PWM) Reg#8Eh,Bit0=0
Reg#8Eh,Bit0=1
V/μs
V/μs
BEMFMIN Minimum BENF Voltagefor
Detection 28 40 mVp-p
VHYS Hysteresis 15 mV
FLL CHARGE PUMP OUTPUT

ILEAK Off State Leakage 0< Vfll_res,3V -50 +50 nA
ELECTRICAL CHARACTERISTICS
(Continued)
L6254

6/17
Symbol Parameter Test Condition Min. Typ. Max. Unit On State Current FLL_RES= 62kΩ
ICP=”1”
ICP=”0”
VRCP Current Set Voltage FLL_RES= 62kΩ 1.18 1.225 1.25 V
CURRENT SENSE AMPLIFIER

IBIAS Input Bias Current 2 μA Voltage Gain 3.8 4.0 4.2 V/V
dVo/dt Output Slew Rate 20 V/μs
SERIAL PORT
Symbol Parameter Min. Typ. Max. Unit

TSCK SCLK Period 40 ns
TCKL SCLK low time 15 ns
TCKH SCLK high time 15 ns
TSDENS Enableto SCLK 35 ns
TSDENH SCLKto disable 20 ns
TDS Data set-up time before rising edge SCLK 10 ns
TDH Data Hold Time 10 ns
TSDENL Minimum SDEN Low Time 50 ns
TSDV SCLK falling edge (A6)to SDATA validon READ op. 3 10 ns
TSDV SCLK rising edge (D0-D7)to SDATA Transitionon READop. 5 35 ns
ELECTRICAL CHARACTERISTICS
(Continued)
0A0 A1
1st Byte 2nd Byte D0 D1 D2 D7
SDEN
SCLK
SDATA
SERIAL PORT WRITE TIMING
SERIAL PORT READ TIMING
1A0 A1
1st Byte 2nd Byte
D98IN844 D0 D1 D2 D7
SDEN
SCLK
SDATA
Figure1. SerialPort Timing Information.
L6254

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SERIAL PORT OPERATION
The serial port interfaceisa bi-directional port for reading and writing programming data from/to the in-
ternal registersof this device. For data transfers SDEN*is brought high, serial datais presentedat the
SDATA pin, anda serial clockis appliedto the SCLK pin. After the SDEN* goes high, the first16 pulses
appliedto the SCLK pin will shift the data presentedat the SDATA pin intoan internal shift registeron
the rising edgeof each clock. An internal counter prevents more than16 bits from being shifted into the
register. The datain the shift registeris latched after the 16th SCLK pulse.If less than16 clock pulses
are provided before SDEN* goes low, thedata transferis aborted.
All transfers are shifted into the serial port LSB first. The first byteof the transferisfor R/W and address
and instruction information.The firstbitis R/W instruction bit,0isfor WRITE and1isfor READ.
Following7 bits are Address.
INSTRUCTION,1 BIT
ADDRESS,7 BITS
D98IN845
DATA,8 BITS
SDEN
SCLK
SDATA
Figure2. SerialPort Data Transfer Format.
INTERNAL REGISTER DEFINITION
Reg:
Name:
Type:
Address:
VCM DAC (High) Register
Write only
0Eh
BIT LABEL DESCRIPTION
VDAC BIT8 VCM DACbit8 VDAC BIT9 VCM DACbit9 VDAC BIT10 VCM DACbit10 VDAC BIT11 VCM DACbit11 VDAC BIT12 VCM DACbit12 VDAC BIT13 MSB resistorladderofthe14bit VCM DAC PSM/LINEAR Selects Voice Coil PSMor Linear Output Current Control. 1=PSM
0=Linear. VCM_CAL VCM calibration.1= Enables VCM control circuits andtristates
VCM power transistors.
L6254

8/17
INTERNAL REGISTER DEFINITION
VCM DAC (High and Low) Registers

Bit0 through5of the VCM DAC (High) Registers andbit0 through7of the VCM DAC (Low) Registers
control the absolutevalueof the voice coil current.Bitis the sign bit, controlling the current direction.All
the13 bits are partofa resistor divider network.
Note.Itis requiredto writeon register1to make effective changeson register0.
Reg:
Name:
Type:
Address:
VCM DAC (Low) Registers
Write only
1Eh
BIT LABEL DESCRIPTION
VDAC BIT0 LSB resistor ladderofthe14bit VCM DAC VDAC BIT1 VCM DACbit1 VDAC BIT2 VCM DAC bit2 VDAC BIT3 VCM DAC bit3 VDAC BIT4 VCM DAC bit4 VDAC BIT5 VCM DAC bit5 VDAC BIT6 VCM DAC bit6 VDAC BIT7 VCM DAC bit7
Reg:
Name:
Type:
Address:
Spindle Control Register
Write only
2Eh
BIT LABEL DESCRIPTION
INCRE_SEQ A0to1 transitionof thisbit incrementsthe spindle Sequencer. START_UP 1= Spindle Internal startup,0= Spindle External startup R_SEQ Reset Spindle sequencer.1= Reset sequencerto phase1. RUN 1= Start Spindle ALIGN& GO,0= Reset Spindle control logic. SPIN_EN Enable Spindle section.1= Enable,0= Disable. MEC/ELEC Specifies electricalor mechanical cyclefor Spindle FLL control.
1=Electrical,0= Mechanical. PWM/LINEAR Selects Spindle PWMor Linear Output Current Control.1= PWM,
0=Linear. EXT/INT Externalor internal Spindle loop feedback.1= external feedback
via index pin.
L6254

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