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ADVANCE DATA
PLC621+7
ORDERING NUMBER: L6232B
part of their structure. The ..
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LC331632M-12 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
L6229Q-L6229QTR
PowerSPIN: DMOS driver for three-phase brushless DC motor
August 2010 Doc ID 15209 Rev 3 1/28
L6229QDMOS driver for three-phase brushless DC motor
Features Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A RMS) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Operating frequency up to 100 kHz Non dissipative overcurrent detection and
protection Diagnostic output Constant tOFF PWM current controller Slow decay synchronous rectification 60° and 120° hall effect decoding logic Brake function Cross conduction protection Thermal shutdown Under voltage lockout Integrated fast free wheeling diodes
DescriptionThe L6229Q is a DMOS fully integrated three-
phase motor driver with overcurrent protection.
Realized in BCDmultipower technology, the
device combines isolated DMOS power
transistors with CMOS and bipolar circuits on the
same chip.
The device includes all the circuitry needed to
drive a three-phase BLDC motor including: a
three-phase DMOS bridge, a constant off time
PWM current controller and the decoding logic for
single ended hall sensors that generates the
required sequence for the power stage.
Available in VFQFPN-32 5 x 5 package, the
L6229Q features a non-dissipative overcurrent
protection on the high side power MOSFETs and
thermal shutdown.
Table 1. Device summary
Contents L6229Q2/28 Doc ID 15209 Rev 3
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 T acho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 20
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226.1 Output current capability and ic power dissipation . . . . . . . . . . . . . . . . . . 23
6.2 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
L6229Q Block diagram
Doc ID 15209 Rev 3 3/28
1 Block diagram
Figure 1. Block diagram
Electrical data L6229Q
4/28 Doc ID 15209 Rev 3
2 Electrical data
2.1 Absolute maximum ratings
2.2 Recommended operating conditions
Table 2. Absolute maximum ratings
Table 3. Recommended operating conditions
L6229Q Electrical data
Doc ID 15209 Rev 3 5/28
2.3 Thermal data
Table 4. Thermal data Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 2 ground layer connected through 18 via holes (9 below the IC).
Pin connection L6229Q
6/28 Doc ID 15209 Rev 3
3 Pin connection
Figure 2. Pin connection (top view)
Note: 1 The pins 2 to 8 are connected to die PAD. The die PAD must be connected to GND pin.
L6229Q Pin connection
Doc ID 15209 Rev 3 7/28
Table 5. Pin description
Electrical characteristics L6229Q
8/28 Doc ID 15209 Rev 3
4 Electrical characteristics
Table 6. Electrical characteristics
(VS = 48 V, TA = 25 °C, unless otherwise specified)
L6229Q Electrical characteristics
Doc ID 15209 Rev 3 9/28 Tested at 25 °C in a restricted range and guaranteed by characterization See Figure3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF. See Figure4.
Table 6. Electrical characteristics (continued)
(VS = 48 V, TA = 25 °C, unless otherwise specified)
Electrical characteristics L6229Q
10/28 Doc ID 15209 Rev 3
Figure 3. Switching characteristic definition
Figure 4. Overcurrent detection timing definition
L6229Q Circuit description
Doc ID 15209 Rev 3 11/28
5 Circuit description
5.1 Power stages and charge pump
The L6229Q integrates a three-phase bridge, which consists of 6 power MOSFETs
connected as shown on the block diagram (see Figure 1). each power MOS has an
RDS(ON) = 0.73 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Switching
patterns are generated by the PWM current controller and the hall effect sensor decoding
logic (see relative paragraph 3.3 and 3.5). Cross conduction protection is implemented by
using a dead time (tDT = 1 µs typical value) set by internal timing circuit between the turn off
and turn on of two power MOSFETs in one leg of a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically)
with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are
shown in Table7.
Figure 5. Charge pump circuit
Table 7. Charge pump external component values
Circuit description L6229Q
12/28 Doc ID 15209 Rev 3
5.2 Logic inputs
Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and microcontroller compatible
logic inputs. The internal structure is shown in Figure 6. Typical value for turn-on and turn-off
thresholds are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin EN (Enable) has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 10. If the driver is a standard Push-Pull structure the resistor REN and the capacitor
CEN are connected as shown in Figure 11. The resistor REN should be chosen in the range
from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 10 kΩ and
5.6 nF . More information on selecting the values is found in the overcurrent protection
section.
Figure 6. Logic inputs internal structure
Figure 7. Pin EN open collector driving
Figure 8. Pin EN push-pull driving
L6229Q Circuit description
Doc ID 15209 Rev 3 13/28
5.3 PWM current control
The L6229Q includes a constant off time PWM current controller. The current control circuit
senses the bridge current by sensing the voltage drop across an external sense resistor
connected between the source of the three lower power MOS transistors and ground, as
shown in Figure 9. As the current in the motor increases the voltage across the sense
resistor increases proportionally. When the voltage drop across the sense resistor becomes
greater than the voltage at the reference input pin VREF the sense comparator triggers the
monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates around the upper half of the bridge in slow
decay mode as described in the next section. When the monostable times out, the bridge
will again turn on. Since the internal dead time, used to prevent cross conduction in the
bridge, delays the turn on of the power MOS, the effective off time tOFF is the sum of the
monostable time plus the dead time.
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the pin RC voltage and the status of the bridge. More details
regarding the synchronous rectification and the output stage configuration are included in
the next section.
Immediately after the power MOS turn on, a high peak current flows through the sense
resistor due to the reverse recovery of the freewheeling diodes. The L6229Q provides a 1 µs
blanking time tBLANK that inhibits the comparator output so that the current spike cannot
prematurely re trigger the monostable.
Figure 9. PWM current controller simplified schematic
Circuit description L6229Q
14/28 Doc ID 15209 Rev 3
Figure 10. Output current regulation waveforms
Figure 11 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
Dead Time with:
20 kΩ ≤ ROFF ≤ 100 kΩ
0.47 nF ≤ COFF ≤ 100 nF
tDT = 1 µs (typical value)
Therefore:
tOFF(MIN) = 6.6 µs
tOFF(MAX) = 6 ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the
pin RCOFF . The rise time tRCRISE will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time tON, which
depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a
good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller
than the minimum on time tON(MIN).
