L6229PD ,DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTORAbsolute Maximum RatingsSymbol Parameter Test conditions Value UnitV Supply Voltage V = V = V 60 VS ..
L6229Q ,PowerSPIN: DMOS driver for three-phase brushless DC motorElectrical characteristics . . . . . 85 Circuit description . . 115.1 Power stages and ch ..
L6229QTR ,PowerSPIN: DMOS driver for three-phase brushless DC motorFeatures■ Operating supply voltage from 8 to 52 V■ 2.8 A output peak current (1.4 A RMS)■ R 0.73 Ω ..
L6230 ,PowerSPIN: DMOS driver for three-phase brushless DC motorFeatures■ Operating supply voltage from 8 to 52 V■ 2.8 A output peak current (1.4 A RMS)■ R 0.73 Ω ..
L6232B ,SPINDLE DRIVERBLOCK DIAGRAM
ADVANCE DATA
PLC621+7
ORDERING NUMBER: L6232B
part of their structure. The ..
L6232E ,SPINDLE DRIVERELECTRICAL CHARACTERISTICS (continued)Symbol Parameter Test Condition Min. Typ. Max. UnitG LIN Erro ..
LC322260J-70 ,2 MEG (131072 words x 16 bits) DRAM fast page mode, byte reed/writePin assignment conforms to the JEDEC standards for4M DRAM (262144 words x 16 bits, 2C-AsnCrgtype). ..
LC322260J-80 ,2 MEG (131072 words x 16 bits) DRAM fast page mode, byte reed/writeAbsolute Maximum RatingsParameter Symbol Ratings Unit NoteMaximum supply voltage Vcc max -IOto +7.0 ..
LC322271M-80 ,2MEG (131072words x 16bit) DRAM fast page mode, byte writeElectrical Characteristics at Ta = 0 to +70°C, V = 5 V ± 10%CCLC322271J, M, TParameter Symbol Condi ..
LC32464M-80 ,256K (65536 words X 4 bits) DRAM Fast Page ModeFeatures. 65536 words K 4 bits configuration.. RAS access time/cycle time/power dissipation256 K (6 ..
LC32464P-80 ,256K (65536 words x 4 bit) DRAM fast page modeBlock DiagramR A S o---- Clock generator No,1 ___-__- (w --C) v C CCAS Cy- 9., Clock generalorNo. 2 ..
LC331632M-12 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
L6229PD
DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTOR
1/25
L6229October 2004
1FEATURES OPERATING SUPPLY VOLTAGE FROM 8 TO
52V 2.8A OUTPUT PEAK CURRENT (1.4A DC) RDS(ON) 0.73Ω TYP. VALUE @ Tj = 25 °C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT
DETECTION AND PROTECTION DIAGNOSTIC OUTPUT CONSTANT tOFF PWM CURRENT
CONTROLLER SLOW DECAY SYNCHR. RECTIFICATION 60° & 120° HALL EFFECT DECODING LOGIC BRAKE FUNCTION TACHO OUTPUT FOR SPEED LOOP CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDERVOLTAGE LOCKOUT INTEGRATED FAST FREEWEELING DIODES
DESCRIPTIONThe L6229 is a DMOS Fully Integrated Three-Phase
Motor Driver with Overcurrent Protection.
Realized in MultiPower-BCD technology, the device
combines isolated DMOS Power Transistors with
CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to drive a
three-phase BLDC motor including: a three-phase
DMOS Bridge, a constant off time PWM Current Con-
troller and the decoding logic for single ended hall
sensors that generates the required sequence for the
power stage.
Available in PowerDIP24 (20+2+2), PowerSO36 and
SO24 (20+2+2) packages, the L6229 features a non-
dissipative overcurrent protection on the high side
Power MOSFETs and thermal shutdown.
DMOS DRIVER FOR
THREE-PHASE BRUSHLESS DC MOTOR
Rev. 3
L6229
Figure 2. Block Diagram
Table 2. Absolute Maximum Ratings
3/25
L6229
Table 3. Recommended Operating Condition
Table 4. Thermal Data(1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 µm).
(2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm).
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm),
16 via holes and a ground layer.
(4) Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board.
L6229
Figure 3. Pin Connections (Top view)(5) The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Table 5. Pin Description
5/25
L6229
Table 6. Electrical Characteristics (VS = 48V , Tamb = 25 °C , unless otherwise specified)
Output DMOS Transistors
Table 5. Pin Description (continued)
L6229
Source Drain Diodes
Logic Input (H1, H2, H3, EN, FWD/REV, BRAKE)
Switching Characteristics
PWM Comparator and Monostable
Tacho Monostable
Table 6. Electrical Characteristics (continued)(VS = 48V , Tamb = 25 °C , unless otherwise specified)
7/25
L6229(6) Tested at 25°C in a restricted range and guaranteed by characterization.
(7) See Fig. 4.
(8) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
(9) See Fig. 5.
Figure 4. Switching Characteristic Definition
Figure 5. Overcurrent Detection Timing Definition
Over Current Detection & Protection
Table 6. Electrical Characteristics (continued)(VS = 48V , Tamb = 25 °C , unless otherwise specified)
L6229 CIRCUIT DESCRIPTION
3.1 POWER STAGES and CHARGE PUMPThe L6229 integrates a Three-Phase Bridge, which consists of 6 Power MOSFETs connected as shown on the
Block Diagram. Each Power MOS has an RDS(ON) = 0.73Ω (typical value @25°C) with intrinsic fast freewheeling
diode. Switching patterns are generated by the PWM Current Controller and the Hall Effect Sensor Decoding
Logic (see relative paragraphs). Cross conduction protection is implemented by using a dead time (tDT = 1µs
typical value) set by internal timing circuit between the turn off and turn on of two Power MOSFETs in one leg
of a bridge.
Pins VSA and VSB MUST be connected together to the supply voltage (VS).
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the
power supply voltage. The Bootstrapped Supply (VBOOT) is obtained through an internal oscillator and few ex-
ternal components to realize a charge pump circuit as shown in Figure 6. The oscillator output (pin VCP) is a
square wave at 600KHz (typically) with 10V amplitude. Recommended values/part numbers for the charge
pump circuit are shown in Table 7.
Table 7. Charge Pump External Component Values.
Figure 6. Charge Pump Circuit
3.2 LOGIC INPUTSPins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and µC compatible logic inputs. The internal struc-
ture is shown in Figure 4. Typical value for turn-ON and turn-OFF thresholds are respectively Vth(ON) = 1.8V and
Vth(OFF) = 1.3V.
Pin EN (enable) may be used to implement Overcurrent and Thermal protection by connecting it to the open collector
DIAG output If the protection and an external disable function are both desired, the appropriate connection must be
implemented. When the external signal is from an open collector output, the circuit in Figure 8 can be used . For ex-
ternal circuits that are push pull outputs the circuit in Figure 9 could be used. The resistor REN should be chosen in
the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF. More
information for selecting the values can be found in the Overcurrent Protection section.
9/25
L6229
Figure 7. Logic Input Internal Structure
Figure 9. Pin EN Push-Pull Driving
3.3 PWM CURRENT CONTROLThe L6229 includes a constant off time PWM Current Controller. The current control circuit senses the bridge
current by sensing the voltage drop across an external sense resistor connected between the source of the
three lower power MOS transistors and ground, as shown in Figure 10. As the current in the motor increases
the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor
becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the
monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the mo-
tor current recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section.
When the monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent
cross conduction in the bridge, delays the turn on of the power MOS, the effective Off Time tOFF is the sum of
the monostable time plus the dead time.
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the pin RC voltage and the status of the bridge. More details regarding the Synchronous Rectification and
the output stage configuration are included in the next section.
Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the re-
L6229 verse recovery of the freewheeling diodes. The L6229 provides a 1µs Blanking Time tBLANK that inhibits the
comparator output so that the current spike cannot prematurely retrigger the monostable.
Figure 10. PWM Current Controller Simplified Schematic
Figure 11. Output Current Regulation Waveforms
11/25
L6229Figure 12 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately
calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with:
20KΩ ≤ ROFF ≤ 100KΩ
0.47nF ≤ COFF ≤ 100nF
tDT = 1µs (typical value)
Therefore:
tOFF(MIN) = 6.6µs
tOFF(MAX) = 6ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The
Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the On Time tON, which depends by motors and supply parameters, has to
be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the On Time tON
can not be smaller than the minimum on time tON(MIN).
tRCRISE = 600 · COFF
Figure 13 shows the lower limit for the On Time tON for having a good PWM current regulation capacity. It has
to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller
than tRCRISE - tDT. In this last case the device continues to work but the Off Time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller On Time and, therefore, higher
switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit
performance.
Figure 12. tOFF versus COFF and ROFF.ONtON MIN() >2.5µs (typ. value)=ONt RCRISEtDT–>⎩⎨⎧
L6229
Figure 13. Area where tON can vary maintaining the PWM regulation.
3.4 SLOW DECAY MODEFigure 14 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two
legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure
and the third leg will be off. At the start of the Off Time, the lower power MOS is switched off and the current
recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slow-
ly. After the Dead Time the upper power MOS is operated in the synchronous rectification mode reducing the
impendence of the freewheeling diode and the related conducting losses. When the monostable times out, up-
per MOS that was operating the synchronous mode turns off and the lower power MOS is turned on again after
some delay set by the Dead Time to prevent cross conduction.
Figure 14. Slow Decay Mode Output Stage Configurations
13/25
L6229
3.5 DECODING LOGICThe Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase
bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3-
phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors
spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a uni-
versal IC without dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor posi-
tions with 120 electrical degrees sensor phasing (see Figure 15, positions 1, 2, 3a, 4, 5 and 6a) and six combi-
nations are valid for rotor positions with 60 electrical degrees phasing (see Figure 17, positions 1, 2, 3b, 4, 5
and 6b). Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 elec-
trical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phas-
ing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following the Table 8. For any input
configuration (H1, H2 and H3) there is one output configuration (OUT1, OUT2 and OUT3). The output configura-
tion 3a is the same than 3b and analogously output configuration 6a is the same than 6b.
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the
Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive
the motor with all the four conventions by changing the direction set.
Table 8. 60 and 120 Electrical Degree Decoding Logic in Forward Direction.
Figure 15. 120° Hall Sensor Sequence.
