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L6225DSTMN/a100avaiDUAL DMOS FULL BRIDGE MOTOR DRIVER
L6225DTRSTN/a1200avaiDMOS DUAL FULL BRIDGE DRIVER
L6225NSTN/a1200avaiDMOS DUAL FULL BRIDGE DRIVER
L6225PDSTMN/a26avaiDMOS DUAL FULL BRIDGE DRIVER


L6225DTR ,DMOS DUAL FULL BRIDGE DRIVERAPPLICATIONS■ BIPOLAR STEPPER MOTORBCD technology, which combines isolated DMOS■ DUAL OR QUAD DC MO ..
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L6225PD ,DMOS DUAL FULL BRIDGE DRIVERapplications, realized in MultiPower-high side PowerMOSFETs and thermal shutdown.
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L6226DTR ,DMOS DUAL FULL BRIDGE DRIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Test conditions Value UnitSupply Voltage V = V = V 60 VVS ..
L6226N ,DMOS DUAL FULL BRIDGE DRIVERL6226DMOS DUAL FULL BRIDGE DRIVER■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V■ 2.8A OUTPUT PEAK CURRENT ..
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LC321664BJ ,1 MEG (65536 words X 16 bits) DRAM Fast Page Mode, Byte WriteFeatures. 65536 words M 16 bits configuration,. Single 5 V , 10% power supply.. All input and outpu ..
LC321664BJ-70 ,1 MEG (65536 words x 16 bit) DRAM, fast page mode, byte writeFeatures. 65536 words M 16 bits configuration,. Single 5 V , 10% power supply.. All input and outpu ..
LC321664BJ-80 ,1 MEG (65536 words x 16 bit) DRAM fast page mode, byte writeOrdering number : EN5082AOve rviewThe LC321664BJ, BM, BT is a CMOS dynamic RAMoperating on a single ..


L6225D-L6225DTR-L6225N-L6225PD
DMOS DUAL FULL BRIDGE DRIVER
1/20
L6225

September 2003 OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A OUTPUT PEAK CURRENT (1.4A DC) RDS(ON) 0.73Ω TYP. VALUE @ Tj = 25 °C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT
PROTECTION PARALLELED OPERATION CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
BIPOLAR STEPPER MOTOR DUAL OR QUAD DC MOTOR
DESCRIPTION

The L6225 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar circuits on
the same chip. Available in PowerDIP20 (16+2+2),
PowerSO20 and SO20(16+2+2) packages, the
L6225 features a non-dissipative protection of the
high side PowerMOSFETs and thermal shutdown.
BLOCK DIAGRAM

DMOS DUAL FULL BRIDGE DRIVER
L6225
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
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L6225
THERMAL DATA
PIN CONNECTIONS (Top View)

(5) The slug is internally connected to pins 1,10,11 and 20 (GND pins).
(1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35μm).
(2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35μm).
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35μm), 16 via holes
and a ground layer.
(4) Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
L6225
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(6) Also connected at the output drain of the Overcurrent and Thermal protection MOSFET. Therefore, it has to be driven putting in series a
resistor with a value in the range of 2.2kΩ - 180KΩ, recommended 100kΩ
PIN DESCRIPTION
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L6225
ELECTRICAL CHARACTERISTICS

(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Output DMOS Transistors
Source Drain Diodes
Logic Input
Switching Characteristics
L6225
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(7) Tested at 25°C in a restricted range and guaranteed by characterization.
(8) See Fig. 1.
(9) See Fig. 2.
Over Current Protection
ELECTRICAL CHARACTERISTICS (continued)

(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
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L6225
Figure 2. Overcurrent Detection Timing Definition
L6225
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CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP

The L6225 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rd-
son=0.73ohm (typical value @25°C), with intrinsic
fast freewheeling diode. Cross conduction protection
is achieved using a dead time (td = 1μs typical) be-
tween the switch off and switch on of two Power MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output
(VCP) is a square wave at 600kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
Figure 3. Charge Pump Circuit
LOGIC INPUTS

Pins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and
μC compatible logic inputs. The internal structure is
shown in Fig. 4. Typical value for turn-on and turn-off
thresholds are respectively Vthon=1.8V and
Vthoff=1.3V.
Pins ENA and ENB have identical input structure with
the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) are also connected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The ENA and ENB in-
puts may be driven in one of two configurations as
shown in figures 5 or 6. If driven by an open drain
(collector) structure, a pull-up resistor REN and a ca-
pacitor CEN are connected as shown in Fig. 5. If the
driver is a standard Push-Pull structure the resistor
REN and the capacitor CEN are connected as shown
in Fig. 6. The resistor REN should be chosen in the
range from 2.2kΩ to 180KΩ. Recommended values
for REN and CEN are respectively 100KΩ and 5.6nF.
More information on selecting the values is found in
the Overcurrent Protection section.
Figure 4. Logic Inputs Internal Structure
Figure 6. ENA and ENB Pins Push-Pull Driving
TRUTH TABLE
= Don't care
High Z = High Impedance Output
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L6225
NON-DISSIPATIVE OVERCURRENT PROTECTION

The L6225 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
circuit to ground or between two phases of the bridge. With this internal over current detection, the external cur-
rent sense resistor normally used and its associated power dissipation are eliminated. Figure 7 shows a simpli-
fied schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent IREF. When the output current in one bridge reaches the detection threshold (typically 2.8A) the relative
OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn
off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an ex-
ternal R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means
of the accurate thresholds of the logic inputs.
Figure 7. Overcurrent Protection Simplified Schematic

Figure 8 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal opera-
tion can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
CEN and REN values and its magnitude is reported in Figure 9. The Delay Time tDELAY before turning off the bridge
when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 10.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN
should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should
be chosen according to the desired Disable Time.
The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN
are respectively 100KΩ and 5.6nF that allow obtaining 200μs Disable Time.
L6225
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Figure 8. Overcurrent Protection Waveforms
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