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L6207STN/a100avaiDMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER
L6207D013TRSTN/a5000avaiDMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER
L6207PD013TRSTMN/a1383avaiDMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER


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L6207-L6207D013TR-L6207PD013TR
DMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER
1/23
L6207

September 2003 OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 5.6A OUTPUT PEAK CURRENT (2.8A DC) RDS(ON) 0.3Ω TYP. VALUE @ Tj = 25 °C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT
PROTECTION DUAL INDEPENDENT CONSTANT tOFF PWM
CURRENT CONTROLLERS SLOW DECAY SYNCHRONOUS
RECTIFICATION CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
BIPOLAR STEPPER MOTOR DUAL DC MOTOR
DESCRIPTION

The L6207 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar circuits on
the same chip. The device also includes two inde-
pendent constant off time PWM Current Controllers
that performs the chopping regulation. Available in
PowerDIP24 (20+2+2), PowerSO36 and SO24
(20+2+2) packages, the L6207 features a non-dissi-
pative overcurrent protection on the high side Power
MOSFETs and thermal shutdown.
BLOCK DIAGRAM

DMOS DUAL FULL BRIDGE DRIVER
WITH PWM CURRENT CONTROLLER
L6207
2/23
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
3/23
L6207
THERMAL DATA
PIN CONNECTIONS (Top View)

(5) The slug is internally connected to pins 1,18,19 and 36 (GND pins).
(1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35μm).
(2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35μm).
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35μm), 16 via holes
and a ground layer.
(4) Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
L6207
4/23
PIN DESCRIPTION
5/23
L6207

(6) Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in
series a resistor with a value in the range of 2.2KΩ - 180KΩ, recommended 100KΩ.
ELECTRICAL CHARACTERISTICS

(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Output DMOS Transistors
Source Drain Diodes
Logic Input
PIN DESCRIPTION (continued)
L6207
6/23
(7) Tested at 25°C in a restricted range and guaranteed by characterization.
(8) See Fig. 1.
(9) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
(10) See Fig. 2.
Switching Characteristics
PWM Comparator and Monostable
Over Current Protection
ELECTRICAL CHARACTERISTICS (continued)

(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
7/23
L6207
Figure 2. Overcurrent Detection Timing Definition
L6207
8/23
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP

The L6207 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rdson =
0.3ohm (typical value @ 25°C), with intrinsic fast
freewheeling diode. Cross conduction protection is
achieved using a dead time (td = 1μs typical) be-
tween the switch off and switch on of two Power MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped
(VBOOT) supply is obtained through an internal Os-
cillator and few external components to realize a
charge pump circuit as shown in Figure 3. The oscil-
lator output (VCP) is a square wave at 600kHz (typi-
cal) with 10V amplitude. Recommended values/part
numbers for the charge pump circuit are shown in
Table1.
Table 1. Charge Pump External Components
Values
Figure 3. Charge Pump Circuit
LOGIC INPUTS

Pins IN1A, IN2B, IN1B and IN2B are TTL/CMOS and
uC compatible logic inputs. The internal structure is
shown in Fig. 4. Typical value for turn-on and turn-off
thresholds are respectively Vthon = 1.8V and Vthoff
= 1.3V.
Pins ENA and ENB have identical input structure with
the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) are also connected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The ENA and ENB in-
puts may be driven in one of two configurations as
shown in figures 5 or 6. If driven by an open drain
(collector) structure, a pull-up resistor REN and a ca-
pacitor CEN are connected as shown in Fig. 5. If the
driver is a standard Push-Pull structure the resistor
REN and the capacitor CEN are connected as shown
in Fig. 6. The resistor REN should be chosen in the
range from 2.2kΩ to 180KΩ. Recommended values
for REN and CEN are respectively 100KΩ and 5.6nF.
More information on selecting the values is found in
the Overcurrent Protection section.
Figure 4. Logic Inputs Internal Structure
Driving
Figure 6. ENA and ENB Pins Push-Pull Driving
9/23
L6207
TRUTH TABLE
= Don't care
High Z = High Impedance Output
GND (Vs) = GND during Ton, Vs during Toff
(*) Valid only in case of load connected between OUT1 and OUT2
PWM CURRENT CONTROL

The L6207 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be-
tween the source of the two lower power MOS transistors and ground, as shown in Figure 7. As the current in
the load builds up the voltage across the sense resistor increases proportionally. When the voltage drop across
the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense com-
parator triggers the monostable switching the low-side MOS off. The low-side MOS remain off for the time set
by the monostable and the motor current recirculates in the upper path. When the monostable times out the
bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays
the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 7. PWM Current Controller Simplified Schematic

Figure 8 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the RC pin voltage and the status of the bridge. Immediately after the low-side Power MOS turns on, a
high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The
L6207 provides a 1μs Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot
prematurely re-trigger the monostable.
L6207
10/23
Figure 8. Output Current Regulation Waveforms

Figure 9 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately cal-
culated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with:
20KΩ ≤ ROFF ≤ 100KΩ
0.47nF ≤ COFF ≤ 100nF
tDT = 1μs (typical value)
Therefore:
tOFF(MIN) = 6.6μs
tOFF(MAX) = 6ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The
Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to
11/23
L6207

be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON
can not be smaller than the minimum on time tON(MIN).
tRCRISE = 600 · COFF
Figure 10 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to
be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller
than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit
performance.
Figure 9. tOFF versus COFF and ROFF
ONtON MIN() >1.5μs (typ. value)=ONt RCRISEtDT–>
L6207
12/23
Figure 10. Area where tON can vary maintaining the PWM regulation.
SLOW DECAY MODE

Figure 11 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchro-
nous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 11. Slow Decay Mode Output Stage Configurations
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