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L5994
ADJUSTABLE TRIPLE OUTPUT POWER SUPPLY CONTROLLER
1/26
L5994
L5994AApril 2002
FEATURE DUAL PWM CONTROLLERS ADJUSTABLE
1.9V to 5.3V(Section1)
1.6V to 3.5V(Section2) AUXILIARY DRIVER FOR LINEAR
REGULATOR CURRENT MODE CONTROL USING A LOW
SENSE RESISTOR DUAL SYNC RECTIFIERS DRIVERS "ONE SHOT" FEATURE (L5994A only) 96% EFFICIENCY ACHIEVABLE 50μA@12V STAND BY CONSUMPTION 4.75V TO 25V OPERATING SUPPLY VOLTAGE EXCELLENT LOAD TRANSIENT RESPONSE "PULSE SKIPPING" FUNCTION OUTPUT UNDER VOLTAGE SHUTDOWN ADAPTATIVE ANTI SHOOT-THROUGH
CONTROL OVER/UNDER VOLTAGE DETECTION POWER GOOD SIGNALS SEPARATED DISABLE THERMAL SHUTDOWN
APPLICATIONS NOTEBOOK AND SUB NOTEBOOK
COMPUTERS 1.8V AND 2.5V I/O SUPPLY WORDPAD INTERNET APPLIANCE
DESCRIPTIONThe device provides a dual PWM controller and a
linear driver controller that can support the complete
power management in mobile equipment with high
efficiency.
ADJUSTABLE TRIPLE OUTPUT
POWER SUPPLY CONTROLLER
Figure 1. System Block Diagram
L5994 - L5994A2/26
DESCRIPTION (continued)The device produces an adjustable regulated voltage in both sections and a linear regulated voltage with an
external bipolar such as for PCMCIA applications.
The auxiliary linear driver is able to source up to 1A for 12V bus and is also possible to use it for the regulation
of 2.5V from 5V bus.
Synchronous rectification and pulse skipping mode for the buck sections optimise the overall efficiency over a
wide load current range.
The two high performance PWM output sections are monitored for over voltage, under voltage and over current
conditions.
A POWER GOOD signal is provided for each section.
On detection of a fault, the relevant POWER GOOD signal is generated and a specific shutdown procedure
takes place to prevent physical damage and data corruption.
A disable function allows to manage the output power sections separately, optimising the quiescent consump-
tion of the IC in stand-by conditions.
The internal architecture is a current mode that allows to have fast transient response without compromise the
efficiency due to the ultra low sense resistor.
Under voltage shutdown is forced in case of short circuit in one of the two sections.
The drivers are provided of an adaptative anti cross conduction system for high output current application
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTIONS (Top views)
3/26
L5994 - L5994A
BLOCK DIAGRAM
ELECTRICAL CHARACTERISTICS (Vin = 12V; Tj = 25°C; Vosc = GND; unless otherwise specified.)
L5994 - L5994A4/26
ELECTRICAL CHARACTERISTICS (continued)
5/26
L5994 - L5994A
ELECTRICAL CHARACTERISTICS (continued)
L5994 - L5994A6/26
PIN DESCRIPTION
7/26
L5994 - L5994A
Detailed Functional DescriptionIn the device block diagram six fundamental functional blocks can be identified: 1.9V to 5.1V step-down PWM switching regulator (section 1, pins 1, 4 to 8, 30 to 32); 1.66V to 3.3V step-down PWM switching regulator (section 2, pins 17 to 20, 24 to 27); Linear regulator driver for an external PNP transistor (pins 21,22); 5V low drop-out linear regulator (pin 29); 2.5V reference voltage generator (pin 12); Power Management section (pins 9 to 11, 14,16).
The chip is supplied through pin Vin (2), typically by a battery pack or the output of an AC-DC adapter, with a
voltage that can range from 5V to 25V. The return of the bias current of the device is the signal ground pin SGND
(13), which references the internal logic circuitry. The drivers of the external MOSFET's have their separate cur-
rent return, namely the power ground pin PGND (28). Take care of keeping separate the routes of signal ground
and the power ground pin when laying out the PCB (see "Layout and grounding" section). The two PWM regu-
lators share the internal oscillator, programmable or synchronizable through pin OSC (15).
PWM RegulatorsEach PWM regulator includes control circuitry as well as gate-drive circuits for a step-down DC-DC converter
in buck topology using synchronous rectification and current mode control.
The two regulators are independent and almost identical. As one can see in the Block Diagram, they share only
PIN DESCRIPTION (continued)
L5994 - L5994A8/26
the oscillator and the internal supply and differ for the pre-set output voltages.
Each converter can be turned on and off independently: RUN1 and RUN2 are control inputs which disable the
relevant section when a low logic level (below 0.8 V) is applied and enable its operation with a high logic level
(above 2.4 V). When both inputs are low the device is in stand-by condition and its current consumption is ex-
tremely reduced (less than 120mA over the entire input voltage range).
The device is able to regulate the desired output voltage in two different ways: classic PWM operation and Pulse
Skip operation (see the relevant sections).
OscillatorThe oscillator, which does not require any external timing component, controls the PWM switching frequency.
This can be either 200 or 300 kHz, depending on the logic state of the control pin OSC, or else can be synchro-
nized by an external oscillator.
If the OSC pin is grounded or connected to pin PREG5 (5V) the oscillator works at 200kHz. By connecting the
OSC pin to a 2.5 V voltage, 300 kHz operation will be selected. Moreover, if pin OSC is fed with an external
signal like the one shown in fig. 2, the oscillator will be synchronized by its falling edges.
Considering the spread of the oscillator, synchronization can be guaranteed for frequencies above 230kHz.
Even though a maximum frequency value is in practice imposed by efficiency considerations it should be noticed
that increasing frequency too much arises problems (noise, subharmonic oscillation, etc.) without significant
benefits in terms of external component size reduction and better dynamic performance.
The oscillator imposes a time interval (300 ns min.), during which the high-side MOSFET is definitely OFF, to
recharge the bootstrap capacitor (see "MOSFET's Drivers" section). This, implies a limit on the maximum duty
cycle (88.5%@fSW=300kHz, 92.6%@fsw=200kHz, worst case) which, in turn, imposes a limit on the minimum
operating input voltage.
Figure 2. Synchronization signal and operation
PWM OperationThe control loop does not employ a traditional error amplifier in favour of an error summing comparator which
sums the reference voltage, the feedback signal, the voltage drop across an external sense resistor and a slope
compensation ramp (to avoid subharmonic oscillation with duty cycles greater than 50%) with the appropriate
signs.
With reference to the schematic of fig. 3, the output latch of both controllers is set by every pulse coming from
9/26
L5994 - L5994Athe oscillator. That turns off the low-side MOSFET (synchronous rectifier) and, when the low-side gate voltage
falls below 0.3V to prevent cross-conduction, turns on the high-side one, thus allowing energy to be drawn from
the input source and stored in the inductor.
The error summing, by comparing the above mentioned signals, determines the moment in which the output
latch is to be reset. The high-side MOSFET is then turned off and the synchronous rectifier is turned on when
the voltage on the high-side MOSFET source falls below 2V to prevent cross-conduction, thus making the in-
ductor current recirculate. The high side mosfet is in any case turned off on the clock signal falling edge: this is
the reason why the duty cicle is limited in its maximum value.
The reached state is maintained until the next oscillator pulse.
The open-loop transfer function of such a kind of control system, under the assumption of an ideal slope com-
pensation, is:
where A is the gain of the error summing comparator, which is 2 by design.
The system is inherently very fast since it tends to correct output voltage deviations nearly on a cycle-by-cycle
basis. Actually, in case of line or load changes, few switching cycles can be sufficient for the transient to expire.
The operation above illustrated is modified during particular or anomalous conditions. Leaving out other circum-
stances (described in "Protections" section) for the moment, consider when the load current is low enough or
during the first switching cycles at start-up: the inductor current may become discontinuous, so it is zero during
the last part of each cycle. In such a case, a "zero current comparator" detects the event and turns off the syn-
chronous rectifier, avoiding inductor current reversal and reproducing the natural turn-off of a diode when re-
verse biased. This allows to increase the efficiency in ligth load. Both MOSFET's stay in off state until the next
oscillator pulse.
Figure 3. Control loop.
Synchronous RectificationVery high efficiency is achieved at high load current with the synchronous rectification technique, which is par-
ticularly advantageous because of the low output voltage. The low-side MOSFET, that is the synchronous rec-
tifier, is selected with a very low on-resistance, so that the paralleled Schottky diode is not turned on, except for
the small time in which neither MOSFET is conducting. The effect is a considerable reduction of power loss dur-
ing the recirculation period. () A Ro sense⋅--------- ----------------- 1 s ESR CO⋅⋅+ RoCo⋅⋅+ () 1s RF CF⋅⋅+ ()⋅- --------------- --------------- ---------------- --------------- --------------- ----------⋅⋅=
L5994 - L5994A10/26
Although the Schottky might appear to be redundant, it is not in a system where a very high efficiency is re-
quired. In fact, its lower threshold prevents the lossy body-diode of the synchronous rectifier MOSFET from turn-
ing on during the above mentioned dead-time. Both conduction and reverse recovery losses are cut down and
efficiency can improve of 1-2% in some cases. Besides a small diode is sufficient since it conducts for a very
short time.
See the "Power Management" section to see how both synchronous rectifiers are used to ensure zero voltage
output in stand-by conditions or in case of overvoltage.
Pulse-skipping operationTo achieve high efficiency at light load current as well, under this condition the regulators change their operation
(unless this feature is disabled): they abandon PWM and enter the so-called pulse-skipping mode, in which a
single switching cycle takes place every many oscillator periods.
The "light load condition" is detected when the voltage across the external sense resistor (VRSENSE) does not
exceed the pulse skipping threshold (13mV typ.) while the high-side MOSFET is conducting. When the reset
signal of the output latch comes from the error summing comparator while VRSENSE is below this value, it is ig-
nored and the actual reset is driven as soon as VRSENSE reaches the pulse skipping threshold. This gives some
extra energy that maintains the output voltage above its nominal value for a while. The oscillator pulses now set
the output latch only when the feedback signal indicates that the output voltage has fallen below its nominal
value. In this way, most of oscillator pulses are skipped and the resulting switching frequency is much lower, as
expressed by the following relationship:
where K = 3.2×103 and fPS is in Hz. As a result, the losses due to switching and to gate-drive, which mostly
account for power dissipation at low output power, are considerably reduced.
The section 1 can work with the input voltage very close to the output one (i.e. the output voltage is 5V), where
the current waveform may be so flat to prevent pulse-skipping from being activated. To avoid this, the pulse-
skipping threshold (of section 1 only) is roughly halved at low input voltages (VIN < 6.8V). Under this condition,
in the above formula the constant K becomes 12.8×103.
When in pulse-skipping, the output voltage is some ten mV higher than in PWM mode, just because of its mode
of operation. If this "load regulation" effect is undesirable for any reason, the pulse skipping feature can be dis-
abled (see "Power Management" section) to the detriment of efficiency at light load.
MOSFET's DriversTo get the gate-drive voltage for the high-side N-channel MOSFET a bootstrap technique is employed. A ca-
pacitor is alternately charged through a diode from the 5V PREG5 line when the high-side MOSFET is OFF and
then connected to its gate-source leads by the internal floating driver to turn the MOSFET on. The PREG5 line
is used to drive the synchronous rectifier as well, and therefore the use of low-threshold MOSFET's (the so-
called "logic-level" devices) is highly recommended.
The drivers are of "dynamic" type, which means they do not give origin to current consumption when they are
in static conditions (ON or OFF), but only during transitions. This feature is aimed at minimizing the power con-
sumption of the device even during stand-by when both low-side MOSFET's are ON.
Adaptative anti shoot-through protection is implemented to prevent cross-conduction: the low side mosfet turn
on is disbled until the HSRC pin is above 2V and, in the same way, the high side mosfet turn on is disabled until
the RGATE pin is above 0.3V. During the time in which both mosfets are in off state, the recirculation of the
current is insured by the schottky diode. The resulting dead time depends on the mosfets used and on the cur-
rent flowing in the inductor; in this way many kinds of mosfets may be used and cross conduction is avoided.PS K R SENSE---- ------------------I OUT V OUT 1 V OUTIN
---------------–⋅⋅ ⋅ ⋅=
11/26
L5994 - L5994A
ProtectionsEach converter is fully protected against fault conditions. A monitoring system checks for overvoltages of the
output, quickly disabling the interested converter in case such an event occurs. This condition is latched and to
allow the device to start again either the supply voltages have to be removed or the relative RUNx pin has to be
driven low.
Also the undervoltage conditions are detected: a light undervoltage (90% of the programmed value) only causes
the relative PWROKx to be driven low while an hard undervolatge (70% of the programmed value) causes in-
terruption of the operation of both converters. This is a protection against short circuits.
PWROKx signals (at pin 10 and 23) reveals the anomaly of the relative section (output voltage not within the
±10% of the programmed voltage) with a low output level. If the chip overheats (above 135°C typ.) the device
stops operating as long as the temperature falls below a safe value (105°C typ.). The overtemperature condition
is signalled by a low level on both PWROKx as well.
A current limitation comparator prevents from excessive current in case of overload. It intervenes as the voltage
VRSENSE exceeds 50mV, turning off the high-side switch before the error summing does. By the way, this also
gives the designer the ability to program the maximum operating current by selecting an appropriate sense re-
sistor. This pulse-by-pulse limitation gives a quasi-constant current characteristic.
Linear DriverThe Linear driver is capable of sinking up to 60mA from an external PNP transistor through the pin VDRLIN
considering the typical application circuit shown in fig. 4. The internal comparator is supplied by the same pin
VDRLIN which accepts voltages included in the range from 4.5V to 20V. If the application works with input volt-
ages that allows the regulation, the supply for the regulator can be obtained directly from the input source (VIN).
If such is not the case and is not available an additional input voltage, the most convenient way to get the supply
is to use an auxiliary winding on one of the two sections inductor with a catch diode, DS, and a filter capacitor,
CS, as shown in fig. 5. This winding delivers energy to pin VDRLIN during the recirculation period of each switch-
ing cycle with a voltage determined by the turns ratio n and little dependent on the input voltage.
Figure 4. Linear regulator supply with auxiliary windingIn case the section with the auxiliary winding is working at full load and the linear regulator is lightly loaded, the
voltage at pin VDRLIN can exceed the expected value. In fact, DS and CS act as a peak-holding circuit and
VDRLIN is influenced by the voltage spikes at switching transients. An internal clamp limits the voltage on the
VDRLIN pin at a maximum value of 16V, but, in case of intervention, the chip power dissipation will rise.The
linear driver is always active as long as PREG5 and VREF are present on the chip (see the relevant section); it
L5994 - L5994A12/26
works in order to obtain a voltage on the VFBLIN pin of about 2.5V. In this way, the minimum regulated voltage
is of 2.5V, obtained connecting directly the VFBLIN pin to the output, while the maximum is of about the supply
voltage minus the bipolar PNP VceSAT.
For a correct operation of the regulator, the voltage at pin VDRLIN must not be too low. The flyback connection
of the two windings ensures a well regulated voltage, provided if there is good magnetic coupling. The coupled
inductors configuration, however, is not able to sustain the auxiliary voltage if the main output is lightly loaded:
the secondary voltage drops and the system goes out of regulation.
The additional winding may be implemented with L5994 if the relative section is loaded enough.
To overcome this problem, in L5994A, when the VDRLIN voltage falls below a certain threshold (13.7V ±5%)
because of too light a load on the section 2, the relevant synchronous rectifier is turned on for 1.5 μs max. during
the interval in which the inductor current is zero ("one-shot" feature, see fig. 6). In this way, the inductor current
reverses and draws from the output capacitor energy which is forward transferred to the auxiliary output.
Since that the linear driver is supplied from the VDRLIN pin, if the linear regulator is not necessary for the application,
leave floating this pin implies that the linear driver is not supplied and so no power is wasted (L5994 only).
The linear regulator is active, if at the least one of the two runx signal is asserted
Figure 5. "One Shot" pulse to substain VDRLIN voltage
+5V Linear Regulator and +2.5V Reference Voltage GeneratorThe 5V low drop-out regulator powers directly the MOSFET drivers and it is externally available through pin
PREG5. A low pass filter is connected between PREG5 pin and SREG5 pin from who all the internal circuitry is
powered. The introduction of this R-C network is useful to minimize noise effects.
The typical external use of this generator is to charge the bootstrap capacitors used to produce the gate-drive
voltage for the high-side MOSFET's of both PWM converters.
At start-up and when the 5V section is not operating, this regulator is powered by the chip input voltage. To re-
duce power consumption, the linear regulator is turned off and the PREG5 pin is internally connected to the 5V
PWM regulator output via V5SW pin, when the 5V PWM regulator is active and its output voltage is above the
switchover threshold, 4.5V. This happens when V5SW pin is connected to the section 1 output regulating 5V.
In any case, if V5SW is above 4.5V, the internal regulator is turned off and PREG5 is powered through this pin.
13/26
L5994 - L5994AThe 5V regulator is always active, even if both PWM regulators are disabled, as long as power is applied to the
chip.
The 2.5V reference voltage generator, provides comparison levels for threshold detection and device operation.
It is allowed to source up to 5mA to an external load from its buffered output, externally available through pin
VREF.
The reference voltage generator is active if at least one of the two RUNx signal is asserted.
If either PREG5 or VREF does not deliver the correct voltage, the device is shut down.
Figure 6. Controlled timing sequencies
