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L4975A-L4975A.
5A SWITCHING REGULATOR
L4975A5A SWITCHING REGULATOR
5A OUTPUT CURRENT
5.1V TO 40V OUTPUT VOLTAGE RANGE
0 TO 90% DUTY CYCLE RANGE
INTERNAL FEED-FORWARD LINE REGULA-
TION
INTERNAL CURRENT LIMITING
PRECISE 5.1V ± 2% ON CHIP REFERENCE
RESET AND POWER FAIL FUNCTIONS
SOFT START
INPUT/OUTPUT SYNC PIN
UNDER VOLTAGE LOCK OUT WITH HYS-
TERETIC TURN-ON
PWM LATCH FOR SINGLE PULSE PER PE-
RIOD
VERY HIGH EFFICIENCY
SWITCHING FREQUENCY UP TO 500KHz
THERMAL SHUTDOWN
CONTINUOUS MODE OPERATION
DESCRIPTIONThe L4975A is a stepdown monolithic power
switching regulator delivering 5A at a voltage vari-
able from 5.1 to 40V.
Realized with BCD mixed technology, the device
uses a DMOS output transistor to obtain very high
efficiency and very fast switching times. Features
of the L4975A include reset and power fail for mi-
croprocessors, feed forward line regulation, soft
start, limiting current and thermal protection. The
device is mounted in a 15-lead multiwatt plastic
power package and requires few external compo-
nents. Efficient operation at switching frequencies
up to 500KHz allows reduction in the size and
cost of external filter components.
BLOCK DIAGRAM
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
L4975A
CIRCUIT OPERATION (refer to the block dia-
gram)
The L4975A is a 5A monolithic stepdown switching
regulator working in continuous mode realized in
the new BCD Technology. This technology allows
the integration of isolated vertical DMOS power
transistors plus mixed CMOS/Bipolar transistors.
The device can deliver 5A at an output voltage
adjustable from 5.1V to 40V, and contains diag-
nostic and control functions that make it particu-
larly suitable for microprocessor based systems.
BLOCK DIAGRAMThe block diagram shows the DMOS power tran-
sistor and the PWM control loop. Integrated func-
tions include a reference voltage trimmed to 5.1V± 2%, soft start, undervoltage lockout, oscillator
with feedforward control, pulse by pulse current
limit, thermal shutdown and finally the reset and
power fail circuit. The reset and power fail circuit
provides an output signal for a microprocessor in-
dicating the status of the system.
Device turn on is around 11V with a typical 1V
hysteresis, this threshold provides a correct volt-
age for the driving stage of the DMOS gate and
the hysteresis prevents instabilities.
An external bootstrap capacitor charged to 12V
by an internal voltage reference is needed to pro-
vide correct gate drive to the power DMOS. The
driving circuit is able to source and sink peak cur-
rents of around 0.5A to the gate of the DMOS
transistor. A typical switching time of the current
in the DMOS transistor is 50ns. Due to the fast
commutation switching frequencies up to 500kHz
are possible.
The PWM control loop consists of a sawtooth os-
cillator, error amplifier, comparator, latch and the
output stage. An error signal is produced by com-
paring the output voltage with the precise 5.1V ±
2% on chip reference. This error signal is then
compared with the sawtooth oscillator, in order to
generate a fixed frequency pulse width modulated
drive for the output stage. A PWM latch is in-
cluded to eliminate multiple pulsing within a pe-
riod even in noisy environments. The gain and
PIN FUNCTIONS
L4975A3/21
Figure 1: Feedforward Waveform
Figure 3: Limiting Current Function
Figure 2: Soft Start Function
L4975A
stability of the loop can be adjusted by an exter-
nal RC network connected to the output of the er-
ror amplifier. A voltage feedforward control has
been added to the oscillator, this maintains supe-
rior line regulation over a wide input voltage
range. Closing the loop directly gives an output
voltage of 5.1V, higher voltages are obtained by
inserting a voltage divider.
At turn on output overcurrents are prevented by
the soft start function (fig. 2). The error amplifier is
initially clamped by an external capacitor Css and
allowed to rise linearly under the charge of an in-
ternal constant current source.
Output overload protection is provided by a cur-
rent limit circuit (fig. 3). The load current is sensed
by an internal metal resistor connected to a com-
parator. When the load current exceeds a preset
threshold the output of the comparator sets a flip
flop which turns off the power DMOS. The next
clock pulse, from an internal 40kHz oscillator will
reset the flip flop and the power DMOS will again
conduct. This current protection method, ensures
a constant current output when the system is
overloaded or short circuited and limits the
switching frequency, in this condition, to 40kHz.
The Reset and Power fail circuitry (fig 4) gener-
ates an output signal when the supply voltage ex-
ceeds a threshold programmed by an external
voltage divider. The reset signal, is generated
with a delay time programmed by an external ca-
pacitor on the delay pin. When the supply voltage
falls below the threshold or the output voltage
goes below 5V the reset output goes low immedi-
ately. The reset output is an open collector-drain.
Fig 4A shows the case when the supply voltage is
higher than the threshold, but the output voltage
is not yet 5V.
Fig 4B shows the case when the output is 5.1V
but the supply voltage is not yet higher than the
fixed threshold.
The thermal protection disables circuit operation
when the junction temperature reaches about
150°C and has an hysterysis to prevent unstable
conditions.
Figure 4: Reset and Power Fail Functions.
L4975A5/21
