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CHL8325A-IR3541MTRPBF
Dual Loop, 4+1 multiphase VR12/AMD PWM controller for high efficiency, highly accurate VR solutions
International
TOR Rectifier
Digital Multi-Phase Buck Controller
|R3541
GHL8325A/B
FEATURES
5-phase dual output PWM Controller
Phases are flexibly assigned between Loops 1 & 2
Intel© VR12, AMDo 400kHz & 3.4MHz SVI and
Memory modes
Dual OCP support for I-spike enhanced AMD CPUs
SMB_A|ert Pin for Servers
PMBus Address pin or Variable Gate Drive
(IR3541/CH L8325A)
2nd Temperature Sense for VR12 Desktop
(CHL8325B)
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per
IR Efficiency Shaping Features including Variable
Gate Drive (IR3541/CHL8325A only) and Dynamic
Phase Control
Programmable l-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
IR Ada ptive Transient Algorithm (ATA) on both
loops minimizes output bulk capacitors and
system cost
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP,
OTP, CFP
|2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
Non-Volatile Memory (NVM) for custom
configuration
Compatible with IR ATL and 3.3V Tri-state Drivers
+3.3V supply voltage; -209C to 859C ambient
operation
Pb-Free, RoHS, 6x6 40-pin QFN, MSL2 package
APPLICATIONS
Intel © VR12 & AMDo SVI based systems
DDR Memory with Vtt tracking
Overclocked & Gaming platforms
DESCRIPTION
The IR3541 and CHL8325A/B are dual-loop digital
multi-phase buck controllers that drive up to 5 phases.
The IR3541 and CHL8325A/B are fully Intelo VR12 and AMD'
SVI compliant on both loops and provides a Vtt tracking
function for DDR memory.
NVM storage saves pins and enables a small package size.
The IR3541 and CHL8325A/B include the IR Efficiency
Shaping Technology to deliver exceptional efficiency at
minimum cost across the entire load range. IR Variable Gate
Drive optimizes the MOSFET gate drive voltage as a function
of real-time load current. IR Dynamic Phase Control
adds/drops active phases based upon load current.
The IR3541 and CHL8325A/B can be configured to enter
l-phase operation and active diode emulation mode
automatically or by command.
IR's unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
The |2C/PMBus interface can communicate with up to 16
IR3541 and CHL8325A/B based VR loops. Device
configuration and fault parameters are easily defined using
the IR Intuitive Power Designer (DPDC) GUI and stored in
on-chip NVM.
The IR3541 and CHL8325A/B also include numerous
features like register diagnostics for fast design cycles and
platform differentiation, truly simplifying VRD design and
enabling fastest time-to-market with its "set-and-forget"
methodology.
PIN DIAGRAM
IR3541
40 Pin 6x6 QFN
Top View
sv ALEHI‘ ’VHXEN‘
sv ClK‘ JSVC‘
SVADTCI‘ JSVD“
SMBJLER
5MB DiO
VAKGATEJMJDDR
Figure 1: IR3541 Package Top View
il June 21,2013 I FINAL I v1.09
International
TOR Rectifier
Digital Multi-Phase Buck Controller
|R3541
GHL8325A/B
ORDERING INFORMATION
IR3541M DUUDDDUT
CHL8325
v'RjEADv‘I
PWRGD‘
ijEADv LL',
IPWR'DK'
Figure 2:
- P/PBF - Lead Free
TR -Tape & Reel /TY - Tray
yy - Configuration File ID
xx - Customer ID
Package Type (QFN)
T-Tape & Reel /TY - Tray
R - Package Type (QFN)
C - Operating Temperature,
Commercial
xx - Configuration File
A:CHL8325A
B:CHL8328B
40 Pin 6x6 QFN
/sercc
IR3541
'/RTN_L2
. ry 5
Top View WM
Ci. PWM4
SVAALERT' IVFIXEN‘
SV_CLK‘ Ist 3
VR_Horx'r
vnuomcnmr‘
SMB ALERTtt :5
SMBACLK ::
Snglo‘ Isvoz
VAR_GATE PM ADDR
IR3541 Package Top View, Enlarged
Packin
HERE 5 (hmmmm mmmmma
TR=3000 IR3541MTRPBF
QFN Default
TY=4900 IR3541MTYPBF
1 Customer
QFN TR=3000 IR3541MxxyyTRP . .
Configuration
Notes:
1. Customer Specific Configuration File, where
xx = Customer ID and yy = Configuration File
(Codes assigned by IR Marketing).
C2ilimIii2qg
QFN T=3000 CHL8325A-00CRT
TY=4900 CHL8325A-00cRTY
QFN T=3000 CHLg325A-xxcRT1
QFN T=3000 CHL83253-00CRT
TY=4900 CHL83258-00CRTY
QFN T=3000 CHt.8325B-xxcRT1
Notes:
I. "xx" indicates a customer specific configuration
VHJEADLU‘ /
PWRG 2
EADY Lal -
IPWRDK2 -
CHL8325A/B
40 Pin 6x6 QFN
Top View
f, RUSP_L2
V RUSM_L2
_ VSEN_L2
_ VRTN_L2
_ PWM5
- PWM4
_ PWM3
_ PWM2
_ PWMI
VINSEN ‘ ‘
VR HOT”Y /
VHHOT ICHIT”2
sv DIo‘/svn2
SV CLK' / SVCz
SV_ALERT‘ IVFIXENZ
ENABLE
(CHLBBZSA)
SMB DIO
TSENZ (CHLBSZSE)
SMB CLK
SMB ALERT!
VARgGATE FM ADDR
Figure 3: CHL8325A/B Package Top View, Enlarged
June 21,2013 I FINAL I V1.09
