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IR2110STRPBF-IR2113STRPBF
High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down
Data Sheet No. PD60147 Rev.T
International
Titait, Rectifier |R2110(S)IIR2113(S) &(PbF)
HIGH AND LOW SIDE DRIVER
Features Product Summary
. Floating channel designed for bootstrap operation
Fully operational to +500V or +600V VOFFSET (IR21 10) 500V max.
Tolerant to negative transient voltage (IR21 13) 600V max.
dV/dt immune
. Gate drive supply range from 10 to 20V kye/- 2A / 2A
. Undervoltage lockout for both channels
. 3.3V logic compatible VOUT 10 - 20V
Separate logic supply range from 3.3V to 20V
Logic and power ground 15V offset ton/off (typ.) 120 & 94 ns
. CMOS Schmitt-trlggered inputs with pull-down Delay Matching (IR2110) 10 ns max.
. Cycle by cycle edge-triggered shutdown logic
. Matched propagation delay for both channels
. Outputs in phase with inputs
. Also available LEAD-FREE
(IR2113) 20ns max.
Packages
Description
The lR2110/lR2113 are high voltage, high speed power MOSFET and
IGBT drivers with independent high and low side referenced output
channels. Proprietary HVIC and latch immune CMOS technologies 14-Lead PDIP m126/ghsf)(is
. . . . . . lR2110/lR2113
enable ruggedized monolithic construction. Logic inputs are compat-
ible with standard CMOS or LSTTL output, down to 3.3V logic. The
output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propaga-
tion delays are matched to simplify use in high frequency applications. The floating channel can be used to drive
an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.
Typical Connection up to 500V or 600V
(Referto Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
1
International
TOR Rectifier
IR2'110(S)llR2113(S) &(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol Definition Min. Max. Units
VB High side floating supply voltage (IR2110) -0.3 525
(IR2113) -0.3 625
Vs High side floating supply offset voltage VB - 25 VB + 0.3
VH0 High side floating output voltage Vs - 0.3 VB + 0.3
Vcc Low side foted supply voltage -0.3 25 V
VL0 Low side output voltage -0.3 VCC + 0.3
VDD Logic supply voltage -0.3 Vss + 25
Vss Logic supply offset voltage VCC - 25 Vcc + 0.3
VIN Logic input voltage (HIN, LIN & SD) Vss - 0.3 VDD + 0.3
dl/s/dt Allowable offset supply voltage transient (rsgure 2) - 50 V/ns
PD Package power dissipation @ TA S +25°C (14 lead DIP) - 1.6 W
(16 lead SOIC) - 1.25
RTHJA Thermal resistance, junction to ambient (14 lead DIP) - 75 o
(16 lead SOIC) - 100 CM,
TJ Junction temperature - 150
Ts Storage temperature -55 150 "C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure I. For proper operation the device should be used within the
recommended conditions. The vs and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 36 and 37.
Symbol Definition Min. Max. Units
VB High side floating supply absolute voltage Vs + 10 Vs + 20
Vs High side floating supply offset voltage (IR2110) Note 1 500
(IR2113) Note 1 600
VH0 High side floating output voltage Vs V3
Vcc Low side fixed supply voltage 10 20 V
VLo Low side output voltage 0 VCC
VDD Logic supply voltage vss + 3 Vss + 20
l/ss Logic supply offset voltage -5 (Note 2) 5
VIN Logic input voltage (HIN, LIN & SD) I/ss VDD
TA Ambient temperature -40 125 "C
Note 1: Logic operational for Vs of -4 to +500V. Logic state held for Vs of -4V to A/BS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When VDD < 5V, the minimum vss offset is limited to A/DD.
