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IP1001IORN/a79avaiFull Function Synchronous Buck Power Block
IP1001IRN/a2879avaiFull Function Synchronous Buck Power Block


IP1001 ,Full Function Synchronous Buck Power BlockBlock DiagramV VIN IND0 D0D1 D15 B 5 Biit t D2 D2DA DAC CD3 D3V VSW SWPW PWM M D4 D4& D & Dr riiv ..
IP1001 ,Full Function Synchronous Buck Power BlockElectrical Specifications @ V = 5V & T 0°C - 90°C (Unless otherwise specified)DD PCBParameter Symbo ..
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IRFW624B ,250V N-Channel MOSFETFeaturesThese N-Channel enhancement mode power field effect • 4.1A, 250V, R = 1.1Ω @V = 10 VDS(on) ..
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IP1001
Full Function Synchronous Buck Power Block
PD - 94336c
International
ISER Rectifier iP1001
tPal/lm"' Full Function Synchronous Buck Power Block
TECHNOLOGY Integrated Power Semiconductors, Control IC & Passives
Features
. 3.3V to 12V input voltage©
. 20A maximum load capability, with no derating up to TPCB
. 5 bit DAC settable, 0.925V to 2V output voltage range C)
. Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit ©
. 200kHz or 300kHz nominal switching frequency
. Optimized for very low power losses
. Over & undervoltage protection
. Adjustable lossless current limit
. Internal features minimize layout sensitivity *
. Very small outline 14mm x 14mm x 3mm iP1001 Power Block
= 90°C
Description
The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.
The iP1001 is optimized for single-phase applications, and includes a full function fast transient response
PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark
power density. Very few external components are required, including output inductor, input & output capacitors.
Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and
operation up to 3.3Vout can be achieved with a simple external voltage divider.
iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers
benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,
heat transfer and component selection.
iP1001 Internal Block Diagram
& Driver
L - - - - --.-
SGND GNDS st v, PGND
. Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be
applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, ifoperated as specified. The
iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable
and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.
05/20/03 1
iP1001
All specifications @ 25°C (unless otherwise specified)
International
TOR Rectifier
Absolute Maximum Ratings
Parameter
V.N to PGND
Vor, to PGND
PGOOD to PGND
ENABLE to PGND
RMS Current
Block Tem re
Recommended Operating Conditions
Conditions
Parameter Symbol Min Typ Max Units Conditions
Supply Voltage VDD 4.5 - 5.5 V
Input Voltage Range co Mr: 3.3 - 12 With 4.5VOutput RMS Current from Vsw © loutvsw - - 20 A
DAC Setting
Output Voltage Range © VOUT 0.925 - 2.0 V see VID code. Table1.
Electrical Specifications © Va, = 5V & TPCB 0°C - 90°C (Unless otherwise specified)
Parameter Symbol Min Typ Max Units Conditions
Power Loss PLoss - 3.1 3.9 W 300kHz, 12V.N, 1.3Vout, 20A
v.N=12v, Vour--1.3V,
Over Current Shutdown - 25 - A FREQ=300KHz, RL.M=340k
Soft Start Time - 1.8 - ms
All DAC codes
Output Voltage Accuracy -2 - 2 % TBLK = 40°C to 125°C
VF Input Resistance - 181 - kn
- 200 - freq pin connected to VDD
F n FRE
reque Cy Q - 300 - kHz freq pin floating
Va, Undervoltage Lockout - 4.2 - V 200mV hysteresis
Output Undervoltage Shutdown 0 8 V
Threshold _ . -
Output Undervoltage Protection _ .
Blanking Time - 20 - ms ENABLE gang high on start-up
Output Overvoltage Shutdown 2 25 V See OVP note in Design
Threshold at Vs - . - Guidelines
PGOOD Trip Threshold PGOOD - VDAC -5% - V At (
PGOOD output high
PGOOD Leakage Current - 1 - pA Forced to 5.5V
PGOOD Output Low Voltage - - 0.4 V [m = 1mA
Logic Input High Voltage 2.4 - - V D0-D4, Enable
Logic Input Low Voltage - - 0.8 V DO-D4, Enable
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