IMSC011-P20S ,Link adaptor, 10 or 20 Mbits/sec operating speedFEATURES Standard INMOS link protocol 10 or 20 Mbits/sec operating speed Communicates with trans ..
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IMSC011-E20S-IMSC011-P20S
Link adaptor
Link adaptor
IMS C011)
FEATURES
APPLICATIONS Standard INMOS link protocol 10or20 Mbits/sec operating speed Communicates with transputers Converts between serial link and parallel bus Converts between serial link and parallel device Two modesof parallel operation:
Mode1: Peripheral interfaceEightbit parallel input interface
Eightbit parallel output interface
Full handshakeon input and output
Mode2: Bus interfaceTristate bidirectional bus interface
Memory mapped registers
Interrupt capability Single +5V 5% power supply TTL and CMOS compatibility 120mW power dissipation 28 pin 0.6” plastic package 28 pin SOJ package 28 pin LCCC package Extended temperature version available Programmable I/O for transputer Connecting microprocessorsto transputers High speed links between microprocessors Inter-family microprocessor interfacing Interconnecting different speed links
Input
InterfaceSystem
Services
Output
Interface
Link
Mode1
Mode2
Interrupt
Control
System
Services
Data and
Status
RegistersLink
Register
Select
Contents
Introduction 3.... .... ... ... ...... .......... .... ... ....... ... ... .... Pin designations 4.... ... ... ...... .... ...... .... ... ... .... .......... System services 5.... ... ... ...... .... ...... .... ... ... .... ..........3.1 Power 5......... ......... ... ........ ....... .............. ........ ....... ....
3.2 CapMinus 5.... ....... ............. ........ ....... ...... ........ ....... .....
3.3 ClockIn 5...... ........ ....... .................. ......... ....... .............
3.4 SeparateIQ 6.. ........ ........ ............ .............. ....... ....... ......
3.5 Reset 7......... ......... ... ........ ....... .............. ........ ....... ....
Links 9.. ... ... ................ .... ... ... .... ......... .............. Mode1 parallel interface 12... ...... .... ...... .... ... ... ..............5.1 Input port 12..... ........ ............ ........ ....... ...... ........ ....... .....
5.2 Output port 13.. ........ ........ ............ .............. ....... ....... ......
Mode2 parallel interface 14... ...... .... ...... .... ... ... ..............6.1 D0–7 14........ ........ ........ ............ .............. ........ ...... ......
6.2 notCS 14......... ......... ... ........ ....... .............. ........ ....... ....
6.3 RnotW 14...... ........ ....... .................. ......... ....... .............
6.4 RS0–1 14...... ........ ....... .................. ......... ....... .............
6.5 InputInt 17...... ........ ....... .................. ......... ....... .............
6.6 OutputInt 18..... ........ ............ ........ ....... ...... ........ ....... .....
6.7 Data read 18..... ........ ............ ........ ....... ...... ........ ....... .....
6.8 Data write 18.... ....... ............. ........ ....... ...... ........ ....... .....
Electrical specifications 19... ...... .... ...... .... ... ... ..............7.1 DC electrical characteristics 19.. ........ ....... ....... ...... ........ ....... .....
7.2 Equivalent circuits 20... ........ ........ .......................................
7.3 AC timing characteristics 21..... ....... ....... .............. ........ ....... ....
7.4 Power rating 23........ ........ ....... ..................... ........ ....... ....
Package details 24.............. .... ... ....... ... ... ... ..............8.1 Package pinouts 24..... ........ ........ ........... ........................ ....
8.2 28-pin plastic DIL package dimensions 25.................................... ....
8.3 28-pin SOJ package dimensions 26..... ........ ....... ...... ........ ....... .....
8.4 28-pin LCCC package dimensions 27... ........ ....... ...... ........ ....... .....
8.5 Thermal specification 28........ ........ .......................................
Ordering 29.. ...... .... ... ... ...... .......... .... ... ... .... ..........
IntroductionThe INMOScommunication linkisa high speed system interconnect which providesfull duplex communi-
cation between membersof the transputer family, accordingto the INMOS serial link protocol. The
IMS C011,a memberof this family, providesfor full duplex transputer link communication with standard
microprocessor and sub-system architectures,by converting bi-directional serial link data into parallel
data streams.
Alltransputer products which use communicationlinks, regardlessof devicetype, support astandard com-
munications frequencyof10 Mbits/sec; most products also support20 Mbits/sec. Productsof different
typeor performancecan, therefore, beinterconnecteddirectly andfuturesystems willbe ableto communi-
cate directly with thoseof today. The IMS C011link will runat either the standard speedof 10 Mbits/secat the higher speedof20 Mbits/sec. Data receptionis asynchronous, allowing communicationtobein-
dependentof clock phase.
The link adaptor canbe operatedin oneof two modes.In Mode1 the IMS C011 converts betweena link
and two independent fully handshaken byte-wide interfaces, one input and one output.It canbe usedby peripheral deviceto communicate witha transputer,a peripheral processoror another link adaptor,or can provide programmable input and output pinsfora transputer. Two IMS C011 devicesin this mode
canbe connected backto back via the parallel ports and usedasa frequency changer between different
speed links. Mode2 the IMS C011providesan interfacebetweenan INMOS seriallink anda microprocessor system
bus. Status and data registers for both input and output ports can be accessed across the byte-wide
bi-directional interface. Two interrupt outputs are provided, oneto indicate input data available and one
for output buffer empty.
Input
Interface
Output
Interface
System
Services
Link Q0–7
Qack
QValid
I0–7
IAck
IValid
VDD
GND
CapMinus
ClockIn
Reset
SeparateIQ
LinkOut
LinkIn
Figure 1.1 IMS C011 Mode1 block diagram
Interrupt
Control
Data and
Status
Registers
System
Services
Link 8 D0–7
InputInt
OutputInt
VDD
GND
CapMinus
ClockIn
Reset
SeparateIQ
LinkOut
LinkIn
Register
Select
LinkSpeed
RS0
RS1
RnotW
notCS
IMS C011 Pin designations
Signal names are prefixedby notif they are active low, otherwise they are active high.
Pinout details for various packages are givenon page 24.
Pin In/Out Function
VDD, GND Power supply and return
CapMinus External capacitor for internal clock power supply
ClockIn in Input clock
Reset in System reset
SeparateIQ in Select mode and Mode1 link speed
LinkIn in Serial data input channel
LinkOut out Serial data output channel
Table 2.1 Services and link
Pin In/Out Function
I0-7 in Parallel input bus
IValid in Data on I0-7is valid
IAck out Acknowledge I0-7 data receivedby other link
Q0-7 out Parallel output bus
QValid out Data on Q0-7is valid
QAck in Acknowledge from device: data Q0-7 was read
Table 2.2 Mode1 parallel interface
Pin In/Out Function
D0-7 in/out Bi-directional data bus
notCS in Chip select
RS0-1 in Register select
RnotW in Read/write control signal
InputInt out Interrupt on link receive buffer full
OutputInt out Interrupt on link transmit buffer empty
LinkSpeed in Select link speedas10or 20 Mbits/sec
HoldToGND Mustbe connectedto GND
DoNotWire Must notbe wired
Table 2.3 Mode2 parallel interface
System services System servicesSystem services includeall the necessary logicto startup and maintain the IMS C011.
3.1 Power
Poweris suppliedto the device via the VDD and GND pins. The supply mustbe decoupled closeto the
chipbyat least one 100nF low inductance (e.g. ceramic) capacitor between VDD and GND. Four layer
boards are recommended;if two layer boards are used, extra care should be takenin decoupling. noise between VDD and GND mustbe kept below 200 mV peakto peakatall frequencies above
100 KHz. AC noise between VDD and the ground referenceof load capacitances mustbe kept below
200 mV peakto peakatall frequencies above30 MHz. Input voltages must not exceed specificationwith
respectto VDD and GND, even during power-up and power-downramping, otherwise latchup can occur.
CMOS devices canbe permanently damagedby excessive periodsof latchup.
3.2 CapMinus
The internally derived power supply for internal clocks requiresan external low leakage, low inductance
1F capacitortobe connected between VDD and CapMinus.A ceramic capacitoris preferred, withan
impedance less than3 Ohms between100 KHz and10 MHz.Ifa polarisedcapacitoris used the negative
terminal shouldbe connectedto CapMinus. Total PCB track lengthshouldbe less than50 mm. Theposi-
tive connectionof the capacitor mustbe connected directly toVDD. Connectionsmust nototherwise touch
power suppliesor other noise sources.
Phase–locked
loops
VDD
GND
CapMinus P.C.B track
P.C.B track
Decoupling
capacitor1F
pin
VDD
Figure 3.1 Recommended PLL decoupling
3.3 ClockIn
Transputerfamily components usea standardclock frequency,suppliedby the useron the ClockIn input.
The nominal frequencyof this clock forall transputer family componentsis5 MHz, regardlessof device
type, transputer word lengthor processor cycle time. High frequency internal clocks are derived from
ClockIn, simplifying system design and avoiding problemsof distributing high speed clocks externally. numberoftransputer family devicesmaybeconnectedto acommon clock,or may have individualclocks
providing each one meets the specified stability criteria.Ina multi-clock system the relative phasingof
ClockIn clocksis not important, dueto the asynchronous natureof the links.Mark/space ratiois unimpor-
tant provided the specified limitsof ClockIn pulse widths are met.
IMS C011
Symbol Parameter Min Nom Max Units Notes
TDCLDCH ClockIn pulse width low 40 ns 1
TDCHDCL ClockIn pulse width high 40 ns 1
TDCLDCL ClockIn period 200 ns 1,2,4
TDCerror ClockIn timing error 0.5 ns 1,3
TDC1DC2 Differencein ClockInfor2 linked devices 400 ppm 1,4
TDCr ClockIn rise time 10 ns 1,5
TDCf ClockIn fall time 8 ns 1,5
Notes Guaranteed, but not tested. Measured between corresponding pointson consecutive falling edges. Variationof individual falling edges from their nominal times. This value allows the useof 200ppm crystal oscillatorsfor two devices connected togetherby link. Clock transitions mustbe monotonic within the range VIHto VIL (table 7.3).
Table 3.1 Input clock
90%
10%
TDCr
2.0V
0.8V
1.5V
TDCerror
TDCerror
TDCerror
TDCerror
TDCLDCH TDCHDCL
TDCLDCL
TDCf
90%
10%
Figure 3.2 ClockIn timing
3.4 SeparateIQ
The IMS C011 link adaptor has two different modesof operation. Mode1is basicallya linkto peripheral
adaptor, whilst Mode2 interfaces betweena link anda microprocessor bus system.
Mode1 canbe selected for oneof two link speedsby connecting SeparateIQto VDD (10 Mbits/sec)or ClockIn (20 Mbits/sec).
Mode2is selectedby connecting SeparateIQto GND;in this mode10 Mbits/secor20 Mbits/secis se-
lectedby LinkSpeed. Link speeds are specified fora ClockIn frequencyof5 MHz.
System servicesthe device.If ClockInis gatedto achieve this,its skew mustbe limitedto the value TDCHSIQH shown table 3.3. The modeof operation (Mode1, Mode2) must notbe changed dynamically.
SeparateIQ Mode Link Speed Mbits/sec
VDD 110
ClockIn 120
GND 210or20
Table 3.2 SeparateIQ mode selection
Symbol Parameter Min Nom Max Units Notes
TDCHSIQH Skew from ClockInto ClockIn 20 ns 1
Notes Skew between ClockIn arriving on the ClockIn pin andon the SeparateIQ pin.
Table 3.3 SeparateIQ
3.5 Reset
The Reset pin cango high with VDD, but mustatno time exceed the maximum specified voltagefor VIH.
After VDDis valid ClockIn shouldbe runningfora minimum period TDCVRL before the endof Reset.All
inputs, with the exceptionof ClockIn and SeparateIQ (plus LinkSpeedin mode2), mustbe heldin their
inactive state during reset.
Reset initialises the IMS C011to the following state: LinkOutis held low; the control outputs (IAck and
QValidin Mode1, InputInt and OutputIntin Mode2) are held low; interrupts (Mode2) are disabled; the
statesof Q0-7in Mode1 are unspecified; D0-7in Mode2 are high impedance.
Symbol Parameter Min Nom Max Units Notes
TPVRH Power valid before Reset 10 ms
TRHRL Reset pulse width high 8 ClockIn 1
TDCVRL ClockIn running before Reset end 10 ms 2
TRLIvH Reset low before IValid high (mode1) 0 ns
TRLCSL Reset low before chip select low (mode2) 0 ns
Notes Full periodsof ClockIn TDCLDCL required. At power-on reset.
Table 3.4 Reset
IMS C011
ClockIn
VDD
Reset
TRLIvH
TRHRLTPVRH
TDCVRL
TRLCSL
IValid
notCS
Figure 3.3 Reset timing
Links LinksINMOS bi-directional serial links provide synchronized communication between transputer productsand
with the outside world. Each link comprisesan input channel and output channel.A link between two de-
vicesis implementedby connectinga link interfaceon one devicetoa link interfaceon the other device.
Every byteof data sent ona linkis acknowledgedon theinputof the samelink, thus eachsignal line carries
both data and control information.
The quiescent stateofa link outputis low. Each data byteis transmittedasa high startbit followedbya
onebit followedby eight data bits followedbya low stop bit. The least significantbitof datais transmitted
first. After transmittinga data byte the sender waitsfor the acknowledge, which consistsofa high startbit
followedbya zero bit. The acknowledge signifies both thata process was ableto receive the acknowl-
edged data byte and that the receiving linkis ableto receive another byte.
Links are not synchronised with ClockIn and are insensitivetoits phase. Thus links from independently
clocked systemsmay communicate, providing only that the clocks arenominally identicaland withinspeci-
fication.
Links are TTL compatible and intendedtobe usedin electrically quiet environments, between deviceson singleprinted circuit boardor between two boardsviaa backplane. Direct connection maybe made be-
tween devices separatedbya distanceof less than 300 millimetres. For longer distancesa matched
100 ohm transmission line shouldbe used with series matching resistors RM. When thisis done the line
delay shouldbe less than 0.4bit timeto ensure that the reflection returns before the next databitis sent.
Buffers maybe used for very long transmissions.If so, their overall propagation delay shouldbe stable
within the skew toleranceof the link, although the absolute valueof the delayis immaterial.
The IMS C011 link supports the standard INMOS communication speed of10 Mbits/sec.In additionit can usedat20 Mbits/sec. Link speedcanbe selectedin oneof two ways.In Mode1itis altered bySepara-
teIQ (page 6).In Mode2itis selectedby LinkSpeed; when the LinkSpeed pinis low, the link operates the standard10 Mbits/sec; when highit operatesat20 Mbits/sec.
012 3 4 5 6 7
Data Ack L LH
Figure 4.1 IMS C011 link data and acknowledge packets
IMS C011
Symbol Parameter Min Nom Max Units Notes
TJQr LinkOut rise time 20 ns 1
TJQf LinkOut fall time 10 ns 1
TJDr LinkIn rise time 20 ns 1
TJDf LinkIn fall time 20 ns 1
TJQJD Buffered edge delay 0 ns
TJBskew Variationin TJQJD 20 Mbits/s 3 ns 2 Mbits/s 10 ns 2
CLIZ LinkIn capacitance @ f=1MHz 7 pF 1
CLL LinkOut load capacitance 50 pF Series resistorfor 100� transmission line 56 ohms
Notes Guaranteed, but not tested. Thisis the variationin the total delay through buffers, transmission lines, differential receivers
etc., causedby such thingsas short term variationin supply voltages and differencesin delays
for rising and falling edges.
Table 4.1 Link
TJQf
90%
10%
TJQr
TJDf
90%
10%
TJDr
LinkOut
LinkIn
Figure 4.2 IMS C011 link timing
1.5V
Latest TJQJD
LinkOut
LinkIn 1.5V
TJBskew
Earliest TJQJD
LinksLinkOut
LinkIn
LinkIn
LinkOut
Transputer family deviceB
Transputer family deviceA
Figure 4.4 Links directly connected
LinkOut
LinkIn
LinkIn
LinkOut
Transputer family deviceB
Transputer family deviceAZo=100 ohms
Zo=100 ohms
Figure 4.5 Links connectedby transmission line
LinkOut
LinkIn
LinkIn
LinkOut
Transputer family deviceB
Transputer family deviceA
buffers
Figure 4.6 Links connectedby buffers
IMS C011 Mode1 parallel interface Mode1 the IMS C011link adaptoris configuredasa parallel peripheral interface with handshake lines.
Communication witha transputer family deviceis via the serial link. The parallel interface comprisesan
input port andan output port, both with handshake.
5.1 Input port
The eightbit parallel input port I0-7 canbe readbya transputer family devicevia the seriallink. IValid and
IAck providea simple two-wire handshakefor this port. When datais validon I0-7, IValidis taken high the peripheral deviceto commence the handshake. The link adaptor transmits data presentedon I0-7
out throughthe serial link. After thedata byte transmissionhasbeen completedandan acknowledgepack-is receivedon the input link, the IMS C011 sets IAck high.To complete the handshake, the peripheral
device must return IValid low. The link adaptor will then set IAck low. New data should notbe put onto
I0-7 until IAckis returned low.
Symbol Parameter Min Nom Max Units Notes
TIdVIvH Data setup 5 ns
TIvHLdV IValid highto link data output 0.8 2.5 bits 1,2
TLaVIaH Link acknowledge startto IAck high 3.5 bits 1,3
TIaHIdX Data hold after IAck high 0 ns
TIaHIvL IValid hold after IAck high 0 ns
TIvLIaL IAck hold after IValid low 0.8 3 bits 1
TIaLIvH Delay before next IValid high 0 ns
Notes Unitof measurementis one link databit time;at10 Mbits/s data link speed, onebit timeis nomi-
nally 100 ns. Maximum time assumes thereisno acknowledge packet alreadyon thelink. Maximum time with
acknowledgeon the linkis extendedby2 bits. Both data transmission and the returned acknowledge mustbe completed before IAck cango
high.
Table 5.1 Mode1 parallel data input
Ack
Data
TIdVIvH
TIvLIaL
TIvHLdV
LinkOut
I0–7
LinkIn
TLaVIaH
IValid
IAck
TIaHIvL TIaLIvH
TIaHIdX
Mode1 parallel interface5.2 Output port
The eightbit parallel output port Q0-7 canbe controlledbya transputer family device via the serial link.
QValid and QAck providea simple two-wire handshakefor this port. data packet receivedon the input linkis presentedon Q0-7; the link adaptor then takes QValid highto
initiate the handshake.After readingdatafrom Q0-7, theperipheral devicesets QAck high. The IMS C011
will then sendan acknowledge packet outof the serial linkto indicatea completed transaction and set
QValid lowto complete the handshake.
Symbol Parameter Min Nom Max Units Notes
TLdVQvH Startof link datato QValid 11.5 bits 1
TQdVQvH Data setup 12 ns 2
TQvHQaH QAck setup time from QValid high 0 ns
TQaHQvL QAck highto QValid low 1.8 bits 1
TQaHLaV QAck highto Ackon link 0.8 2.5 bits 1,3
TQvLQaL QAck hold after QValid low 0 ns
TQvLQdX Data hold 11 bits 1,4
Notes Unitof measurementis one link databit time;at10 Mbits/s data link speed, onebit timeis nomi-
nally 100 ns. Wherean existing data outputbitis re-written with the same level there willbeno glitchin the
output level. Maximum time assumes thereisno data packet alreadyon the link. Maximum time with dataon
the linkis extendedby11 bits. Data output remains valid until overwrittenby new data.
Table 5.2 Mode1 parallel data output
Ack
DataData
TLdVQvH
TQvHQaH
LinkIn
QValid
Q0–7
LinkOut
TQdVQvH TQvLQdX
TQaHQvL
TQvLQaL
QAck
TQaHLaV
Figure 5.2 IMS C011 Mode1 parallel data output from link adaptor
IMS C011 Mode2 parallel interface
The IMS C011 providesan interface betweena link anda microprocessor style bus. Operationof the link
adaptoris controlled through the parallelinterface bus lines D0-7by reading and writing various registers the link adaptor. Registers are selectedby RS0-1 and RnotW, and the chip enabled with notCS.
For convenienceof description, the device connectedto the parallel sideof the link adaptoris presumed bea microprocessor, although this will not alwaysbe the case.
6.1 D0–7
Datais communicated betweena microprocessor bus and the link adaptor via the bidirectional bus lines
D0-7. The busis high impedance unless the link adaptor chipis selected and the RnotW lineis high. The
busis usedby the microprocessorto access status and data registers.
6.2 notCS
The link adaptor chipis selected when notCSis low.Register selectorsRS0-1 and RnotW mustbe valid
before notCS goes low; D0-7 must alsobe validif writingto the chip (RnotW low). Datais readby the link
adaptoron the rising edgeof notCS.
6.3 RnotW
RnotW, inconjunction with notCS, selectsthe linkadaptor registersfor reador write mode. When RnotW high, the contentsofan addressed register appearon the data bus D0-7; when RnotWis low the data D0-7is written into the addressed register.The stateof RnotWis latched into the link adaptor bynotCS
going low;it may be changed before notCS returns high, within the timing restrictions given.
6.4 RS0–1
Oneof four registersis selectedby RS0-1.A registeris addressedby settingup RS0-1 and then taking
notCS low; the stateof RnotW when notCS goes low determines whether the register willbe reador writ-
ten. The stateof RS0-1is latched into the link adaptorby notCS going low;it maybe changed before
notCS returns high, within the timing restrictions given. The register set comprisesa read-only data input
register,a write-only data output register anda read/write status register for each.
RS1 RS0 RnotW Register 0 1 Read data 0 0 Invalid 1 1 Invalid 1 0 Write data 0 1 Read input status 0 0 Write input status 1 1 Read output status 1 0 Write output status
Table 6.1 IMS C011 Mode2 register selection
6.4.1 Input Data Register
This register holds the last data packet received from the serial link.It never contains acknowledge pack-
ets.It contains valid data only whilst the data present flagis setin the input status register.It cannotbe
Mode2 parallel interfaceSymbol Parameter Min Nom Max Units Notes
TRSVCSL Register select setup 5 ns
TCSLRSX Register select hold 8 ns
TRWVCSL Read/write strobe setup 5 ns
TCSLRWX Read/write strobe hold 8 ns
TCSLCSH Chip select active 60 ns
TCSHCSL Delay before re-assertionof chip select 50 ns
Table 6.2 IMS C011 Mode2 parallel interface control
Symbol Parameter Min Nom Max Units Notes
TLdVIIH Startof link datato InputInt high 14 bits 1
TCSLIIL Chip selectto InputInt low 35 ns
TCSLDrX Chip selectto bus active 5 ns
TCSLDrV Chip selectto data valid 50 ns
TCSHDrZ Chip select highto bus tristate 38 ns
TCSHDrX Data hold after chip select high 5 ns
TCSHLaV Chip de-selectto startof Ack 0.8 2.5 bits 1,2
Notes Unitof measurementis one link databit time;at10 Mbits/s data link speed, onebit timeis nomi-
nally 100 ns. Maximum time assumes thereisno data packet alreadyon the link. Maximum time with dataon
the linkis extendedby11 bits.
Table 6.3 IMS C011 Mode2 parallel interface read
Ack
DataData
TLdVIIH
TCSLIIL
TRSVCSL TCSLRSX
TRWVCSL TCSLRSX
TCSHDrZ
TCSHDrXTCSLDrX
TCSLDrV
TCSHLaV
LinkIn
InputInt
RS0–1
RnotW
notCS
D0–7
LinkOut
TCSLCSH TCSHCSL
