74F164D ,8-bit serial-in parallel-out shift registerPIN CONFIGURATION• Gated serial data inputsDsa 1 14 VCC• Typical shift frequency of 100MHzDsb 2 13 ..
74F164D ,8-bit serial-in parallel-out shift registerPIN CONFIGURATION• Gated serial data inputsDsa 1 14 VCC• Typical shift frequency of 100MHzDsb 2 13 ..
74F164N ,8-bit serial-in parallel-out shift registerPIN CONFIGURATION• Gated serial data inputsDsa 1 14 VCC• Typical shift frequency of 100MHzDsb 2 13 ..
74F169 ,4-bit up/down binary synchronous counter
74F169 ,4-bit up/down binary synchronous counterFeaturesYAsynchronous counting and loadingThe ’F169 is a fully synchronous 4-stage up/down counter. ..
74F169 ,4-bit up/down binary synchronous counter
74HCT32 ,74HCT32 Data SheetMAXIMUM RATINGSÎÎ Symbol Parameter Value UnitThis device contains protectioncircuitry to guard agai ..
74HCT32D ,74HC32; 74HCT32; Quad 2-input OR gatePin configuration DHVQFN145.2 Pin description Table 2. Pin descriptionSymbol Pin Description1A to 4 ..
74HCT32DB ,Quad 2-input OR gateGENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si- ..
74HCT32DB ,Quad 2-input OR gateGENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si- ..
74HCT32D-T , Quad 2-input OR gate
74HCT32N ,Quad 2-input OR gateGENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si- ..
74F164D-74F164N-I74F164D
8-bit serial-in parallel-out shift register
Product specification 1995 Sep 22
IC15 Data Handbook
Philips Semiconductors Product specification
74F1648-bit serial-in parallel-out shift register
FEATURES Gated serial data inputs Typical shift frequency of 100MHz Asynchronous Master Reset Buffered clock and data inputs Fully synchronous data transfer Industrial temperature range available (–40°C to +85°C)
DESCRIPTIONThe 74F164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
through one of two inputs (Dsa, Dsb); either input can be used as an
active High enable for data entry through the other input. Both inputs
must be connected together or an unused input must be tied High.
Data shifts one place to the right on each Low-to-High transition of
the clock (CP) input, and enters into Q0 the logical AND of the two
data inputs (Dsa, Dsb) that existed one setup time before the rising
edge. A Low level on the Master Reset (MR) input overrides all
other inputs and clears the register asynchronously, forcing all
outputs Low.
PIN CONFIGURATION
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN OUT TABLEOne (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
Philips Semiconductors Product specification
74F1648-bit serial-in parallel-out shift register
LOGIC DIAGRAM
FUNCTION TABLE= High voltage level= High voltage level one setup time prior to the Low-to-High clock transition.= Low voltage level = Low voltage level one setup time prior to the Low-to-High clock transition.= Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition.= Don’t care= Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74F1648-bit serial-in parallel-out shift register
DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)
Notes to DC electrical characteristics For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. All typical values are at VCC = 5V, Tamb = 25°C. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, IOS tests should be performed last. Measure ICC with the serial inputs grounded, the clock input at 2.4V, and a momentary ground, then applied to Master Reset, and all outputs
open.
APPLICATION
Philips Semiconductors Product specification
74F1648-bit serial-in parallel-out shift register
AC ELECTRICAL CHARACTERISTICS
AC SETUP REQUIREMENTS
AC WAVEFORMSFor all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1. Propagation delay for Clock input to output,
Clock Pulse width, and maximum Clock frequency
Waveform 3. Master Reset pulse width, Master Reset to output
delay and Master Reset to Clock recovery time
Philips Semiconductors Product specification
74F1648-bit serial-in parallel-out shift register
TEST CIRCUIT AND WAVEFORMS
