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HYB18RL25616AC-4-HYB18RL25616AC-5-HYB18RL25632AC-5
Specialty DRAMs
Graphics & Speciality DRAMs
256 Mbit DDR Reduced Latency DRAM
Version 1.60
July 2003
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Edition Jun. 2002This edition was realized using the software system FrameMaker.
Published by Infineon Technologies,
Marketing-Kommunikation,
Balanstraße 73,
81541 München© Infineon Technologies 6/30/2002.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits imple-mented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest In-
fineon Technologies Office.
Infineon Technologies is an approved CECC manufacturer.
PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing
material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of Infineon Technologies, may only be used in life-support devices or systems2 with the express written approval of Infineon Tech-nologies.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-
support device or system, or to affect its safety or effectiveness of that device or system.Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAMOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3Ball Configuration Package and Ballout . . . . . . . . . . . . . . . . . . . . . . .6
1.3.1Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.1Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.2Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.1Clocks, Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.3Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . .17
2.4Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.5Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.5.1Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.5.2Write - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.5.2.1Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.5.2.2Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.5.3Write Data Mask Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5.3.1Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5.3.2Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5.4Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.5.4.1Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.5.4.2Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.6Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.6.1Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.6.2Read - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.6.2.1Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.6.2.2Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.6.3Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . 293.1Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1.1Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1.2Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1.3Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1.4Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2.1Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2.2Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2.3Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2.4Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.3TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.4Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.4.1x16 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.4.2x32 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.5TAP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.6JTAG TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.7JTAG TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . .34
3.8JTAG DC Operating Conditons . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.9JTAG AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.10JTAG AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .35
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAMElectrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.2Recommended Power & DC Operation Ratings . . . . . . . . . . . . . . . .37
4.3AC Operation Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.4Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.5Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.6Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1Overview
1.1Features256 Megabit (256M)0.17µm process technologyCyclic bank addressing for maximum data out bandwidthOrganization 8M x 32, 16M x 16 in 8 banksNon-multiplexed addressesNon-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), DDR Up to 600Mb/sec/pin data rateProgrammable Read Latency (RL) of 5..6Data valid signal (DVLD) activated as Read Data is availableData Mask signals (DM0 / DM1) to mask first and second part of write data burst
z IEEE 1149.1 compliant JTAG Boundary Scan
z Pseudo-HSTL 1.8V IO Supply
z Internal autoprecharge
z Refresh requirements: 32ms at 100°C junction temperature (8k refresh for each bank, 64k refresh
commands must be issued in total each 32ms)
z Package T-FBGA 144
z 2.5V VEXT, 1.8V VDD, 1.8V VDDQ
Table 1Key timing parameters (Configuration Example x32, x16 device)
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.2General DescriptionThe Infineon 256M Reduced Latency DRAM (RLDRAM) contains 8 banks x 32 Mb of memory accessible
with 32bit or 16bit I/O’s in a double data rate (DDR) format where the data is provided and synchronized with
a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized
for fast random access and high data bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication
systems as well as data or instruction cache applications requiring large amounts of memory.
1.3Ball Configuration Package and Ballout
Figure 1T-FBGA 144 package 256 Mbit DDR Reduced Latency DRAM
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 2Ballout of 256 Mbit Reduced Latency DRAM (x32 configuration)
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 3Ballout of 256Mbit Reduced Latency DRAM (x16 configuration)
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAMNote:NC : No Connect : These signals are internally connected and have parasitic characterisitcs of an IO. They may optionally be
connected to ground for improved heat dissipation.
1.3.1Ball Description
Table 2Ball description
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Table 2Ball description
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.4Functional Block Diagram
Figure 4Functional Block Diagram 8M x 32 ConfigurationNote: When the BL4 setting is used, A18 is a "Don’t Care"
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 5Functional Block Diagram 16M x 16 ConfigurationNote:1 When the BL4 setting is used, A19 is a "Don’t Care".
Note:2 In the 16Mx16 configuration, only DQS[1:0] & DQS#[1:0] are used
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.5Commands
1.5.1Command TableAccording to the functional signal description the following command sequences are possible. All input
states or sequences not shown are illegal or reserved. All command and address inputs must meet setup
and hold times around the rising edge of CK.
Table 3 Truth tableNote:1: X = “Don’t Care” ; H = Logic HIGH; L = Logic LOW
Note:2: Only A[17:0] are used for the MRS command.
Note:3: See Table 4
Table 4 Address Width tableNote:1: The x32 and x16 configurations have different ballouts (see Fig. 2 & Fig. 3)
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.5.2Description of Commands
Table 5 Description of CommandsNote:1: Actual refresh is 32ms/8K/8 = 0.488µs
Note:2: Actual refresh is 32ms/8K = 3.90µs
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAMFunctional Description
2.1Clocks, Commands and Addresses
Figure 6Clock Command/Address Timings
Table 6General Timing Parameters for -2.5, -3.3 and -5.0 ns speed sorts Note:1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and
Address signals.
Note:2. The signal imput slew rate must be ≥ 1V/ns.
Note:3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.2InitializationThe RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation or permanent damage to the device.
The following sequence is used for Power-Up:Apply power (VEXT, VDD, VDDQ, VREF) and start clock as soon as the supply voltages are stable. ApplyDD and VEXT before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF.
There is no timing relation between VEXT and VDD, the chip starts the power up sequence only when
both voltages are at their nominal level. However, the pad supply must not be applied before the core
supplies. Maintain all pins in NOP conditions. Maintain stable conditions for 200 µs minimum. Issue three Mode Register Set commands - 2 dummies plus 1 valid MRS (Figure 7).After tMRSC issue 8 Auto Refresh commands, one on each bank and separated by 2048 cycles.After tRC the chip is ready for normal operation.
Figure 7Power Up Sequence
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.3Mode Register Set Command (MRS)The mode register stores the data for controlling the operating modes of
the memory. It programs the RLDRAM configuration, burst length, test
mode and IO options. During a Mode Register Set command the address
inputs A<17:0> are sampled and stored in the mode register. tMRSCmust be met before any command can be issued to the RLDRAM. The
mode register may be set anytime as long as all command are
completed, and the RLDRAM is in an idle state (no persistent
commands).
Figure 9Mode Register Set Timing
Table 7Timing Parameters MRS
Figure 10Mode Register BitmapNote:1 HSTL compliant current specification
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.4Configuration TableThe following table shows, for different operating frequencies, the different RLDRAM configurations that can
be programmed into the Mode Register. The Read Latency (tRL) and the Write Latency (tWL) used by the
RLDRAM for the two Burst Lengths (BL) are also indicated. Finally the minimum row cycle time (tRC) in clock
cycles and in ns are shown as well. The shaded areas correspond to configurations that are not allowed.
Note:1: The speed sort -3.3 provides parts functional up to 300MHz in the configuration 4 only. The functionality of the configurations
1,2 and 3 is not guaranteed for speed sort -3.3.
Note:2: The speed sort -4.0 provides parts functional up to 250MHz in the configurations 3 and 4 only. The functionality of the
configurations 1 and 2 is not guaranteed for speed sort -4.0.
Note:3: The speed sort -5.0 provides parts functional in all configurations.
Table 8RLDRAM configuration table
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5Writes (WR)
2.5.1Write - Basic InformationWrite accesses are initiated with a WRITE command, as shown in
Figure 11. Row and bank addresses are provided together with the
WRITE command.
During WRITE commands, data will be registered at both edges of CK
according to the programmed burst length BL. The first valid data is
registered with the first rising CK edge WL (Write Latency) cycles after
the WRITE command has been issued.
Any WRITE burst may be followed by a subsequent READ command.
Figure 17 and Figure 18 illustrate the timing requirements for a WRITE
followed by a READ for a burst of 2 and 4 respectively.
Setup and hold time for incoming DQs relative to the CK edges are
specified as tDS and tDH.
The first or the second part of the incoming data burst is masked if the
corresponding DMx signal is sampled HIGH along with the WRITE
command. Setup and hold time for DM is the same as for addresses
and commands.
Figure 12Basic Write Burst Timing
Table 9WRITE Timing Parameters Note:1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and
Address signals.
Note:2. The signal imput slew rate must be ≥ 1V/ns.
Note:3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
