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HCF4094BEYSTN/a6825avai8-STAGE SHIFT-AND-STORE BUS REGISTER
HCF4094BM1STN/a4847avai8-STAGE SHIFT-AND-STORE BUS REGISTER
HCF4094M013TRSTN/a13750avai8-STAGE SHIFT-AND-STORE BUS REGISTER


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HCF4094BEY-HCF4094BM1-HCF4094M013TR
8-STAGE SHIFT-AND-STORE BUS REGISTER
1/12October 2002 3- STATE PARALLEL OUTPUTS FOR
CONNECTION TO COMMON BUS SEPARATE SERIAL OUTPUTS
SYNCHRONOUS TO BOTH POSITIVE AND
NEGATIVE CLOCK EDGES FOR
CASCADING MEDIUM SPEED OPERATION 5MHzat 10V QUIESCENT CURRENT SPECIFIED UP TO
20V STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENTI= 100nA (MAX)ATVDD =18VTA= 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B" STANDARD SPECIFICATIONS
FOR DESCRIPTION OFB SERIES CMOS
DEVICES"
DESCRIPTION

The HCF4094Bisa monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology availablein DIP and SOP packages.
The HCF4094Bisan8 stages serial shift register
havinga storage latch associated with each stage
for strobing data from the serial inputto parallel
buffered 3-state outputs. The parallel outputs may connected directlyto common bus lines. Data shifted on positive clock transition. The datain
each shift register stageis transferred to the
storage register when the STROBE inputis high.
Datain the storage register appearsat the outputs
whenever the OUTPUT-ENABLE signalis high.
Two serial outputs are available for cascadinga
numberof HCF4094B devices. Datais available the QS serial output terminalon positive clock
edges to allow for high speed operation in
cascaded systemin which the clock rise timeis
fast. The same serial information, availableat theS terminal on the next negative clock edge,
providesa means for cascading HCF4094B
devices when the clock rise timeis slow.
HCF4094B
STAGE SHIFT AND STORE BUS REGISTER
WITH 3-STATE OUTPUTS
PIN CONNECTION
ORDER CODES
HCF4094B
2/12
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE
: Don’t Care: Open CircuitAtthe positive clock edge informationonthe7th shift register stageis transferredtothe8th register stageandtheQS output.
HCF4094B
3/12
LOGIC DIAGRAM
TIMING CHART
HCF4094B
4/12
ABSOLUTE MAXIMUM RATINGS

AbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied.
All voltage valuesare referredto VSSpin voltage.
(*) 500mWat65°C; derateto 300mWby 10mW/°Cfrom 65°Cto85°C
RECOMMENDED OPERATING CONDITIONS
HCF4094B
5/12 SPECIFICATIONS
The Noise Marginfor both"1"and"0" levelis:1V min. with VDD=5V,2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4094B
6/12
DYNAMIC ELECTRICAL CHARACTERISTICS
(T amb= 25°C,CL= 50pF,RL= 200KΩ,tr=tf =20ns)
(*) Typical temperature coefficientforall VDD valueis0.3 %/°C.
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