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HCF4020BEY-HCF4020BM1-HCF4020M013TR
14 STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDERS
1/10September 2002 MEDIUM SPEED OPERATION :
16MHz (Typ.) at VDD = 10V FULLY STATIC OPERATION COMMON RESET BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO
20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONHCF4020B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4020B is a ripple carry binary counter. All
counter stages are master-slave flip-flops. The
state of a counter advances one count on the
negative transition of each input pulse; a high level
on the RESET line resets the counter to its all
zeros stage. Schmitt trigger action on the input
pulse line permits unlimited clock rise and fall
times.
All inputs and outputs are buffered.
HCF4020BRIPPLE-CARRY BINARY COUNTER/DIVIDERS 14 STAGE
PIN CONNECTION
ORDER CODES
HCF4020B2/10
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM
HCF4020B3/10
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4020B4/10
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4020B5/10
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
HCF4020B6/10
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : MINIMUM PULSE WIDTH (RESET) AND REMOVAL TIME ( RESET TO Φ) (f=1MHz; 50% duty cycle)
