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GTLP8T306MTCFAIRCHILN/a188avai8-Bit LVTTL-to-GTLP Bus Transceiver
GTLP8T306MTCFAIRCHILDN/a128avai8-Bit LVTTL-to-GTLP Bus Transceiver
GTLP8T306MTCXFAICHN/a2200avai8-Bit LVTTL-to-GTLP Bus Transceiver
GTLP8T306MTCXFAIN/a622avai8-Bit LVTTL-to-GTLP Bus Transceiver


GTLP8T306MTCX ,8-Bit LVTTL-to-GTLP Bus TransceiverFeaturesThe GTLP8T306 is an 8-bit bus transceiver that provides

GTLP8T306MTC-GTLP8T306MTCX
8-Bit LVTTL-to-GTLP Bus Transceiver
GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver September 1997 Revised December 2000 GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver General Description Features The GTLP8T306 is an 8-bit bus transceiver that providesBidirectional interface between GTLP and LVTTL logic LVTTL to GTLP signal level translation. The device pro- levels vides a high speed interface between cards operating atDesigned with edge rate control circuitry to reduce out- LVTTL logic levels and a backplane operating at GTLP put noise on the GTLP port logic levels. High speed backplane operation is a direct V pin provides external supply reference voltage for REF result of GTLP’s reduced output swing (<1V), reduced input receiver threshold adjustibility threshold levels and output edge rate control. The edge Special PVT Compensation circuitry to provide consis- rate control minimizes bus settling time. GTLP is a Fairchild tent performance over variations of process, supply volt- Semiconductor derivative of the Gunning Transceiver logic age and temperature (GTL) JEDEC standard JESD8-3. TTL compatible driver and control inputs Fairchild’s GTLP has internal output edge-rate control and is process, voltage, and temperature (PVT) compensated.Designed using Fairchild advanced CMOS technology Its function is similar to BTL and GTL but with different out- Bushold data inputs on A port to eliminate the need for put levels and receiver thresholds. The GTLP output LOW external pull-up resistors for unused inputs level is typically less than 0.5V, the output HIGH level is Power up/down and power off high impedance for live 1.5V and the receiver threshold is 1.0V. insertion 5V over voltage tolerance on LVTTL ports Open drain on GTLP to support wired-or connection Flow through pinout optimizes PCB layout A Port source/sink −24mA/+24mA B Port sink +50mA Ordering Code: Order Number Package Number Package Description GTLP8T306MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS500051
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