GTLP18T612MTD ,18-Bit LVTTL/GTLP Universal Bus TransceiverGTLP18T612 18-Bit LVTTL/GTLP Universal Bus TransceiverMay 1999Revised July 2002GTLP18T61218-Bit LVT ..
GTLP18T612MTD ,18-Bit LVTTL/GTLP Universal Bus TransceiverFeaturesThe GTLP18T612 is an 18-bit universal bus transceiver
GTLP18T612MEA-GTLP18T612MTD-GTLP18T612MTDX
18-Bit LVTTL/GTLP Universal Bus Transceiver
GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver May 1999 Revised July 2002 GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver General Description Features The GTLP18T612 is an 18-bit universal bus transceiverBidirectional interface between GTLP and LVTTL logic which provides LVTTL to GTLP signal level translation. It levels allows for transparent, latched and clocked modes of dataDesigned with edge rate control circuitry to reduce out- transfer. The device provides a high speed interface for put noise on the GTLP port cards operating at LVTTL logic levels and a backplane V pin provides external supply reference voltage for REF operating at GTLP logic levels. High speed backplane receiver threshold adjustibility operation is a direct result of GTLP’s reduced output swing Special PVT compensation circuitry to provide consis- (< 1V), reduced input threshold levels and output edge rate tent performance over variations of process, supply volt- control. The edge rate control minimizes bus settling time. age and temperature GTLP is a Fairchild Semiconductor derivative of the Gun- ning Transistor logic (GTL) JEDEC standard JESD8-3.TTL compatible driver and control inputs Fairchild’s GTLP has internal edge-rate control and is Pro-Designed using Fairchild advanced BiCMOS technology cess, Voltage, and Temperature (PVT) compensated. Its Bushold data inputs on A port to eliminate the need for function is similar to BTL or GTL but with different output external pull-up resistors for unused inputs levels and receiver thresholds. GTLP output LOW level is Power up/down and power off high impedance for live less than 0.5V, the output HIGH is 1.5V and the receiver insertion threshold is 1.0V. Open drain on GTLP to support wired-or connection Flow through pinout optimizes PCB layout D-type flip-flop, latch and transparent data paths A Port source/sink −24mA/+24mA B Port sink +50mA Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Order Number Package Number Package Description GTLP18T612G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) GTLP18T612MEA 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide MS56A (Note 2) GTLP18T612MTD 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide MTD56 (Note 2) Note 1: Ordering code “G” indicates Trays. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2002 DS500169
