GTLP16612 ,CMOS 18-Bit GTL/TTL Universal Bus TransceiverGTLP16612CMOS18-BitGTLP/TTLUniversalBusTransceiverOctober1996GTLP16612CMOS18-BitGTLP/TTLUniversalBu ..
GTLP16612MEA ,CMOS 18-Bit TTL/GTLP Universal Bus TransceiverGTLP16612 18-Bit TTL/GTLP Universal Bus TransceiverMarch 1995Revised March 2001GTLP1661218-Bit TTL/ ..
GTLP16612MEAX ,CMOS 18-Bit TTL/GTLP Universal Bus TransceiverGTLP16612 18-Bit TTL/GTLP Universal Bus TransceiverMarch 1995Revised March 2001GTLP1661218-Bit TTL/ ..
GTLP16612MEAX ,CMOS 18-Bit TTL/GTLP Universal Bus TransceiverFeaturesThe GTLP16612 is an 18-bit universal bus transceiver
GTLP16612
CMOS 18-Bit GTL/TTL Universal Bus Transceiver
TL/F/12390
GTLP16612
CMOS
18-Bit
GTLP/TTL
Universal
Bus
Transceiver
October 1996
GTLP16612
CMOS 18-Bit GTLP/TTL Universal Bus Transceiver
General Description
The GTLP16612isan 18-bit universalbustransceiverwhich
providesTTLto GTLP signal level translation.The deviceis
designedto providea high speed interface between cards
operatingat TTL logic levelsanda backplane operatingat
GTLP logic levels. High speed backplane operationisadi-
rect resultof GTLP’s reduced output swing (k1V), reduced
input threshold levelsand output edge rate control which
minimizes signal settling times. GTLPisa National Semi-
conductor derivativeof the Gunning Transceiver Logic
(GTL) JEDEC standard JESD8-3.
National’s GTLPhas internal edge-rate controlandis Pro-
cess, Voltage, and Temperature (PVT) compensated.Its
functionis similarto BTLor GTLbut with different driver
output levelsand receiver threshold. GTLP outputlow volt-
ageis typically 0.5V, theoutput high is1.5Vand thereceiver
thresholdis 1.0V.
Features Bidirectional interface between GTLP and TTL logic
levels Designed with Edge Rate Control Circuitto reduce out-
put noise VREFpin provides external supply reference voltagefor
receiver threshold Submicron Core CMOS technologyforlow power dissi-
pation Special PVT Compensation circuitryto provide consist-
ent performance over variationsof process, supply volt-
ageand temperature5V tolerant inputsand outputson A-port Bus-Hold data inputson A-portto eliminatethe need
for external pull-up resistorsfor unused inputs Power up/down high impedance TTL compatible Driverand Control inputs A-port outputs source/sink b32 mA/a32mA Flow-through architecture optimizes PCB layout Open drainon GTLPto support wired-or connection Availablein SSOP
Pin Descriptions
PinNames Description
OEAB A-to-B Output Enable (ActiveLOW)
OEBA B-to-A Output Enable (ActiveLOW)
CEAB A-to-B ClockEnable (Active LOW)
CEBA B-to-A ClockEnable (Active LOW)
LEAB A-to-B Latch Enable (Active HIGH)
LEBA B-to-A Latch Enable (Active HIGH)
CLKAB A-to-B ClockPulse
CLKBA B-to-A ClockPulse
VREF GTLP InputReference Voltage
A1–A18 A-to-BTTL Data Inputsor
B-to-A TRI-STATEÉ Outputs
B1–B18 B-to-A GTLP Data Inputsor
A-to-B Open Drain Outputs
Connection Diagram
PinAssignmentfor SSOP
TL/F/12390–2
Order Number GTLP16612MEA
SeeNS PackageNumberMS56A
TRI-STATEÉ isaRegisteredTrademarkof National Semiconductor Corporation.
C1996National SemiconductorCorporation RRD-B30M17/Printed inU.S.A. http://
