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FQP2P40FAIRCHILDN/a500avai400V P-Channel MOSFET


FQP2P40 ,400V P-Channel MOSFETFQP2P40December 2000TMQFET QFET QFET QFETFQP2P40400V P-Channel MOSFET
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FQP2P40
400V P-Channel MOSFET
FQP2P40 December 2000 TM QFET QFET QFET QFET FQP2P40 400V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect  -2.0A, -400V, R = 6.5Ω @V = -10 V DS(on) GS transistors are produced using Fairchild’s proprietary,  Low gate charge ( typical 10 nC) planar stripe, DMOS technology.  Low Crss ( typical 6.5 pF) This advanced technology is especially tailored to minimize  Fast switching on-state resistance, provide superior switching  100% avalanche tested performance, and withstand a high energy pulse in the  Improved dv/dt capability avalanche and commutation modes. These devices are well suited for electronic lamp ballasts based on the complementary half bridge topology. S !!!!!!!! ●●●● ●●●● G!!!!!!!! ●●●●●●●● ▶▶▶▶ ▶▶▶▶ ▲▲▲▲▲▲▲▲ ●●●● ●●●● G D TO-220 S FQP Series !!!! !!!! D Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FQP2P40 Units V Drain-Source Voltage -400 V DSS I - Continuous (T = 25°C) Drain Current -2.0 A D C - Continuous (T = 100°C) -1.27 A C I (Note 1) Drain Current - Pulsed -8.0 A DM V Gate-Source Voltage ± 30 V GSS E (Note 2) Single Pulsed Avalanche Energy 120 mJ AS I Avalanche Current (Note 1) -2.0 A AR E (Note 1) Repetitive Avalanche Energy 6.3 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) -4.5 V/ns P Power Dissipation (T = 25°C) 63 W D C - Derate above 25°C 0.51 W/°C T , T Operating and Storage Temperature Range -55 to +150 °C J STG Maximum lead temperature for soldering purposes, T 300 °C L 1/8” from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 1.98 °C/W θJC R Thermal Resistance, Case-to-Sink 0.5 -- °C/W θCS R Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W θJA ©2000 Fairchild Semiconductor International Rev. A2, December 2000
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