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FQB17N08FAIRCHILN/a4800avai80V N-Channel MOSFET


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FQB17N08
80V N-Channel MOSFET
FQB17N08 / FQI17N08 January 2001 TM QFET QFET QFET QFET FQB17N08 / FQI17N08 80V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect  16.5A, 80V, R = 0.115Ω @V = 10 V DS(on) GS transistors are produced using Fairchild’s proprietary,  Low gate charge ( typical 12 nC) planar stripe, DMOS technology.  Low Crss ( typical 28 pF) This advanced technology has been especially tailored to  Fast switching minimize on-state resistance, provide superior switching  100% avalanche tested performance, and withstand a high energy pulse in the  Improved dv/dt capability avalanche and commutation modes. These devices are  175°C maximum junction temperature rating well suited for low voltage applications such as automotive, high efficiency switching for DC/DC converters, and DC motor control. D D ! ! "" !!"" "" G! ! "" G S 2 2 D -PAK I -PAK G D S ! ! FQB Series FQI Series S Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FQB17N08 / FQI17N08 Units V Drain-Source Voltage 80 V DSS I - Continuous (T = 25°C) Drain Current 16.5 A D C - Continuous (T = 100°C) 11.6 A C I (Note 1) Drain Current - Pulsed 66 A DM V Gate-Source Voltage ± 25 V GSS E (Note 2) Single Pulsed Avalanche Energy 100 mJ AS I Avalanche Current (Note 1) 16.5 A AR E (Note 1) Repetitive Avalanche Energy 6.5 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) 6.5 V/ns Power Dissipation (T = 25°C) * 3.13 W P A D Power Dissipation (T = 25°C) 65 W C - Derate above 25°C 0.43 W/°C T , T Operating and Storage Temperature Range -55 to +150 °C J STG Maximum lead temperature for soldering purposes, T 300 °C L 1/8" from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 2.31 °C/W θJC R Thermal Resistance, Junction-to-Ambient * -- 40 °C/W θJA R Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W θJA * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A1, January 2001
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