FIN1026 ,3.3V LVDS 2-Bit High Speed Differential ReceiverFeaturesThis dual receiver is designed for high speed interconnects
FIN1026
3.3V LVDS 2-Bit High Speed Differential Receiver
FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver June 2002 Revised June 2002 FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver General Description Features This dual receiver is designed for high speed interconnectsGreater than 400Mbs data rate utilizing Low Voltage Differential Signaling (LVDS) technol-Flow-through pinout simplifies PCB layout ogy. The receiver translates LVDS levels, with a typical dif- 3.3V power supply operation ferential input threshold of 100mV, to LVTTL signal levels. 0.4ns maximum differential pulse skew LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed2.5ns maximum propagation delay transfer of clock and data.Low power dissipation The FIN1026 can be paired with its companion driver, thePower-Off protection FIN1025, or any other LVDS driver. Fail safe protection for open-circuit, shorted and termi- nated non-driven input conditions Meets or exceeds the TIA/EIA-644 LVDS standard 14-Lead TSSOP package saves space Ordering Code: Order Number Package Number Package Description FIN1026MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Description R , R LVTTL Data Outputs OUT1 OUT2 R , R Non-Inverting LVDS Inputs IN1+ IN2+ R , R Inverting LVDS Inputs IN1− IN2− EN Driver Enable Pin EN Inverting Driver Enable Pin V Power Supply CC GND Ground NC No Connect Truth Table Inputs Outputs EN EN R R R IN+ IN− OUT HL or Open H L H HL or Open L H L H L or Open Fail Safe Condition H XH X X Z L or Open X X X Z H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Fail Safe = Open, Shorted, Terminated © 2002 DS500784
