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FDS6912FAIRCHILN/a2500avaiDual N-Channel Logic Level PWM Optimized PowerTrench MOSFET


FDS6912 ,Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFETFeaturesThese N-Channel Logic Level MOSFETs have been • 6 A, 30 V. R = 0.028 Ω @ V = 10 VDS(ON) GSd ..
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FDS6912
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
FDS6912 July 2000 FDS6912     Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET General Description Features These N-Channel Logic Level MOSFETs have been • 6 A, 30 V. R = 0.028 Ω @ V = 10 V DS(ON) GS designed specifically to improve the overall efficiency of R = 0.042 Ω @ V = 4.5 V. DS(ON) GS DC/DC converters using either synchronous or • Optimized for use in switching DC/DC converters conventional switching PWM controllers. with PWM controllers These MOSFETs feature faster switching and lower gate charge than other MOSFETs with comparable • Very fast switching. RDS(ON) specifications. • Low gate charge The result is a MOSFET that is easy and safer to drive (even at very high frequencies), and DC/DC power supply designs with higher overall efficiency. D1 5 4 D1 D2 Q1 6 3 D2 7 2 Q2 G1 8 1 S1 SO-8 G2 S2 o T =25 C unless otherwise noted Absolute Maximum Ratings A Symbol Parameter Ratings Units V Drain-Source Voltage 30 V DSS V Gate-Source Voltage V GSS ±25 I Drain Current – Continuous (Note 1a) 6A D – Pulsed 20 P W D Power Dissipation for Dual Operation 2 Power Dissipation for Single Operation (Note 1a) 1.6 (Note 1b) 1 (Note 1c) 0.9 T , T Operating and Storage Junction Temperature Range -55 to +150 °C J stg Thermal Characteristics (Note 1a) R Thermal Resistance, Junction-to-Ambient 78 °C/W θJA Thermal Resistance, Junction-to-Case (Note 1) 40 R °C/W θJC Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS6912 FDS6912 13’’ 12mm 2500 units FDS6912 Rev F (W) 2000
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